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Searched refs:Periphs (Results 1 – 25 of 40) sorted by relevance

12

/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_bus.h566 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) in LL_AHB3_GRP1_EnableClock() argument
569 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
571 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
616 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB3_GRP1_IsEnabledClock() argument
618 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB3_GRP1_IsEnabledClock()
662 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) in LL_AHB3_GRP1_DisableClock() argument
664 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
698 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) in LL_AHB3_GRP1_ForceReset() argument
700 SET_BIT(RCC->AHB3RSTR, Periphs); in LL_AHB3_GRP1_ForceReset()
734 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB3_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_bus.h287 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
290 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
292 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
309 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
311 return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
327 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
329 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
346 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
348 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
365 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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Dstm32wlxx_ll_system.h1255 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_FreezePeriph() argument
1257 SET_BIT(DBGMCU->APB1FZR1, Periphs); in LL_DBGMCU_APB1_GRP1_FreezePeriph()
1274 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) in LL_C2_DBGMCU_APB1_GRP1_FreezePeriph() argument
1276 SET_BIT(DBGMCU->C2APB1FZR1, Periphs); in LL_C2_DBGMCU_APB1_GRP1_FreezePeriph()
1289 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP2_FreezePeriph() argument
1291 SET_BIT(DBGMCU->APB1FZR2, Periphs); in LL_DBGMCU_APB1_GRP2_FreezePeriph()
1304 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) in LL_C2_DBGMCU_APB1_GRP2_FreezePeriph() argument
1306 SET_BIT(DBGMCU->C2APB1FZR2, Periphs); in LL_C2_DBGMCU_APB1_GRP2_FreezePeriph()
1323 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_UnFreezePeriph() argument
1325 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); in LL_DBGMCU_APB1_GRP1_UnFreezePeriph()
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/hal_stm32-3.5.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_bus.h334 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) in LL_AHB2_GRP1_EnableClock() argument
337 WRITE_REG(RCC->MC_AHB2ENSETR, Periphs); in LL_AHB2_GRP1_EnableClock()
339 tmpreg = READ_BIT(RCC->MC_AHB2ENSETR, Periphs); in LL_AHB2_GRP1_EnableClock()
360 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB2_GRP1_IsEnabledClock() argument
362 return (READ_BIT(RCC->MC_AHB2ENSETR, Periphs) == Periphs); in LL_AHB2_GRP1_IsEnabledClock()
382 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) in LL_AHB2_GRP1_DisableClock() argument
384 WRITE_REG(RCC->MC_AHB2ENCLRR, Periphs); in LL_AHB2_GRP1_DisableClock()
405 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) in LL_AHB2_GRP1_ForceReset() argument
407 WRITE_REG(RCC->AHB2RSTSETR, Periphs); in LL_AHB2_GRP1_ForceReset()
428 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB2_GRP1_ReleaseReset() argument
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Dstm32mp1xx_ll_system.h1059 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_FreezePeriph() argument
1061 SET_BIT(DBGMCU->APB1FZ2, Periphs); in LL_DBGMCU_APB1_GRP1_FreezePeriph()
1099 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_UnFreezePeriph() argument
1101 CLEAR_BIT(DBGMCU->APB1FZ2, Periphs); in LL_DBGMCU_APB1_GRP1_UnFreezePeriph()
1121 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB2_GRP1_FreezePeriph() argument
1123 SET_BIT(DBGMCU->APB2FZ2, Periphs); in LL_DBGMCU_APB2_GRP1_FreezePeriph()
1143 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB2_GRP1_UnFreezePeriph() argument
1145 CLEAR_BIT(DBGMCU->APB2FZ2, Periphs); in LL_DBGMCU_APB2_GRP1_UnFreezePeriph()
1161 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB3_GRP1_FreezePeriph() argument
1163 SET_BIT(DBGMCU->APB3FZ2, Periphs); in LL_DBGMCU_APB3_GRP1_FreezePeriph()
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/hal_stm32-3.5.0/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_bus.h364 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
367 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
369 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
389 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
391 return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
410 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
412 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
432 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
434 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
454 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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Dstm32wbxx_ll_system.h1668 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_FreezePeriph() argument
1670 SET_BIT(DBGMCU->APB1FZR1, Periphs); in LL_DBGMCU_APB1_GRP1_FreezePeriph()
1685 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) in LL_C2_DBGMCU_APB1_GRP1_FreezePeriph() argument
1687 SET_BIT(DBGMCU->C2APB1FZR1, Periphs); in LL_C2_DBGMCU_APB1_GRP1_FreezePeriph()
1697 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP2_FreezePeriph() argument
1699 SET_BIT(DBGMCU->APB1FZR2, Periphs); in LL_DBGMCU_APB1_GRP2_FreezePeriph()
1709 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) in LL_C2_DBGMCU_APB1_GRP2_FreezePeriph() argument
1711 SET_BIT(DBGMCU->C2APB1FZR2, Periphs); in LL_C2_DBGMCU_APB1_GRP2_FreezePeriph()
1727 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_UnFreezePeriph() argument
1729 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); in LL_DBGMCU_APB1_GRP1_UnFreezePeriph()
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/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_bus.h227 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
230 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
232 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
258 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
260 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
285 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
287 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
304 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
306 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
323 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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Dstm32wbaxx_ll_system.h781 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_FreezePeriph() argument
783 SET_BIT(DBGMCU->APB1LFZR, Periphs); in LL_DBGMCU_APB1_GRP1_FreezePeriph()
793 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP2_FreezePeriph() argument
795 SET_BIT(DBGMCU->APB1HFZR, Periphs); in LL_DBGMCU_APB1_GRP2_FreezePeriph()
809 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_UnFreezePeriph() argument
811 CLEAR_BIT(DBGMCU->APB1LFZR, Periphs); in LL_DBGMCU_APB1_GRP1_UnFreezePeriph()
821 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP2_UnFreezePeriph() argument
823 CLEAR_BIT(DBGMCU->APB1HFZR, Periphs); in LL_DBGMCU_APB1_GRP2_UnFreezePeriph()
835 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB2_GRP1_FreezePeriph() argument
837 SET_BIT(DBGMCU->APB2FZR, Periphs); in LL_DBGMCU_APB2_GRP1_FreezePeriph()
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/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_bus.h425 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
428 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
430 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
476 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
478 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
534 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
536 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
570 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
572 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
607 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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Dstm32u5xx_ll_system.h1258 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_FreezePeriph() argument
1260 SET_BIT(DBGMCU->APB1FZR1, Periphs); in LL_DBGMCU_APB1_GRP1_FreezePeriph()
1274 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP2_FreezePeriph() argument
1276 SET_BIT(DBGMCU->APB1FZR2, Periphs); in LL_DBGMCU_APB1_GRP2_FreezePeriph()
1295 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP1_UnFreezePeriph() argument
1297 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); in LL_DBGMCU_APB1_GRP1_UnFreezePeriph()
1308 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB1_GRP2_UnFreezePeriph() argument
1310 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); in LL_DBGMCU_APB1_GRP2_UnFreezePeriph()
1324 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) in LL_DBGMCU_APB2_GRP1_FreezePeriph() argument
1326 SET_BIT(DBGMCU->APB2FZR, Periphs); in LL_DBGMCU_APB2_GRP1_FreezePeriph()
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/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_bus.h542 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
545 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
547 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
587 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
589 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
628 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
630 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
657 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
659 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
686 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_bus.h243 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
246 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
248 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
271 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
273 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
295 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
297 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
320 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
322 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
345 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_bus.h221 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
224 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
226 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
249 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
251 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
274 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
276 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
297 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
299 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
320 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_bus.h327 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
330 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
332 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
359 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
361 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
387 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
389 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
416 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
418 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
445 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_bus.h238 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
241 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
243 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
292 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
294 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
342 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
344 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
383 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
385 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
424 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_bus.h309 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
312 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
314 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
371 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
373 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
429 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
431 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
476 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
478 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
523 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_bus.h409 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
412 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
414 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
473 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
475 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
533 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
535 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
582 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
584 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
631 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_bus.h158 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
161 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
163 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
178 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
180 return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
194 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
196 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
211 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
213 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
228 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_bus.h222 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
225 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
227 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
250 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
252 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
274 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
276 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
299 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
301 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
324 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_bus.h250 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
253 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
255 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
275 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
277 return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
296 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
298 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
318 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
320 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
340 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_bus.h214 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
217 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
219 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
258 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
260 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
298 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
300 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
339 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
341 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
380 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_bus.h225 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
228 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
230 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
265 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
267 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
301 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
303 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
328 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
330 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
355 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_bus.h269 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
272 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
274 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
307 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
309 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
341 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
343 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
359 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
361 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
376 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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/hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_bus.h285 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
288 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
290 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
337 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
339 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
385 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
387 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
424 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
426 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
463 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
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