1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2016 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32L0xx_LL_BUS_H
37 #define __STM32L0xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32l0xx.h"
45
46 /** @addtogroup STM32L0xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58
59 /* Private constants ---------------------------------------------------------*/
60
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */
74 #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */
75 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable */
76 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */
77 #if defined(TSC)
78 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */
79 #endif /*TSC*/
80 #if defined(RNG)
81 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */
82 #endif /*RNG*/
83 #if defined(AES)
84 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */
85 #endif /*AES*/
86 /**
87 * @}
88 */
89
90
91 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
92 * @{
93 */
94 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
95 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */
96 #if defined(TIM3)
97 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */
98 #endif
99 #if defined(TIM6)
100 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */
101 #endif
102 #if defined(TIM7)
103 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */
104 #endif
105 #if defined(LCD)
106 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */
107 #endif /*LCD*/
108 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */
109 #if defined(SPI2)
110 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */
111 #endif
112 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */
113 #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */
114 #if defined(USART4)
115 #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */
116 #endif
117 #if defined(USART5)
118 #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */
119 #endif
120 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */
121 #if defined(I2C2)
122 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */
123 #endif
124 #if defined(USB)
125 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */
126 #endif /*USB*/
127 #if defined(CRS)
128 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */
129 #endif /*CRS*/
130 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */
131 #if defined(DAC)
132 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */
133 #endif
134 #if defined(I2C3)
135 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */
136 #endif
137 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */
138 /**
139 * @}
140 */
141
142
143
144
145 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
146 * @{
147 */
148 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
149 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */
150 #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */
151 #if defined(TIM22)
152 #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */
153 #endif
154 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */
155 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */
156 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */
157 #if defined(USART1)
158 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */
159 #endif
160 #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */
161
162 /**
163 * @}
164 */
165
166
167
168 /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
169 * @{
170 */
171 #define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
172 #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */
173 #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */
174 #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */
175 #if defined(GPIOD)
176 #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */
177 #endif /*GPIOD*/
178 #if defined(GPIOE)
179 #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */
180 #endif /*GPIOE*/
181 #if defined(GPIOH)
182 #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */
183 #endif /*GPIOH*/
184 /**
185 * @}
186 */
187
188
189 /**
190 * @}
191 */
192
193 /* Exported macro ------------------------------------------------------------*/
194 /* Exported functions --------------------------------------------------------*/
195 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
196 * @{
197 */
198
199 /** @defgroup BUS_LL_EF_AHB1 AHB1
200 * @{
201 */
202
203 /**
204 * @brief Enable AHB1 peripherals clock.
205 * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n
206 * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n
207 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
208 * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n
209 * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n
210 * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock
211 * @param Periphs This parameter can be a combination of the following values:
212 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
213 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
214 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
215 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
216 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
217 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
218 *
219 * (*) value not defined in all devices.
220 * @retval None
221 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)222 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
223 {
224 __IO uint32_t tmpreg;
225 SET_BIT(RCC->AHBENR, Periphs);
226 /* Delay after an RCC peripheral clock enabling */
227 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
228 (void)tmpreg;
229 }
230
231 /**
232 * @brief Check if AHB1 peripheral clock is enabled or not
233 * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n
234 * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n
235 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
236 * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
237 * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
238 * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock
239 * @param Periphs This parameter can be a combination of the following values:
240 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
241 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
242 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
243 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
244 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
245 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
246 *
247 * (*) value not defined in all devices.
248 * @retval State of Periphs (1 or 0).
249 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)250 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
251 {
252 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL);
253 }
254
255 /**
256 * @brief Disable AHB1 peripherals clock.
257 * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n
258 * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n
259 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
260 * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n
261 * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n
262 * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock
263 * @param Periphs This parameter can be a combination of the following values:
264 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
265 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
266 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
267 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
268 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
269 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
270 *
271 * (*) value not defined in all devices.
272 * @retval None
273 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)274 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
275 {
276 CLEAR_BIT(RCC->AHBENR, Periphs);
277 }
278
279 /**
280 * @brief Force AHB1 peripherals reset.
281 * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n
282 * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n
283 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
284 * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n
285 * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n
286 * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset
287 * @param Periphs This parameter can be a combination of the following values:
288 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
289 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
290 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
291 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
292 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
293 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
294 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
295 *
296 * (*) value not defined in all devices.
297 * @retval None
298 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)299 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
300 {
301 SET_BIT(RCC->AHBRSTR, Periphs);
302 }
303
304 /**
305 * @brief Release AHB1 peripherals reset.
306 * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n
307 * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n
308 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
309 * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
310 * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
311 * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset
312 * @param Periphs This parameter can be a combination of the following values:
313 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
314 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
315 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
316 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
317 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
318 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
319 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
320 *
321 * (*) value not defined in all devices.
322 * @retval None
323 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)324 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
325 {
326 CLEAR_BIT(RCC->AHBRSTR, Periphs);
327 }
328
329 /**
330 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
331 * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n
332 * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n
333 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n
334 * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n
335 * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n
336 * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n
337 * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep
338 * @param Periphs This parameter can be a combination of the following values:
339 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
340 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
341 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
342 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
343 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
344 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
345 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
346 *
347 * (*) value not defined in all devices.
348 * @retval None
349 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)350 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
351 {
352 __IO uint32_t tmpreg;
353 SET_BIT(RCC->AHBSMENR, Periphs);
354 /* Delay after an RCC peripheral clock enabling */
355 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
356 (void)tmpreg;
357 }
358
359 /**
360 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
361 * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n
362 * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n
363 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n
364 * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n
365 * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n
366 * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n
367 * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep
368 * @param Periphs This parameter can be a combination of the following values:
369 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
370 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
371 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
372 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
373 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
374 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
375 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
376 *
377 * (*) value not defined in all devices.
378 * @retval None
379 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)380 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
381 {
382 CLEAR_BIT(RCC->AHBSMENR, Periphs);
383 }
384
385 /**
386 * @}
387 */
388
389 /** @defgroup BUS_LL_EF_APB1 APB1
390 * @{
391 */
392
393 /**
394 * @brief Enable APB1 peripherals clock.
395 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
396 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
397 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
398 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
399 * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n
400 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
401 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
402 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
403 * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n
404 * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
405 * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
406 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
407 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
408 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
409 * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
410 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
411 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
412 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
413 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock
414 * @param Periphs This parameter can be a combination of the following values:
415 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
416 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
417 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
418 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
419 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
420 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
421 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
422 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
423 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
424 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
425 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
426 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
427 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
428 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
429 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
430 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
431 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
432 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
433 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
434 *
435 * (*) value not defined in all devices.
436 * @retval None
437 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)438 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
439 {
440 __IO uint32_t tmpreg;
441 SET_BIT(RCC->APB1ENR, Periphs);
442 /* Delay after an RCC peripheral clock enabling */
443 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
444 (void)tmpreg;
445 }
446
447 /**
448 * @brief Check if APB1 peripheral clock is enabled or not
449 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
450 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
451 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
452 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
453 * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n
454 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
455 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
456 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
457 * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n
458 * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
459 * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
460 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
461 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
462 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
463 * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
464 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
465 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
466 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
467 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock
468 * @param Periphs This parameter can be a combination of the following values:
469 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
470 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
471 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
472 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
473 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
474 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
475 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
476 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
477 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
478 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
479 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
480 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
481 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
482 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
483 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
484 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
485 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
486 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
487 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
488 *
489 * (*) value not defined in all devices.
490 * @retval State of Periphs (1 or 0).
491 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)492 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
493 {
494 return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
495 }
496
497 /**
498 * @brief Disable APB1 peripherals clock.
499 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
500 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
501 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
502 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
503 * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n
504 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
505 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
506 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
507 * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n
508 * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
509 * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
510 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
511 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
512 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
513 * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
514 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
515 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
516 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
517 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock
518 * @param Periphs This parameter can be a combination of the following values:
519 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
520 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
521 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
522 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
523 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
524 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
525 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
526 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
527 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
528 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
529 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
530 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
531 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
532 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
533 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
534 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
535 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
536 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
537 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
538 *
539 * (*) value not defined in all devices.
540 * @retval None
541 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)542 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
543 {
544 CLEAR_BIT(RCC->APB1ENR, Periphs);
545 }
546
547 /**
548 * @brief Force APB1 peripherals reset.
549 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
550 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
551 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
552 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
553 * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n
554 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
555 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
556 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
557 * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n
558 * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
559 * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
560 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
561 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
562 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
563 * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
564 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
565 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
566 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
567 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset
568 * @param Periphs This parameter can be a combination of the following values:
569 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
570 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
571 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
572 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
573 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
574 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
575 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
576 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
577 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
578 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
579 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
580 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
581 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
582 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
583 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
584 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
585 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
586 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
587 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
588 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
589 *
590 * (*) value not defined in all devices.
591 * @retval None
592 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)593 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
594 {
595 SET_BIT(RCC->APB1RSTR, Periphs);
596 }
597
598 /**
599 * @brief Release APB1 peripherals reset.
600 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
601 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
602 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
603 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
604 * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n
605 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
606 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
607 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
608 * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n
609 * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
610 * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
611 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
612 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
613 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
614 * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
615 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
616 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
617 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
618 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset
619 * @param Periphs This parameter can be a combination of the following values:
620 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
622 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
623 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
624 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
625 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
626 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
627 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
628 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
629 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
630 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
631 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
632 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
633 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
634 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
635 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
636 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
637 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
638 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
639 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
640 *
641 * (*) value not defined in all devices.
642 * @retval None
643 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)644 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
645 {
646 CLEAR_BIT(RCC->APB1RSTR, Periphs);
647 }
648
649 /**
650 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
651 * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n
652 * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n
653 * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n
654 * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n
655 * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n
656 * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n
657 * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n
658 * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n
659 * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n
660 * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n
661 * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n
662 * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n
663 * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n
664 * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n
665 * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n
666 * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n
667 * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n
668 * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n
669 * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep
670 * @param Periphs This parameter can be a combination of the following values:
671 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
672 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
673 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
674 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
675 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
676 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
677 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
678 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
679 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
680 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
681 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
682 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
683 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
684 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
685 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
686 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
687 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
688 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
689 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
690 *
691 * (*) value not defined in all devices.
692 * @retval None
693 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)694 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
695 {
696 __IO uint32_t tmpreg;
697 SET_BIT(RCC->APB1SMENR, Periphs);
698 /* Delay after an RCC peripheral clock enabling */
699 tmpreg = READ_BIT(RCC->APB1SMENR, Periphs);
700 (void)tmpreg;
701 }
702
703 /**
704 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
705 * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n
706 * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n
707 * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n
708 * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n
709 * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n
710 * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n
711 * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n
712 * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n
713 * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n
714 * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n
715 * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n
716 * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n
717 * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n
718 * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n
719 * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n
720 * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n
721 * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n
722 * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n
723 * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep
724 * @param Periphs This parameter can be a combination of the following values:
725 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
726 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
727 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
728 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
729 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
730 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
731 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
732 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
733 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
734 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
735 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
736 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
737 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
738 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
739 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
740 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
741 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
742 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
743 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
744 *
745 * (*) value not defined in all devices.
746 * @retval None
747 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)748 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
749 {
750 CLEAR_BIT(RCC->APB1SMENR, Periphs);
751 }
752
753 /**
754 * @}
755 */
756
757 /** @defgroup BUS_LL_EF_APB2 APB2
758 * @{
759 */
760
761 /**
762 * @brief Enable APB2 peripherals clock.
763 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
764 * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n
765 * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n
766 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
767 * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n
768 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
769 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
770 * APB2ENR DBGEN LL_APB2_GRP1_EnableClock
771 * @param Periphs This parameter can be a combination of the following values:
772 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
773 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
774 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
775 * @arg @ref LL_APB2_GRP1_PERIPH_FW
776 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
777 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
778 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
779 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
780 *
781 * (*) value not defined in all devices.
782 * @retval None
783 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)784 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
785 {
786 __IO uint32_t tmpreg;
787 SET_BIT(RCC->APB2ENR, Periphs);
788 /* Delay after an RCC peripheral clock enabling */
789 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
790 (void)tmpreg;
791 }
792
793 /**
794 * @brief Check if APB2 peripheral clock is enabled or not
795 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
796 * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n
797 * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n
798 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
799 * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n
800 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
801 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
802 * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock
803 * @param Periphs This parameter can be a combination of the following values:
804 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
805 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
806 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
807 * @arg @ref LL_APB2_GRP1_PERIPH_FW
808 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
809 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
810 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
811 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
812 *
813 * (*) value not defined in all devices.
814 * @retval State of Periphs (1 or 0).
815 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)816 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
817 {
818 return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
819 }
820
821 /**
822 * @brief Disable APB2 peripherals clock.
823 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
824 * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n
825 * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n
826 * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n
827 * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n
828 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
829 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
830 * APB2ENR DBGEN LL_APB2_GRP1_DisableClock
831 * @param Periphs This parameter can be a combination of the following values:
832 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
833 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
834 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
835 * @arg @ref LL_APB2_GRP1_PERIPH_FW
836 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
837 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
838 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
839 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
840 *
841 * (*) value not defined in all devices.
842 * @retval None
843 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)844 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
845 {
846 CLEAR_BIT(RCC->APB2ENR, Periphs);
847 }
848
849 /**
850 * @brief Force APB2 peripherals reset.
851 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
852 * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n
853 * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n
854 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
855 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
856 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
857 * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset
858 * @param Periphs This parameter can be a combination of the following values:
859 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
860 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
861 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
862 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
863 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
864 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
865 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
866 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
867 *
868 * (*) value not defined in all devices.
869 * @retval None
870 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)871 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
872 {
873 SET_BIT(RCC->APB2RSTR, Periphs);
874 }
875
876 /**
877 * @brief Release APB2 peripherals reset.
878 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
879 * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n
880 * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n
881 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
882 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
883 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
884 * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset
885 * @param Periphs This parameter can be a combination of the following values:
886 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
887 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
888 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
889 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
890 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
891 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
892 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
893 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
894 *
895 * (*) value not defined in all devices.
896 * @retval None
897 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)898 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
899 {
900 CLEAR_BIT(RCC->APB2RSTR, Periphs);
901 }
902
903 /**
904 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
905 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockSleep\n
906 * APB2SMENR TIM21SMEN LL_APB2_GRP1_EnableClockSleep\n
907 * APB2SMENR TIM22SMEN LL_APB2_GRP1_EnableClockSleep\n
908 * APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n
909 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n
910 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n
911 * APB2SMENR DBGSMEN LL_APB2_GRP1_EnableClockSleep
912 * @param Periphs This parameter can be a combination of the following values:
913 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
914 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
915 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
916 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
917 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
918 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
919 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
920 *
921 * (*) value not defined in all devices.
922 * @retval None
923 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)924 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
925 {
926 __IO uint32_t tmpreg;
927 SET_BIT(RCC->APB2SMENR, Periphs);
928 /* Delay after an RCC peripheral clock enabling */
929 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
930 (void)tmpreg;
931 }
932
933 /**
934 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
935 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockSleep\n
936 * APB2SMENR TIM21SMEN LL_APB2_GRP1_DisableClockSleep\n
937 * APB2SMENR TIM22SMEN LL_APB2_GRP1_DisableClockSleep\n
938 * APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n
939 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n
940 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n
941 * APB2SMENR DBGSMEN LL_APB2_GRP1_DisableClockSleep
942 * @param Periphs This parameter can be a combination of the following values:
943 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
944 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
945 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
946 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
947 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
948 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
949 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
950 *
951 * (*) value not defined in all devices.
952 * @retval None
953 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)954 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
955 {
956 CLEAR_BIT(RCC->APB2SMENR, Periphs);
957 }
958
959 /**
960 * @}
961 */
962 /** @defgroup BUS_LL_EF_IOP IOP
963 * @{
964 */
965
966 /**
967 * @brief Enable IOP peripherals clock.
968 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n
969 * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n
970 * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n
971 * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n
972 * IOPENR GPIOEEN LL_IOP_GRP1_EnableClock\n
973 * IOPENR GPIOHEN LL_IOP_GRP1_EnableClock
974 * @param Periphs This parameter can be a combination of the following values:
975 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
976 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
977 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
978 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
979 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
980 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
981 *
982 * (*) value not defined in all devices.
983 * @retval None
984 */
LL_IOP_GRP1_EnableClock(uint32_t Periphs)985 __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
986 {
987 __IO uint32_t tmpreg;
988 SET_BIT(RCC->IOPENR, Periphs);
989 /* Delay after an RCC peripheral clock enabling */
990 tmpreg = READ_BIT(RCC->IOPENR, Periphs);
991 (void)tmpreg;
992 }
993
994 /**
995 * @brief Check if IOP peripheral clock is enabled or not
996 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n
997 * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n
998 * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n
999 * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n
1000 * IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock\n
1001 * IOPENR GPIOHEN LL_IOP_GRP1_IsEnabledClock
1002 * @param Periphs This parameter can be a combination of the following values:
1003 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1004 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1005 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1006 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
1007 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
1008 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
1009 *
1010 * (*) value not defined in all devices.
1011 * @retval State of Periphs (1 or 0).
1012 */
LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)1013 __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
1014 {
1015 return ((READ_BIT(RCC->IOPENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1016 }
1017
1018 /**
1019 * @brief Disable IOP peripherals clock.
1020 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n
1021 * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n
1022 * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n
1023 * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n
1024 * IOPENR GPIOEEN LL_IOP_GRP1_DisableClock\n
1025 * IOPENR GPIOHEN LL_IOP_GRP1_DisableClock
1026 * @param Periphs This parameter can be a combination of the following values:
1027 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1028 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1029 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1030 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
1031 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
1032 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
1033 *
1034 * (*) value not defined in all devices.
1035 * @retval None
1036 */
LL_IOP_GRP1_DisableClock(uint32_t Periphs)1037 __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
1038 {
1039 CLEAR_BIT(RCC->IOPENR, Periphs);
1040 }
1041
1042 /**
1043 * @brief Disable IOP peripherals clock.
1044 * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ForceReset\n
1045 * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ForceReset\n
1046 * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ForceReset\n
1047 * IOPRSTR GPIODSMEN LL_IOP_GRP1_ForceReset\n
1048 * IOPRSTR GPIOESMEN LL_IOP_GRP1_ForceReset\n
1049 * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ForceReset
1050 * @param Periphs This parameter can be a combination of the following values:
1051 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
1052 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1053 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1054 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1055 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
1056 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
1057 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
1058 *
1059 * (*) value not defined in all devices.
1060 * @retval None
1061 */
LL_IOP_GRP1_ForceReset(uint32_t Periphs)1062 __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
1063 {
1064 SET_BIT(RCC->IOPRSTR, Periphs);
1065 }
1066
1067 /**
1068 * @brief Release IOP peripherals reset.
1069 * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ReleaseReset\n
1070 * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ReleaseReset\n
1071 * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ReleaseReset\n
1072 * IOPRSTR GPIODSMEN LL_IOP_GRP1_ReleaseReset\n
1073 * IOPRSTR GPIOESMEN LL_IOP_GRP1_ReleaseReset\n
1074 * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ReleaseReset
1075 * @param Periphs This parameter can be a combination of the following values:
1076 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
1077 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1078 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1079 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1080 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
1081 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
1082 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
1083 *
1084 * (*) value not defined in all devices.
1085 * @retval None
1086 */
LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)1087 __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
1088 {
1089 CLEAR_BIT(RCC->IOPRSTR, Periphs);
1090 }
1091
1092 /**
1093 * @brief Enable IOP peripherals clock during Low Power (Sleep) mode.
1094 * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_EnableClockSleep\n
1095 * IOPSMENR GPIOBRST LL_IOP_GRP1_EnableClockSleep\n
1096 * IOPSMENR GPIOCRST LL_IOP_GRP1_EnableClockSleep\n
1097 * IOPSMENR GPIODRST LL_IOP_GRP1_EnableClockSleep\n
1098 * IOPSMENR GPIOERST LL_IOP_GRP1_EnableClockSleep\n
1099 * IOPSMENR GPIOHRST LL_IOP_GRP1_EnableClockSleep
1100 * @param Periphs This parameter can be a combination of the following values:
1101 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1102 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1103 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1104 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
1105 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
1106 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
1107 *
1108 * (*) value not defined in all devices.
1109 * @retval None
1110 */
LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs)1111 __STATIC_INLINE void LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs)
1112 {
1113 __IO uint32_t tmpreg;
1114 SET_BIT(RCC->IOPSMENR, Periphs);
1115 /* Delay after an RCC peripheral clock enabling */
1116 tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
1117 (void)tmpreg;
1118 }
1119
1120 /**
1121 * @brief Disable IOP peripherals clock during Low Power (Sleep) mode.
1122 * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_DisableClockSleep\n
1123 * IOPSMENR GPIOBRST LL_IOP_GRP1_DisableClockSleep\n
1124 * IOPSMENR GPIOCRST LL_IOP_GRP1_DisableClockSleep\n
1125 * IOPSMENR GPIODRST LL_IOP_GRP1_DisableClockSleep\n
1126 * IOPSMENR GPIOERST LL_IOP_GRP1_DisableClockSleep\n
1127 * IOPSMENR GPIOHRST LL_IOP_GRP1_DisableClockSleep
1128 * @param Periphs This parameter can be a combination of the following values:
1129 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1130 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1131 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1132 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
1133 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
1134 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
1135 *
1136 * (*) value not defined in all devices.
1137 * @retval None
1138 */
LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs)1139 __STATIC_INLINE void LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs)
1140 {
1141 CLEAR_BIT(RCC->IOPSMENR, Periphs);
1142 }
1143
1144 /**
1145 * @}
1146 */
1147
1148
1149 /**
1150 * @}
1151 */
1152
1153 /**
1154 * @}
1155 */
1156
1157 #endif /* defined(RCC) */
1158
1159 /**
1160 * @}
1161 */
1162
1163 #ifdef __cplusplus
1164 }
1165 #endif
1166
1167 #endif /* __STM32L0xx_LL_BUS_H */
1168
1169
