1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Access to DBGCMU registers
25 (+) Access to SYSCFG registers
26
27 @endverbatim
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32MP1xx_LL_SYSTEM_H
33 #define STM32MP1xx_LL_SYSTEM_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32mp1xx.h"
41
42 /** @addtogroup STM32MP1xx_LL_Driver
43 * @{
44 */
45
46 #if defined (SYSCFG) || defined (DBGMCU)
47
48 /** @defgroup SYSTEM_LL SYSTEM
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
57 * @{
58 */
59 /**
60 * @}
61 */
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
68 * @{
69 */
70
71 /** @defgroup SYSTEM_LL_EC_BOOT_PIN SYSCFG Boot Pin code selection
72 * @{
73 */
74 #define LL_SYSCFG_BOOT0 SYSCFG_BOOTR_BOOT0 /*!< BOOT0 pin connected to VDD */
75 #define LL_SYSCFG_BOOT1 SYSCFG_BOOTR_BOOT1 /*!< BOOT1 pin connected to VDD */
76 #define LL_SYSCFG_BOOT2 SYSCFG_BOOTR_BOOT2 /*!< BOOT2 pin connected to VDD */
77 /**
78 * @}
79 */
80
81 /** @defgroup SYSTEM_LL_EC_BOOT_PIN_PD SYSCFG Boot Pin Pull-Down code selection
82 * @{
83 */
84 #define LL_SYSCFG_BOOT0_PD SYSCFG_BOOTR_BOOT0_PD /*!< Enable BOOT0 pin pull-down disabled */
85 #define LL_SYSCFG_BOOT1_PD SYSCFG_BOOTR_BOOT1_PD /*!< Enable BOOT1 pin pull-down disabled */
86 #define LL_SYSCFG_BOOT2_PD SYSCFG_BOOTR_BOOT2_PD /*!< Enable BOOT2 pin pull-down disbaled */
87 /**
88 * @}
89 */
90
91 /** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
92 * @{
93 */
94 #define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< PA0 Switch Open */
95 #define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< PA1 Switch Open */
96 /**
97 * @}
98 */
99
100 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
101 * @{
102 */
103 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCSETR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
104 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCSETR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
105 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCSETR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
106 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCSETR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
107 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCSETR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */
108 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C6 SYSCFG_PMCSETR_I2C6_FMP /*!< Enable Fast Mode Plus for I2C6 */
109 /**
110 * @}
111 */
112
113 /** @defgroup SYSTEM_LL_EC_ETHERNET_PHY Ethernet PHY Interface Selection
114 * @{
115 */
116 #define LL_SYSCFG_ETH_GMII 0x00000000U /*!< Enable ETH Media GMII interface */
117 #define LL_SYSCFG_ETH_MII 0x00100000U /*!< Enable ETH Media MII interface */
118 #define LL_SYSCFG_ETH_RGMII 0x00200000U /*!< Enable ETH Media RGMII interface */
119 #define LL_SYSCFG_ETH_RMII 0x00800000U /*!< Enable ETH Media RMII interface */
120 /**
121 * @}
122 */
123
124
125 /** @defgroup SYSTEM_LL_EC_ETHERNET_MII Ethernet MII Mode Selection
126 * @{
127 */
128 #define LL_SYSCFG_ETH_CLK SYSCFG_PMCSETR_ETH_CLK_SEL /*!< Enable ETH clock selection */
129 #define LL_SYSCFG_ETH_REF_CLK SYSCFG_PMCSETR_ETH_REF_CLK_SEL /*!< Enable ETH REF clock selection */
130 /**
131 * @}
132 */
133
134 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
135 * @{
136 */
137 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection
138 with TIM1/8/15/16/17 Break Input
139 and also the PVDE and PLS bits of the Power Control Interface */
140 #define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Cortex-M4 LOCKUP signal
141 with Break Input of TIM1/8/15/16/17 */
142
143 /**
144 * @}
145 */
146
147 /** @defgroup SYSTEM_LL_EC_IO_COMPENSATION SYSCFG I/O compensation cell code selection
148 * @{
149 */
150 #define LL_SYSCFG_CELL_CODE 0U /*!< Disable Compensation Software Control */
151 #define LL_SYSCFG_REGISTER_CODE SYSCFG_CMPCR_SW_CTRL /*!< Enable Compensation Software Control */
152 /**
153 * @}
154 */
155
156 /** @defgroup SYSTEM_LL_EC_AXI Master code selection
157 * @{
158 */
159 #define LL_SYSCFG_AXI_MASTER0_S1 SYSCFG_ICNR_AXI_M0 /*!< Enable AXI Master access DDR through Slave S1 */
160 #define LL_SYSCFG_AXI_MASTER1_S1 SYSCFG_ICNR_AXI_M1 /*!< Enable AXI Master access DDR through Slave S1 */
161 #define LL_SYSCFG_AXI_MASTER2_S1 SYSCFG_ICNR_AXI_M2 /*!< Enable AXI Master access DDR through Slave S1 */
162 #define LL_SYSCFG_AXI_MASTER3_S1 SYSCFG_ICNR_AXI_M3 /*!< Enable AXI Master access DDR through Slave S1 */
163 #define LL_SYSCFG_AXI_MASTER5_S1 SYSCFG_ICNR_AXI_M5 /*!< Enable AXI Master access DDR through Slave S1 */
164 #define LL_SYSCFG_AXI_MASTER6_S1 SYSCFG_ICNR_AXI_M6 /*!< Enable AXI Master access DDR through Slave S1 */
165 #define LL_SYSCFG_AXI_MASTER7_S1 SYSCFG_ICNR_AXI_M7 /*!< Enable AXI Master access DDR through Slave S1 */
166 #define LL_SYSCFG_AXI_MASTER8_S1 SYSCFG_ICNR_AXI_M8 /*!< Enable AXI Master access DDR through Slave S1 */
167 #define LL_SYSCFG_AXI_MASTER9_S1 SYSCFG_ICNR_AXI_M9 /*!< Enable AXI Master access DDR through Slave S1 */
168 #define LL_SYSCFG_AXI_MASTER10_S1 SYSCFG_ICNR_AXI_M10 /*!< Enable AXI Master access DDR through Slave S1 */
169 /**
170 * @}
171 */
172
173 /** @defgroup SYSTEM_LL_EC_TRIGGER_OUTPUT DBGMCU TRIGGER output direction
174 * @{
175 */
176 #define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U /*!< Disable External trigger output */
177 #define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN /*!< Enable External trigger output */
178 /**
179 * @}
180 */
181
182 /** @defgroup SYSTEM_LL_EC_IWDG DBGMCU IWDG Freeze Watchdog
183 * @{
184 */
185 #define LL_DBGMCU_IWDG_FREEZE_1CA7_HALT 0U /*!< Freeze Watchdog timer when either CA7 core halt in debug mode */
186 #define LL_DBGMCU_IWDG_FREEZE_2CA7_HALT DBGMCU_CR_DBG_WDFZCTL /*!< Freeze Watchdog timer when both CA7 cores halt in debug mode */
187 /**
188 * @}
189 */
190
191
192 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
193 * @{
194 */
195 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
196 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
197 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
198 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
199 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
200 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
201 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
202 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
203 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
204 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIM1 counter stopped when core is halted */
205 #define LL_DBGMCU_APB1_GRP1_WWDG1_STOP DBGMCU_APB1_FZ_DBG_WWDG1_STOP /*!< WWDG1 counter stopped when core is halted */
206 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
207 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
208 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
209 #define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1_FZ_DBG_I2C5_STOP /*!< I2C5 SMBUS timeout mode stopped when Core is halted */
210 /**
211 * @}
212 */
213
214 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
215 * @{
216 */
217 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 is frozen while the core is in debug mode */
218 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 is frozen while the core is in debug mode */
219 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 is frozen while the core is in debug mode */
220 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 is frozen while the core is in debug mode */
221 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 is frozen while the core is in debug mode */
222 #define LL_DBGMCU_APB2_GRP1_FDCAN_STOP DBGMCU_APB2_FZ_DBG_FDCAN_STOP /*!< FDCAN is frozen while the core is in debug mode */
223 /**
224 * @}
225 */
226
227 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
228 * @{
229 */
230 #define LL_DBGMCU_APB3_GRP1_LPTIM2_STOP DBGMCU_APB3_FZ_DBG_LPTIM2_STOP /*!< LPTIM2 counter stopped when core is halted */
231 #define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3_FZ_DBG_LPTIM3_STOP /*!< LPTIM3 counter stopped when core is halted */
232 #define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3_FZ_DBG_LPTIM4_STOP /*!< LPTIM4 counter stopped when core is halted */
233 #define LL_DBGMCU_APB3_GRP1_LPTIM5_STOP DBGMCU_APB3_FZ_DBG_LPTIM5_STOP /*!< LPTIM5 counter stopped when core is halted */
234 /**
235 * @}
236 */
237
238 /** @defgroup SYSTEM_LL_EC_APB5_GRP1_STOP_IP DBGMCU APB5 GRP1 STOP IP
239 * @{
240 */
241 #define LL_DBGMCU_APB5_GRP1_I2C4_STOP DBGMCU_APB5_FZ_DBG_I2C4_STOP /*!< I2C4 is frozen while the core is in debug mode */
242 #define LL_DBGMCU_APB5_GRP1_RTC_STOP DBGMCU_APB5_FZ_DBG_RTC_STOP /*!< RTC is frozen while the core is in debug mode */
243 #define LL_DBGMCU_APB5_GRP1_I2C6_STOP DBGMCU_APB5_FZ_DBG_I2C6_STOP /*!< I2C6 is frozen while the core is in debug mode */
244 /**
245 * @}
246 */
247 /**
248 * @}
249 */
250
251 /* Exported macro ------------------------------------------------------------*/
252
253 /* Exported functions --------------------------------------------------------*/
254 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
255 * @{
256 */
257
258 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
259 * @{
260 */
261
262 /**
263 * @brief Get boot pin value connected to VDD
264 * @rmtoll SYSCFG_BOOTR BOOTx LL_SYSCFG_GetBootPinValueToVDD
265 * @param BootPinValue This parameter can be a combination of the following values:
266 * @arg @ref LL_SYSCFG_BOOT0
267 * @arg @ref LL_SYSCFG_BOOT1
268 * @arg @ref LL_SYSCFG_BOOT2
269 * @retval None
270 */
LL_SYSCFG_GetBootPinValueToVDD(uint16_t BootPinValue)271 __STATIC_INLINE uint32_t LL_SYSCFG_GetBootPinValueToVDD(uint16_t BootPinValue)
272 {
273 return (uint32_t)(READ_BIT(SYSCFG->BOOTR, BootPinValue));
274 }
275
276 /**
277 * @brief Enable boot pin pull-down disabled
278 * @rmtoll SYSCFG_BOOTR BOOTx_PD LL_SYSCFG_EnableBootPinPullDownDisabled
279 * @param BootPinPDValue This parameter can be a combination of the following values:
280 * @arg @ref LL_SYSCFG_BOOT0_PD
281 * @arg @ref LL_SYSCFG_BOOT1_PD
282 * @arg @ref LL_SYSCFG_BOOT2_PD
283 * @retval None
284 */
LL_SYSCFG_EnableBootPinPullDownDisabled(uint16_t BootPinPDValue)285 __STATIC_INLINE void LL_SYSCFG_EnableBootPinPullDownDisabled(uint16_t BootPinPDValue)
286 {
287 SET_BIT(SYSCFG->BOOTR, BootPinPDValue);
288 }
289
290 /**
291 * @brief Disable boot pin pull-down disabled
292 * @rmtoll SYSCFG_BOOTR BOOTx_PD LL_SYSCFG_DisableBootPinPullDownDisabled
293 * @param BootPinPDValue This parameter can be a combination of the following values:
294 * @arg @ref LL_SYSCFG_BOOT0_PD
295 * @arg @ref LL_SYSCFG_BOOT1_PD
296 * @arg @ref LL_SYSCFG_BOOT2_PD
297 * @retval None
298 */
LL_SYSCFG_DisableBootPinPullDownDisabled(uint16_t BootPinPDValue)299 __STATIC_INLINE void LL_SYSCFG_DisableBootPinPullDownDisabled(uint16_t BootPinPDValue)
300 {
301 CLEAR_BIT(SYSCFG->BOOTR, BootPinPDValue);
302 }
303
304 /**
305 * @brief Set Ethernet PHY interface
306 * @rmtoll SYSCFG_PMCSETR ETH_SEL LL_SYSCFG_SetPHYInterface
307 * @rmtoll SYSCFG_PMCSETR ETH_SELMII LL_SYSCFG_SetPHYInterface
308 * @param Interface : Interface This parameter can be one of the following values:
309 * @arg @ref LL_SYSCFG_ETH_MII
310 * @arg @ref LL_SYSCFG_ETH_GMII
311 * @arg @ref LL_SYSCFG_ETH_RGMII
312 * @arg @ref LL_SYSCFG_ETH_RMII
313 * @retval None
314 */
LL_SYSCFG_SetPHYInterface(uint32_t Interface)315 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
316 {
317 MODIFY_REG(SYSCFG->PMCCLRR, SYSCFG_PMCCLRR_ETH_SEL_CONF, SYSCFG_PMCCLRR_ETH_SEL_CONF);
318 MODIFY_REG(SYSCFG->PMCSETR, SYSCFG_PMCSETR_ETH_SEL_CONF, Interface);
319 }
320
321 /**
322 * @brief Get Ethernet PHY interface
323 * @rmtoll SYSCFG_PMCSETR ETH_SEL LL_SYSCFG_GetPHYInterface
324 * @rmtoll SYSCFG_PMCSETR ETH_SELMII LL_SYSCFG_GetPHYInterface
325 * @retval Returned value can be one of the following values:
326 * @arg @ref LL_SYSCFG_ETH_MII
327 * @arg @ref LL_SYSCFG_ETH_RMII
328 * @arg @ref LL_SYSCFG_ETH_GMII
329 * @arg @ref LL_SYSCFG_ETH_RGMII
330 */
LL_SYSCFG_GetPHYInterface(void)331 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
332 {
333 return (uint32_t)(READ_BIT(SYSCFG->PMCSETR, SYSCFG_PMCSETR_ETH_SEL_CONF));
334 }
335
336 /**
337 * @brief Clear Ethernet PHY mode
338 * @rmtoll SYSCFG_PMCSETR ETH_SEL LL_SYSCFG_ClearPHYInterface
339 * @rmtoll SYSCFG_PMCSETR ETH_SELMII LL_SYSCFG_ClearPHYInterface
340 * @param Interface : Interface This parameter can be one of the following values:
341 * @arg @ref LL_SYSCFG_ETH_MII
342 * @arg @ref LL_SYSCFG_ETH_GMII
343 * @arg @ref LL_SYSCFG_ETH_RGMII
344 * @arg @ref LL_SYSCFG_ETH_RMII
345 * @retval None
346 */
LL_SYSCFG_ClearPHYInterface(uint32_t Interface)347 __STATIC_INLINE void LL_SYSCFG_ClearPHYInterface(uint32_t Interface)
348 {
349 MODIFY_REG(SYSCFG->PMCCLRR, SYSCFG_PMCCLRR_ETH_SEL_CONF, Interface);
350 }
351
352 /**
353 * @brief Enable Ethernet clock
354 * @rmtoll SYSCFG_PMCSETR ETH_CLK_SEL LL_SYSCFG_EnablePHYInternalClock\n
355 * SYSCFG_PMCSETR ETH_REF_CLK_SEL LL_SYSCFG_EnablePHYInternalClock
356 * @param Clock : This parameter can be one of the following values:
357 * @arg @ref LL_SYSCFG_ETH_CLK
358 * @arg @ref LL_SYSCFG_ETH_REF_CLK
359 * @retval None
360 */
LL_SYSCFG_EnablePHYInternalClock(uint32_t Clock)361 __STATIC_INLINE void LL_SYSCFG_EnablePHYInternalClock(uint32_t Clock)
362 {
363 MODIFY_REG(SYSCFG->PMCSETR, (SYSCFG_PMCSETR_ETH_CLK_SEL | SYSCFG_PMCSETR_ETH_REF_CLK_SEL), Clock);
364 }
365
366 /**
367 * @brief Disable Ethernet clock
368 * @rmtoll SYSCFG_PMCCLRR ETH_CLK_SEL LL_SYSCFG_DisablePHYInternalClock\n
369 * SYSCFG_PMCCLRR ETH_REF_CLK_SEL LL_SYSCFG_DisablePHYInternalClock
370 * @param Clock : This parameter can be one of the following values:
371 * @arg @ref LL_SYSCFG_ETH_CLK
372 * @arg @ref LL_SYSCFG_ETH_REF_CLK
373 * @retval None
374 */
LL_SYSCFG_DisablePHYInternalClock(uint32_t Clock)375 __STATIC_INLINE void LL_SYSCFG_DisablePHYInternalClock(uint32_t Clock)
376 {
377 MODIFY_REG(SYSCFG->PMCCLRR, (SYSCFG_PMCCLRR_ETH_CLK_SEL | SYSCFG_PMCCLRR_ETH_REF_CLK_SEL), Clock);
378 }
379
380
381 /**
382 * @brief Open an Analog Switch
383 * @rmtoll SYSCFG_PMCSETR ANA0_SEL LL_SYSCFG_OpenAnalogSwitch
384 * SYSCFG_PMCSETR ANA1_SEL LL_SYSCFG_OpenAnalogSwitch
385 * @param AnalogSwitch This parameter can be one of the following values:
386 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
387 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
388 * @retval None
389 */
LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)390 __STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
391 {
392 SET_BIT(SYSCFG->PMCSETR, AnalogSwitch);
393 }
394
395 /**
396 * @brief Close an Analog Switch
397 * @rmtoll SYSCFG_PMCCLRR ANA0_SEL LL_SYSCFG_CloseAnalogSwitch
398 * SYSCFG_PMCCLRR ANA1_SEL LL_SYSCFG_CloseAnalogSwitch
399 * @param AnalogSwitch This parameter can be one of the following values:
400 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
401 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
402 * @retval None
403 */
LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)404 __STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
405 {
406 MODIFY_REG(SYSCFG->PMCCLRR, (SYSCFG_PMCCLRR_ANA0_SEL_SEL | SYSCFG_PMCCLRR_ANA1_SEL_SEL), AnalogSwitch);
407 }
408
409 /**
410 * @brief Enable the Analog GPIO switch to control voltage selection
411 * when the supply voltage is supplied by VDDA
412 * @rmtoll SYSCFG_PMCSETR ANASWVDD LL_SYSCFG_EnableAnalogGpioSwitch
413 * @note Activating the gpio switch enable IOs analog switches supplied by VDDA
414 * @retval None
415 */
LL_SYSCFG_EnableAnalogGpioSwitch(void)416 __STATIC_INLINE void LL_SYSCFG_EnableAnalogGpioSwitch(void)
417 {
418 SET_BIT(SYSCFG->PMCSETR, SYSCFG_PMCSETR_ANASWVDD);
419 }
420
421 /**
422 * @brief Disable the Analog GPIO switch to control voltage selection
423 * when the supply voltage is supplied by VDDA
424 * @rmtoll SYSCFG_PMCCLRR ANASWVDD LL_SYSCFG_DisableAnalogGpioSwitch
425 * @note Activating the gpio switch enable IOs analog switches supplied by VDDA
426 * @retval None
427 */
LL_SYSCFG_DisableAnalogGpioSwitch(void)428 __STATIC_INLINE void LL_SYSCFG_DisableAnalogGpioSwitch(void)
429 {
430 SET_BIT(SYSCFG->PMCCLRR, SYSCFG_PMCCLRR_ANASWVDD);
431 }
432
433 /**
434 * @brief Enable the Analog booster to reduce the total harmonic distortion
435 * of the analog switch when the supply voltage is lower than 2.7 V
436 * @rmtoll SYSCFG_PMCSETR EN_BOOSTER LL_SYSCFG_EnableAnalogBooster
437 * @note Activating the booster allows to guaranty the analog switch AC performance
438 * when the supply voltage is below 2.7 V: in this case, the analog switch
439 * performance is the same on the full voltage range
440 * @retval None
441 */
LL_SYSCFG_EnableAnalogBooster(void)442 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
443 {
444 SET_BIT(SYSCFG->PMCSETR, SYSCFG_PMCSETR_EN_BOOSTER);
445 }
446
447 /**
448 * @brief Disable the Analog booster
449 * @rmtoll SYSCFG_PMCCLRR EN_BOOSTER LL_SYSCFG_DisableAnalogBooster
450 * @note Activating the booster allows to guaranty the analog switch AC performance
451 * when the supply voltage is below 2.7 V: in this case, the analog switch
452 * performance is the same on the full voltage range
453 * @retval None
454 */
LL_SYSCFG_DisableAnalogBooster(void)455 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
456 {
457 SET_BIT(SYSCFG->PMCCLRR, SYSCFG_PMCCLRR_EN_BOOSTER);
458 }
459
460 /**
461 * @brief Enable the I2C fast mode plus driving capability.
462 * @rmtoll SYSCFG_PMCSETR I2Cx_FMP LL_SYSCFG_EnableFastModePlus\n
463 * @param ConfigFastModePlus This parameter can be a combination of the following values:
464 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
465 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
466 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
467 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
468 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5
469 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C6
470 * @retval None
471 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)472 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
473 {
474 SET_BIT(SYSCFG->PMCSETR, ConfigFastModePlus);
475 }
476
477 /**
478 * @brief Disable the I2C fast mode plus driving capability.
479 * @rmtoll SYSCFG_PMCCLRR I2Cx_FMP LL_SYSCFG_DisableFastModePlus\n
480 * @param ConfigFastModePlus This parameter can be a combination of the following values:
481 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
482 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
483 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
484 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
485 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5
486 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C6
487 * @retval None
488 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)489 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
490 {
491 MODIFY_REG(SYSCFG->PMCCLRR, (SYSCFG_PMCCLRR_I2C1_FMP | SYSCFG_PMCCLRR_I2C2_FMP | SYSCFG_PMCCLRR_I2C3_FMP | SYSCFG_PMCCLRR_I2C4_FMP | SYSCFG_PMCCLRR_I2C5_FMP | SYSCFG_PMCCLRR_I2C6_FMP), ConfigFastModePlus);
492 }
493
494 /**
495 * @brief Enable the Compensation Cell
496 * @rmtoll SYSCFG_CMPENSETR MCU_EN LL_SYSCFG_EnableCompensationCell
497 * @note The I/O compensation cell can be used only when the device supply
498 * voltage ranges from 2.4 to 3.6 V
499 * @retval None
500 */
LL_SYSCFG_EnableCompensationCell(void)501 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
502 {
503 SET_BIT(SYSCFG->CMPENSETR, SYSCFG_CMPENSETR_MCU_EN);
504 }
505
506 /**
507 * @brief Disable the Compensation Cell
508 * @rmtoll SYSCFG_CMPENCLRR MCU_EN LL_SYSCFG_DisableCompensationCell
509 * @note The I/O compensation cell can be used only when the device supply
510 * voltage ranges from 2.4 to 3.6 V
511 * @retval None
512 */
LL_SYSCFG_DisableCompensationCell(void)513 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
514 {
515 SET_BIT(SYSCFG->CMPENCLRR, SYSCFG_CMPENCLRR_MCU_EN);
516 }
517
518 /**
519 * @brief Check if the Compensation Cell is enabled
520 * @rmtoll SYSCFG_CMPENSETR MCU_EN LL_SYSCFG_IsEnabledCompensationCell
521 * @retval State of bit (1 or 0).
522 */
LL_SYSCFG_IsEnabledCompensationCell(void)523 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
524 {
525 return (uint32_t)(READ_BIT(SYSCFG->CMPENSETR, SYSCFG_CMPENSETR_MCU_EN) == SYSCFG_CMPENSETR_MCU_EN);
526 }
527
528 /**
529 * @brief Get Compensation Cell ready Flag
530 * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsReadyCompensationCell
531 * @retval State of bit (1 or 0).
532 */
LL_SYSCFG_IsReadyCompensationCell(void)533 __STATIC_INLINE uint32_t LL_SYSCFG_IsReadyCompensationCell(void)
534 {
535 return (uint32_t)(READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
536 }
537
538 /**
539 * @brief Enable the SPI I/O speed optimization when the product voltage is low.
540 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_SPI LL_SYSCFG_EnableIOSpeedOptimizeSPI
541 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
542 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
543 * might be destructive.
544 * @retval None
545 */
LL_SYSCFG_EnableIOSpeedOptimizationSPI(void)546 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimizationSPI(void)
547 {
548 SET_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_SPI);
549 }
550
551 /**
552 * @brief To Disable optimize the SPI I/O speed when the product voltage is low.
553 * @rmtoll SYSCFG_IOCTRLCLRR HSLVEN_SPI LL_SYSCFG_DisableIOSpeedOptimizeSPI
554 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
555 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
556 * might be destructive.
557 * @retval None
558 */
LL_SYSCFG_DisableIOSpeedOptimizationSPI(void)559 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimizationSPI(void)
560 {
561 MODIFY_REG(SYSCFG->IOCTRLCLRR, SYSCFG_IOCTRLCLRR_HSLVEN_SPI, SYSCFG_IOCTRLCLRR_HSLVEN_SPI);
562 }
563
564 /**
565 * @brief Check if the SPI I/O speed optimization is enabled
566 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_SPI LL_SYSCFG_IsEnabledIOSpeedOptimizationSPI
567 * @retval State of bit (1 or 0).
568 */
LL_SYSCFG_IsEnabledIOSpeedOptimizationSPI(void)569 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimizationSPI(void)
570 {
571 return (uint32_t)(READ_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_SPI) == SYSCFG_IOCTRLSETR_HSLVEN_SPI);
572 }
573
574 /**
575 * @brief Enable the SDMMC I/O speed optimization when the product voltage is low.
576 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_SDMMC LL_SYSCFG_EnableIOSpeedOptimizeSDMMC
577 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
578 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
579 * might be destructive.
580 * @retval None
581 */
LL_SYSCFG_EnableIOSpeedOptimizationSDMMC(void)582 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimizationSDMMC(void)
583 {
584 SET_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_SDMMC);
585 }
586
587 /**
588 * @brief To Disable optimize the SDMMC I/O speed when the product voltage is low.
589 * @rmtoll SYSCFG_IOCTRLCLRR HSLVEN_SDMMC LL_SYSCFG_DisableIOSpeedOptimizeSDMMC
590 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
591 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
592 * might be destructive.
593 * @retval None
594 */
LL_SYSCFG_DisableIOSpeedOptimizationSDMMC(void)595 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimizationSDMMC(void)
596 {
597 MODIFY_REG(SYSCFG->IOCTRLCLRR, SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC, SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC);
598 }
599
600 /**
601 * @brief Check if the SDMMC I/O speed optimization is enabled
602 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_SDMMC LL_SYSCFG_IsEnabledIOSpeedOptimizationSDMMC
603 * @retval State of bit (1 or 0).
604 */
LL_SYSCFG_IsEnabledIOSpeedOptimizationSDMMC(void)605 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimizationSDMMC(void)
606 {
607 return (uint32_t)(READ_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_SDMMC) == SYSCFG_IOCTRLSETR_HSLVEN_SDMMC);
608 }
609
610 /**
611 * @brief Enable the ETH I/O speed optimization when the product voltage is low.
612 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_ETH LL_SYSCFG_EnableIOSpeedOptimizeETH
613 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
614 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
615 * might be destructive.
616 * @retval None
617 */
LL_SYSCFG_EnableIOSpeedOptimizationETH(void)618 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimizationETH(void)
619 {
620 SET_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_ETH);
621 }
622
623 /**
624 * @brief To Disable optimize the ETH I/O speed when the product voltage is low.
625 * @rmtoll SYSCFG_IOCTRLCLRR HSLVEN_ETH LL_SYSCFG_DisableIOSpeedOptimizeETH
626 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
627 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
628 * might be destructive.
629 * @retval None
630 */
LL_SYSCFG_DisableIOSpeedOptimizationETH(void)631 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimizationETH(void)
632 {
633 MODIFY_REG(SYSCFG->IOCTRLCLRR, SYSCFG_IOCTRLCLRR_HSLVEN_ETH, SYSCFG_IOCTRLCLRR_HSLVEN_ETH);
634 }
635
636 /**
637 * @brief Check if the ETH I/O speed optimization is enabled
638 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_ETH LL_SYSCFG_IsEnabledIOSpeedOptimizationETH
639 * @retval State of bit (1 or 0).
640 */
LL_SYSCFG_IsEnabledIOSpeedOptimizationETH(void)641 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimizationETH(void)
642 {
643 return (uint32_t)(READ_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_ETH) == SYSCFG_IOCTRLSETR_HSLVEN_ETH);
644 }
645
646
647 /**
648 * @brief Enable the QUADSPI I/O speed optimization when the product voltage is low.
649 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_QUADSPI LL_SYSCFG_EnableIOSpeedOptimizeQUADSPI
650 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
651 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
652 * might be destructive.
653 * @retval None
654 */
LL_SYSCFG_EnableIOSpeedOptimizationQUADSPI(void)655 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimizationQUADSPI(void)
656 {
657 SET_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI);
658 }
659
660 /**
661 * @brief To Disable optimize the QUADSPI I/O speed when the product voltage is low.
662 * @rmtoll SYSCFG_IOCTRLCLRR HSLVEN_QUADSPI LL_SYSCFG_DisableIOSpeedOptimizeQUADSPI
663 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
664 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
665 * might be destructive.
666 * @retval None
667 */
LL_SYSCFG_DisableIOSpeedOptimizationQUADSPI(void)668 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimizationQUADSPI(void)
669 {
670 MODIFY_REG(SYSCFG->IOCTRLCLRR, SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI, SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI);
671 }
672
673 /**
674 * @brief Check if the QUADSPI I/O speed optimization is enabled
675 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_QUADSPI LL_SYSCFG_IsEnabledIOSpeedOptimizationQUADSPI
676 * @retval State of bit (1 or 0).
677 */
LL_SYSCFG_IsEnabledIOSpeedOptimizationQUADSPI(void)678 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimizationQUADSPI(void)
679 {
680 return (uint32_t)(READ_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI) == SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI);
681 }
682
683 /**
684 * @brief Enable the TRACE I/O speed optimization when the product voltage is low.
685 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_TRACE LL_SYSCFG_EnableIOSpeedOptimizeTRACE
686 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
687 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
688 * might be destructive.
689 * @retval None
690 */
LL_SYSCFG_EnableIOSpeedOptimizationTRACE(void)691 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimizationTRACE(void)
692 {
693 SET_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_TRACE);
694 }
695
696 /**
697 * @brief To Disable optimize the TRACE I/O speed when the product voltage is low.
698 * @rmtoll SYSCFG_IOCTRLCLRR HSLVEN_TRACE LL_SYSCFG_DisableIOSpeedOptimizeTRACE
699 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
700 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
701 * might be destructive.
702 * @retval None
703 */
LL_SYSCFG_DisableIOSpeedOptimizationTRACE(void)704 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimizationTRACE(void)
705 {
706 MODIFY_REG(SYSCFG->IOCTRLCLRR, SYSCFG_IOCTRLCLRR_HSLVEN_TRACE, SYSCFG_IOCTRLCLRR_HSLVEN_TRACE);
707 }
708
709 /**
710 * @brief Check if the TRACE I/O speed optimization is enabled
711 * @rmtoll SYSCFG_IOCTRLSETR HSLVEN_TRACE LL_SYSCFG_IsEnabledIOSpeedOptimizationTRACE
712 * @retval State of bit (1 or 0).
713 */
LL_SYSCFG_IsEnabledIOSpeedOptimizationTRACE(void)714 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimizationTRACE(void)
715 {
716 return (uint32_t)(READ_BIT(SYSCFG->IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_TRACE) == SYSCFG_IOCTRLSETR_HSLVEN_TRACE);
717 }
718
719
720 /**
721 * @brief Enable the AXI master access DDR through slave S1
722 * @rmtoll SYSCFG_ICNR AXI_Mx LL_SYSCFG_EnableAXIMasterDDRAccessS1
723 * @param ConfigAxiMaster This parameter can be a combination of the following values:
724 * @arg @ref LL_SYSCFG_AXI_MASTER0_S1
725 * @arg @ref LL_SYSCFG_AXI_MASTER1_S1
726 * @arg @ref LL_SYSCFG_AXI_MASTER2_S1
727 * @arg @ref LL_SYSCFG_AXI_MASTER3_S1
728 * @arg @ref LL_SYSCFG_AXI_MASTER5_S1
729 * @arg @ref LL_SYSCFG_AXI_MASTER6_S1
730 * @arg @ref LL_SYSCFG_AXI_MASTER7_S1
731 * @arg @ref LL_SYSCFG_AXI_MASTER8_S1
732 * @arg @ref LL_SYSCFG_AXI_MASTER9_S1
733 * @arg @ref LL_SYSCFG_AXI_MASTER10_S1
734 * @retval None
735 */
LL_SYSCFG_EnableAXIMasterDDRAccessS1(uint32_t ConfigAxiMaster)736 __STATIC_INLINE void LL_SYSCFG_EnableAXIMasterDDRAccessS1(uint32_t ConfigAxiMaster)
737 {
738 SET_BIT(SYSCFG->ICNR, ConfigAxiMaster);
739 }
740
741 /**
742 * @brief Disable the AXI master access DDR through slave S1
743 * @rmtoll SYSCFG_ICNR AXI_Mx LL_SYSCFG_DisableFAXIMasterDDRAccessS1
744 * @param ConfigAxiMaster This parameter can be a combination of the following values:
745 * @arg @ref LL_SYSCFG_AXI_MASTER0_S1
746 * @arg @ref LL_SYSCFG_AXI_MASTER1_S1
747 * @arg @ref LL_SYSCFG_AXI_MASTER2_S1
748 * @arg @ref LL_SYSCFG_AXI_MASTER3_S1
749 * @arg @ref LL_SYSCFG_AXI_MASTER5_S1
750 * @arg @ref LL_SYSCFG_AXI_MASTER6_S1
751 * @arg @ref LL_SYSCFG_AXI_MASTER7_S1
752 * @arg @ref LL_SYSCFG_AXI_MASTER8_S1
753 * @arg @ref LL_SYSCFG_AXI_MASTER9_S1
754 * @arg @ref LL_SYSCFG_AXI_MASTER10_S1
755 * @retval None
756 */
LL_SYSCFG_DisableAXIMasterDDRAccessS1(uint32_t ConfigAxiMaster)757 __STATIC_INLINE void LL_SYSCFG_DisableAXIMasterDDRAccessS1(uint32_t ConfigAxiMaster)
758 {
759 CLEAR_BIT(SYSCFG->ICNR, ConfigAxiMaster);
760 }
761
762 /**
763 * @brief Set the code selection for the I/O Compensation cell
764 * @rmtoll SYSCFG_CMPCR SW_CTRL LL_SYSCFG_SetCellCompensationCode
765 * @param CompCode: Selects the code to be applied for the I/O compensation cell
766 * This parameter can be one of the following values:
767 * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell
768 * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register
769 * @retval None
770 */
LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)771 __STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
772 {
773 SET_BIT(SYSCFG->CMPCR, CompCode);
774 }
775
776 /**
777 * @brief Get the code selected for the I/O Compensation cell
778 * @rmtoll SYSCFG_CMPCR SW_CTRL LL_SYSCFG_GetCellCompensationCode
779 * @retval Returned value can be one of the following values:
780 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell
781 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register
782 */
LL_SYSCFG_GetCellCompensationCode(void)783 __STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
784 {
785 return (uint32_t)(READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_SW_CTRL));
786 }
787
788 /**
789 * @brief Get I/O compensation cell value for PMOS transistors
790 * @rmtoll SYSCFG_CMPCR APSRC LL_SYSCFG_GetPMOSCompensationValue
791 * @retval Returned value is the I/O compensation cell value for PMOS transistors
792 */
LL_SYSCFG_GetPMOSCompensationValue(void)793 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
794 {
795 return (uint32_t)(READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_APSRC));
796 }
797
798 /**
799 * @brief Get I/O compensation cell value for NMOS transistors
800 * @rmtoll SYSCFG_CMPCR ANSRC LL_SYSCFG_GetNMOSCompensationValue
801 * @retval Returned value is the I/O compensation cell value for NMOS transistors
802 */
LL_SYSCFG_GetNMOSCompensationValue(void)803 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
804 {
805 return (uint32_t)(READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_ANSRC));
806 }
807
808 /**
809 * @brief Set I/O compensation cell code for PMOS transistors
810 * @rmtoll SYSCFG_CMPCR RAPSRC LL_SYSCFG_SetPMOSCompensationCode
811 * @param PMOSCode PMOS compensation code
812 * This code is applied to the I/O compensation cell when the CS bit of the
813 * SYSCFG_CMPCR is set
814 * @retval None
815 */
LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)816 __STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
817 {
818 MODIFY_REG(SYSCFG->CMPCR, SYSCFG_CMPCR_RAPSRC, PMOSCode);
819 }
820
821 /**
822 * @brief Get I/O compensation cell code for PMOS transistors
823 * @rmtoll SYSCFG_CMPCR RAPSRC LL_SYSCFG_GetPMOSCompensationCode
824 * @retval Returned value is the I/O compensation cell code for PMOS transistors
825 */
LL_SYSCFG_GetPMOSCompensationCode(void)826 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
827 {
828 return (uint32_t)(READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_RAPSRC));
829 }
830
831 /**
832 * @brief Set I/O compensation cell code for NMOS transistors
833 * @rmtoll SYSCFG_CMPCR RANSRC LL_SYSCFG_SetNMOSCompensationCode
834 * @param NMOSCode: NMOS compensation code
835 * This code is applied to the I/O compensation cell when the CS bit of the
836 * SYSCFG_CMPCR is set
837 * @retval None
838 */
LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)839 __STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
840 {
841 MODIFY_REG(SYSCFG->CMPCR, SYSCFG_CMPCR_RANSRC, NMOSCode);
842 }
843
844 /**
845 * @brief Get I/O compensation cell code for NMOS transistors
846 * @rmtoll SYSCFG_CMPCR RANSRC LL_SYSCFG_GetNMOSCompensationCode
847 * @retval Returned value is the I/O compensation cell code for NMOS transistors
848 */
LL_SYSCFG_GetNMOSCompensationCode(void)849 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
850 {
851 return (uint32_t)(READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_RANSRC));
852 }
853
854 /**
855 * @brief Set connections to TIM1/8/15/16/17 Break inputs
856 * @note this feature is available on STM32MP1 rev.B and above
857 * @rmtoll SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs\n
858 * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs
859 * @param Break This parameter can be a combination of the following values:
860 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
861 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
862 * @retval None
863 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)864 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
865 {
866 MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_PVDL | SYSCFG_CBR_CLL, Break);
867 }
868
869 /**
870 * @brief Get connections to TIM1/8/15/16/17 Break inputs
871 * @note this feature is available on STM32MP1 rev.B and above
872 * @rmtoll
873 * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs\n
874 * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs
875 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
876 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
877 */
LL_SYSCFG_GetTIMBreakInputs(void)878 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
879 {
880 return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL | SYSCFG_CBR_CLL));
881 }
882
883
884 /**
885 * @}
886 */
887
888 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
889 * @{
890 */
891
892 /**
893 * @brief Return the device identifier
894 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
895 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
896 */
LL_DBGMCU_GetDeviceID(void)897 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
898 {
899 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
900 }
901
902 /**
903 * @brief Return the device revision identifier
904 * @note This field indicates the revision of the device.
905 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
906 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
907 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
908 */
LL_DBGMCU_GetRevisionID(void)909 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
910 {
911 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
912 }
913
914 /**
915 * @brief Enable D1 Domain debug during SLEEP mode
916 * @rmtoll DBGMCU_CR DBGSLEEP LL_DBGMCU_EnableDebugInSleepMode
917 * @retval None
918 */
LL_DBGMCU_EnableDebugInSleepMode(void)919 __STATIC_INLINE void LL_DBGMCU_EnableDebugInSleepMode(void)
920 {
921 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
922 }
923
924 /**
925 * @brief Disable D1 Domain debug during SLEEP mode
926 * @rmtoll DBGMCU_CR DBGSLEEP LL_DBGMCU_DisableDebugInSleepMode
927 * @retval None
928 */
LL_DBGMCU_DisableDebugInSleepMode(void)929 __STATIC_INLINE void LL_DBGMCU_DisableDebugInSleepMode(void)
930 {
931 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
932 }
933
934 /**
935 * @brief Enable D1 Domain debug during STOP mode
936 * @rmtoll DBGMCU_CR DBGSTOP LL_DBGMCU_EnableDebugInStopMode
937 * @retval None
938 */
LL_DBGMCU_EnableDebugInStopMode(void)939 __STATIC_INLINE void LL_DBGMCU_EnableDebugInStopMode(void)
940 {
941 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
942 }
943
944 /**
945 * @brief Disable D1 Domain debug during STOP mode
946 * @rmtoll DBGMCU_CR DBGSTOP LL_DBGMCU_DisableDebugInStopMode
947 * @retval None
948 */
LL_DBGMCU_DisableDebugInStopMode(void)949 __STATIC_INLINE void LL_DBGMCU_DisableDebugInStopMode(void)
950 {
951 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
952 }
953
954 /**
955 * @brief Enable D1 Domain debug during STANDBY mode
956 * @rmtoll DBGMCU_CR DBGSTBY LL_DBGMCU_EnableDebugInStandbyMode
957 * @retval None
958 */
LL_DBGMCU_EnableDebugInStandbyMode(void)959 __STATIC_INLINE void LL_DBGMCU_EnableDebugInStandbyMode(void)
960 {
961 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
962 }
963
964 /**
965 * @brief Disable D1 Domain debug during STANDBY mode
966 * @rmtoll DBGMCU_CR DBGSTBY LL_DBGMCU_DisableDebugInStandbyMode
967 * @retval None
968 */
LL_DBGMCU_DisableDebugInStandbyMode(void)969 __STATIC_INLINE void LL_DBGMCU_DisableDebugInStandbyMode(void)
970 {
971 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
972 }
973
974 /**
975 * @brief Set the direction of the bi-directional trigger pin TRGIO
976 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n
977 * @param PinDirection This parameter can be one of the following values:
978 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
979 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
980 * @retval None
981 */
LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)982 __STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
983 {
984 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
985 }
986
987 /**
988 * @brief Get the direction of the bi-directional trigger pin TRGIO
989 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n
990 * @retval Returned value can be one of the following values:
991 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
992 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
993 */
LL_DBGMCU_GetExternalTriggerPinDirection(void)994 __STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
995 {
996 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
997 }
998
999 /**
1000 * @brief Set the Watchdog Timer behaviour
1001 * @rmtoll DBGMCU_CR WDFZCTL LL_DBGMCU_SetWatchdogTimerBehaviour\n
1002 * @param PinBehaviour This parameter can be one of the following values:
1003 * @arg @ref LL_DBGMCU_IWDG_FREEZE_1CA7_HALT
1004 * @arg @ref LL_DBGMCU_IWDG_FREEZE_2CA7_HALT
1005 * @retval None
1006 */
LL_DBGMCU_SetWatchdogTimerBehaviour(uint32_t PinBehaviour)1007 __STATIC_INLINE void LL_DBGMCU_SetWatchdogTimerBehaviour(uint32_t PinBehaviour)
1008 {
1009 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_WDFZCTL, PinBehaviour);
1010 }
1011
1012 /**
1013 * @brief Get the Watchdog Timer behaviour
1014 * @rmtoll DBGMCU_CR WDFZCTL LL_DBGMCU_GetWatchdogTimerBehaviour\n
1015 * @retval Returned value can be one of the following values:
1016 * @arg @ref LL_DBGMCU_IWDG_FREEZE_1CA7_HALT
1017 * @arg @ref LL_DBGMCU_IWDG_FREEZE_2CA7_HALT
1018 */
LL_DBGMCU_GetWatchdogTimerBehaviour(void)1019 __STATIC_INLINE uint32_t LL_DBGMCU_GetWatchdogTimerBehaviour(void)
1020 {
1021 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WDFZCTL));
1022 }
1023
1024 /**
1025 * @brief Freeze APB1 group1 peripherals
1026 * @rmtoll DBGMCU_APB1FZ2 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1027 * DBGMCU_APB1FZ2 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1028 * DBGMCU_APB1FZ2 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1029 * DBGMCU_APB1FZ2 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1030 * DBGMCU_APB1FZ2 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1031 * DBGMCU_APB1FZ2 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1032 * DBGMCU_APB1FZ2 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1033 * DBGMCU_APB1FZ2 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1034 * DBGMCU_APB1FZ2 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1035 * DBGMCU_APB1FZ2 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1036 * DBGMCU_APB1FZ2 WWDG1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1037 * DBGMCU_APB1FZ2 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1038 * DBGMCU_APB1FZ2 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1039 * DBGMCU_APB1FZ2 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1040 * DBGMCU_APB1FZ2 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1041 * @param Periphs This parameter can be a combination of the following values:
1042 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1043 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1044 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1045 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1046 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1047 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1048 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1049 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1050 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1051 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1052 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG1_STOP
1053 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1054 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1055 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1056 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP
1057 * @retval None
1058 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1059 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1060 {
1061 SET_BIT(DBGMCU->APB1FZ2, Periphs);
1062 }
1063
1064 /**
1065 * @brief Unfreeze APB1 group1 peripherals
1066 * @rmtoll DBGMCU_APB1FZ2 TIM2 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1067 * DBGMCU_APB1FZ2 TIM3 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1068 * DBGMCU_APB1FZ2 TIM4 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1069 * DBGMCU_APB1FZ2 TIM5 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1070 * DBGMCU_APB1FZ2 TIM6 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1071 * DBGMCU_APB1FZ2 TIM7 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1072 * DBGMCU_APB1FZ2 TIM12 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1073 * DBGMCU_APB1FZ2 TIM13 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1074 * DBGMCU_APB1FZ2 TIM14 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1075 * DBGMCU_APB1FZ2 LPTIM1 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1076 * DBGMCU_APB1FZ2 WWDG1 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1077 * DBGMCU_APB1FZ2 I2C1 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1078 * DBGMCU_APB1FZ2 I2C2 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1079 * DBGMCU_APB1FZ2 I2C3 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1080 * DBGMCU_APB1FZ2 I2C5 LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1081 * @param Periphs This parameter can be a combination of the following values:
1082 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1083 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1084 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1085 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1086 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1087 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1088 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1089 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1090 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1091 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1092 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG1_STOP
1093 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1094 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1095 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1096 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP
1097 * @retval None
1098 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1099 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1100 {
1101 CLEAR_BIT(DBGMCU->APB1FZ2, Periphs);
1102 }
1103
1104 /**
1105 * @brief Freeze APB2 group1 peripherals
1106 * @rmtoll DBGMCU_APB2FZ2 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1107 * DBGMCU_APB2FZ2 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1108 * DBGMCU_APB2FZ2 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1109 * DBGMCU_APB2FZ2 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1110 * DBGMCU_APB2FZ2 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1111 * DBGMCU_APB2FZ2 FDCAN LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1112 * @param Periphs This parameter can be a combination of the following values:
1113 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1114 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1115 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1116 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1117 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1118 * @arg @ref LL_DBGMCU_APB2_GRP1_FDCAN_STOP
1119 * @retval None
1120 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1121 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1122 {
1123 SET_BIT(DBGMCU->APB2FZ2, Periphs);
1124 }
1125
1126 /**
1127 * @brief Unfreeze APB2 group1 peripherals
1128 * @rmtoll DBGMCU_APB2FZ2 TIM1 LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1129 * DBGMCU_APB2FZ2 TIM8 LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1130 * DBGMCU_APB2FZ2 TIM15 LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1131 * DBGMCU_APB2FZ2 TIM16 LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1132 * DBGMCU_APB2FZ2 TIM17 LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1133 * DBGMCU_APB2FZ2 FDCAN LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1134 * @param Periphs This parameter can be a combination of the following values:
1135 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1136 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1137 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1138 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1139 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1140 * @arg @ref LL_DBGMCU_APB2_GRP1_FDCAN_STOP
1141 * @retval None
1142 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1143 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1144 {
1145 CLEAR_BIT(DBGMCU->APB2FZ2, Periphs);
1146 }
1147
1148 /**
1149 * @brief Freeze APB3 peripherals
1150 * @rmtoll DBGMCU_APB3FZ2 LPTIM2 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
1151 * DBGMCU_APB3FZ2 LPTIM3 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
1152 * DBGMCU_APB3FZ2 LPTIM4 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
1153 * DBGMCU_APB3FZ2 LPTIM5 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
1154 * @param Periphs This parameter can be a combination of the following values:
1155 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM2_STOP
1156 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
1157 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
1158 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM5_STOP
1159 * @retval None
1160 */
LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)1161 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
1162 {
1163 SET_BIT(DBGMCU->APB3FZ2, Periphs);
1164 }
1165
1166 /**
1167 * @brief Unfreeze APB3 peripherals
1168 * @rmtoll DBGMCU_APB3FZ2 LPTIM2 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
1169 * DBGMCU_APB3FZ2 LPTIM3 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
1170 * DBGMCU_APB3FZ2 LPTIM4 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
1171 * DBGMCU_APB3FZ2 LPTIM5 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
1172 * @param Periphs This parameter can be a combination of the following values:
1173 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM2_STOP
1174 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
1175 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
1176 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM5_STOP
1177 * @retval None
1178 */
LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)1179 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
1180 {
1181 CLEAR_BIT(DBGMCU->APB3FZ2, Periphs);
1182 }
1183
1184 /**
1185 * @brief Freeze APB5 peripherals
1186 * @rmtoll DBGMCU_APB5FZ2 I2C4 LL_DBGMCU_APB5_GRP1_FreezePeriph\n
1187 * DBGMCU_APB5FZ2 RTC LL_DBGMCU_APB5_GRP1_FreezePeriph\n
1188 * DBGMCU_APB5FZ2 I2C6 LL_DBGMCU_APB5_GRP1_FreezePeriph\n
1189 * @param Periphs This parameter can be a combination of the following values:
1190 * @arg @ref LL_DBGMCU_APB5_GRP1_I2C4_STOP
1191 * @arg @ref LL_DBGMCU_APB5_GRP1_RTC_STOP
1192 * @arg @ref LL_DBGMCU_APB5_GRP1_I2C6_STOP
1193 * @retval None
1194 */
LL_DBGMCU_APB5_GRP1_FreezePeriph(uint32_t Periphs)1195 __STATIC_INLINE void LL_DBGMCU_APB5_GRP1_FreezePeriph(uint32_t Periphs)
1196 {
1197 SET_BIT(DBGMCU->APB5FZ2, Periphs);
1198 }
1199
1200 /**
1201 * @brief Unfreeze APB5 peripherals
1202 * @rmtoll DBGMCU_APB5FZ2 I2C4 LL_DBGMCU_APB5_GRP1_UnFreezePeriph\n
1203 * DBGMCU_APB5FZ2 RTC LL_DBGMCU_APB5_GRP1_UnFreezePeriph\n
1204 * DBGMCU_APB5FZ2 I2C6 LL_DBGMCU_APB5_GRP1_UnFreezePeriph\n
1205 * @param Periphs This parameter can be a combination of the following values:
1206 * @arg @ref LL_DBGMCU_APB5_GRP1_I2C4_STOP
1207 * @arg @ref LL_DBGMCU_APB5_GRP1_RTC_STOP
1208 * @arg @ref LL_DBGMCU_APB5_GRP1_I2C6_STOP
1209 * @retval None
1210 */
LL_DBGMCU_APB5_GRP1_UnFreezePeriph(uint32_t Periphs)1211 __STATIC_INLINE void LL_DBGMCU_APB5_GRP1_UnFreezePeriph(uint32_t Periphs)
1212 {
1213 CLEAR_BIT(DBGMCU->APB5FZ2, Periphs);
1214 }
1215 /**
1216 * @}
1217 */
1218
1219 /**
1220 * @}
1221 */
1222
1223 /**
1224 * @}
1225 */
1226
1227 #endif /* defined (SYSCFG) || defined (DBGMCU) */
1228
1229 /**
1230 * @}
1231 */
1232
1233 #ifdef __cplusplus
1234 }
1235 #endif
1236
1237 #endif /* STM32MP1xx_LL_SYSTEM_H */
1238
