1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2019 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef STM32G4xx_LL_BUS_H
37 #define STM32G4xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32g4xx.h"
45
46 /** @addtogroup STM32G4xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58
59 /* Private constants ---------------------------------------------------------*/
60
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
74 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
75 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
76 #define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
77 #define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
78 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
79 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
80 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
81 /**
82 * @}
83 */
84
85 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
86 * @{
87 */
88 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
89 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
90 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
91 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
92 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
93 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
94 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
95 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
96 #define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSMEN
97 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
98 #define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN
99 #if defined(ADC345_COMMON)
100 #define LL_AHB2_GRP1_PERIPH_ADC345 RCC_AHB2ENR_ADC345EN
101 #endif /* ADC345_COMMON */
102 #define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
103 #if defined(DAC2)
104 #define LL_AHB2_GRP1_PERIPH_DAC2 RCC_AHB2ENR_DAC2EN
105 #endif /* DAC2 */
106 #define LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN
107 #if defined(DAC4)
108 #define LL_AHB2_GRP1_PERIPH_DAC4 RCC_AHB2ENR_DAC4EN
109 #endif /* DAC4 */
110 #if defined(AES)
111 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
112 #endif /* AES */
113 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
114 /**
115 * @}
116 */
117
118 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
119 * @{
120 */
121 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
122 #if defined(FMC_Bank1_R)
123 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
124 #endif /* FMC_Bank1_R */
125 #if defined(QUADSPI)
126 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
127 #endif /* QUADSPI */
128 /**
129 * @}
130 */
131
132 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
133 * @{
134 */
135 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
136 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
137 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
138 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
139 #if defined(TIM5)
140 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
141 #endif /* TIM5 */
142 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
143 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
144 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
145 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
146 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
147 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
148 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
149 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
150 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
151 #if defined(UART4)
152 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
153 #endif /* UART4 */
154 #if defined(UART5)
155 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
156 #endif /* UART5 */
157 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
158 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
159 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
160 #if defined(FDCAN1)
161 #define LL_APB1_GRP1_PERIPH_FDCAN RCC_APB1ENR1_FDCANEN
162 #endif /* FDCAN1 */
163 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
164 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
165 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
166 /**
167 * @}
168 */
169
170
171 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
172 * @{
173 */
174 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
175 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
176 #if defined(I2C4)
177 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
178 #endif /* I2C4 */
179 #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
180 /**
181 * @}
182 */
183
184 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
185 * @{
186 */
187 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
188 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
189 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
190 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
191 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
192 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
193 #if defined(SPI4)
194 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
195 #endif /* SPI4 */
196 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
197 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
198 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
199 #if defined(TIM20)
200 #define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
201 #endif /* TIM20 */
202 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
203 #if defined(HRTIM1)
204 #define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
205 #endif /* HRTIM1 */
206 /**
207 * @}
208 */
209
210 /**
211 * @}
212 */
213
214 /* Exported macro ------------------------------------------------------------*/
215 /* Exported functions --------------------------------------------------------*/
216 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
217 * @{
218 */
219
220 /** @defgroup BUS_LL_EF_AHB1 AHB1
221 * @{
222 */
223
224 /**
225 * @brief Enable AHB1 peripherals clock.
226 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
227 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
228 * AHB1ENR DMAMMUXEN LL_AHB1_GRP1_EnableClock\n
229 * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
230 * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
231 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
232 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
233 * @param Periphs This parameter can be a combination of the following values:
234 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
235 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
236 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
237 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
238 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
239 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
240 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
241 * @retval None
242 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)243 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
244 {
245 __IO uint32_t tmpreg;
246 SET_BIT(RCC->AHB1ENR, Periphs);
247 /* Delay after an RCC peripheral clock enabling */
248 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
249 (void)tmpreg;
250 }
251
252 /**
253 * @brief Check if AHB1 peripheral clock is enabled or not
254 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
255 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
256 * AHB1ENR DMAMUXEN LL_AHB1_GRP1_IsEnabledClock\n
257 * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
258 * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
259 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
260 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
261 * @param Periphs This parameter can be a combination of the following values:
262 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
263 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
264 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
265 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
266 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
267 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
268 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
269 * @retval State of Periphs (1 or 0).
270 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)271 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
272 {
273 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
274 }
275
276 /**
277 * @brief Disable AHB1 peripherals clock.
278 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
279 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
280 * AHB1ENR DMAMUXEN LL_AHB1_GRP1_DisableClock\n
281 * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
282 * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
283 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
284 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
285 * @param Periphs This parameter can be a combination of the following values:
286 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
287 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
288 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
289 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
290 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
291 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
292 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
293 * @retval None
294 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)295 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
296 {
297 CLEAR_BIT(RCC->AHB1ENR, Periphs);
298 }
299
300 /**
301 * @brief Force AHB1 peripherals reset.
302 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
303 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
304 * AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ForceReset\n
305 * AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset\n
306 * AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset\n
307 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
308 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
309 * @param Periphs This parameter can be a combination of the following values:
310 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
311 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
312 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
313 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
314 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
315 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
316 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
317 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
318 * @retval None
319 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)320 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
321 {
322 SET_BIT(RCC->AHB1RSTR, Periphs);
323 }
324
325 /**
326 * @brief Release AHB1 peripherals reset.
327 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
328 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
329 * AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ReleaseReset\n
330 * AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset\n
331 * AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset\n
332 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
333 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
334 * @param Periphs This parameter can be a combination of the following values:
335 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
336 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
337 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
338 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
339 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
340 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
341 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
342 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
343 * @retval None
344 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)345 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
346 {
347 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
348 }
349
350 /**
351 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
352 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
353 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
354 * AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
355 * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
356 * AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
357 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
358 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
359 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
360 * @param Periphs This parameter can be a combination of the following values:
361 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
362 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
363 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
364 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
365 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
366 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
367 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
368 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
369 * @retval None
370 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)371 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
372 {
373 __IO uint32_t tmpreg;
374 SET_BIT(RCC->AHB1SMENR, Periphs);
375 /* Delay after an RCC peripheral clock enabling */
376 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
377 (void)tmpreg;
378 }
379
380 /**
381 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
382 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
383 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
384 * AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
385 * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
386 * AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
387 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
388 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
389 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
390 * @param Periphs This parameter can be a combination of the following values:
391 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
392 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
393 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
394 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
395 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
396 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
397 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
398 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
399 * @retval None
400 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)401 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
402 {
403 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
404 }
405
406 /**
407 * @}
408 */
409
410 /** @defgroup BUS_LL_EF_AHB2 AHB2
411 * @{
412 */
413
414 /**
415 * @brief Enable AHB2 peripherals clock.
416 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
417 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
418 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
419 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
420 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
421 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
422 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
423 * AHB2ENR ADC12EN LL_AHB2_GRP1_EnableClock\n
424 * AHB2ENR ADC345EN LL_AHB2_GRP1_EnableClock\n
425 * AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock\n
426 * AHB2ENR DAC2EN LL_AHB2_GRP1_EnableClock\n
427 * AHB2ENR DAC3EN LL_AHB2_GRP1_EnableClock\n
428 * AHB2ENR DAC4EN LL_AHB2_GRP1_EnableClock\n
429 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
430 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
431 * @param Periphs This parameter can be a combination of the following values:
432 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
433 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
434 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
435 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
436 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
437 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
438 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
439 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
440 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
441 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
442 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
443 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
444 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
445 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
446 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
447 *
448 * (*) value not defined in all devices.
449 * @retval None
450 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)451 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
452 {
453 __IO uint32_t tmpreg;
454 SET_BIT(RCC->AHB2ENR, Periphs);
455 /* Delay after an RCC peripheral clock enabling */
456 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
457 (void)tmpreg;
458 }
459
460 /**
461 * @brief Check if AHB2 peripheral clock is enabled or not
462 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
463 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
464 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
465 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
466 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
467 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
468 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
469 * AHB2ENR ADC12EN LL_AHB2_GRP1_IsEnabledClock\n
470 * AHB2ENR ADC345EN LL_AHB2_GRP1_IsEnabledClock\n
471 * AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock\n
472 * AHB2ENR DAC2EN LL_AHB2_GRP1_IsEnabledClock\n
473 * AHB2ENR DAC3EN LL_AHB2_GRP1_IsEnabledClock\n
474 * AHB2ENR DAC4EN LL_AHB2_GRP1_IsEnabledClock\n
475 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
476 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
477 * @param Periphs This parameter can be a combination of the following values:
478 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
479 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
480 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
481 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
482 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
483 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
484 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
485 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
486 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
487 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
488 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
489 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
490 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
491 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
492 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
493 *
494 * (*) value not defined in all devices.
495 * @retval State of Periphs (1 or 0).
496 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)497 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
498 {
499 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
500 }
501
502 /**
503 * @brief Disable AHB2 peripherals clock.
504 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
505 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
506 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
507 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
508 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
509 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
510 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
511 * AHB2ENR ADC12EN LL_AHB2_GRP1_DisableClock\n
512 * AHB2ENR ADC345EN LL_AHB2_GRP1_DisableClock\n
513 * AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock\n
514 * AHB2ENR DAC2EN LL_AHB2_GRP1_DisableClock\n
515 * AHB2ENR DAC3EN LL_AHB2_GRP1_DisableClock\n
516 * AHB2ENR DAC4EN LL_AHB2_GRP1_DisableClock\n
517 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
518 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
519 * @param Periphs This parameter can be a combination of the following values:
520 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
521 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
522 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
523 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
524 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
525 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
526 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
527 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
528 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
529 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
530 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
531 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
532 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
533 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
534 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
535 *
536 * (*) value not defined in all devices.
537 * @retval None
538 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)539 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
540 {
541 CLEAR_BIT(RCC->AHB2ENR, Periphs);
542 }
543
544 /**
545 * @brief Force AHB2 peripherals reset.
546 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
547 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
548 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
549 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
550 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
551 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
552 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
553 * AHB2RSTR ADC12RST LL_AHB2_GRP1_ForceReset\n
554 * AHB2RSTR ADC345RST LL_AHB2_GRP1_ForceReset\n
555 * AHB2RSTR DAC1RST LL_AHB2_GRP1_ForceReset\n
556 * AHB2RSTR DAC2RST LL_AHB2_GRP1_ForceReset\n
557 * AHB2RSTR DAC3RST LL_AHB2_GRP1_ForceReset\n
558 * AHB2RSTR DAC4RST LL_AHB2_GRP1_ForceReset\n
559 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
560 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
561 * @param Periphs This parameter can be a combination of the following values:
562 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
563 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
564 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
565 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
566 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
567 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
568 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
569 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
570 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
571 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
572 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
573 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
574 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
575 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
576 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
577 *
578 * (*) value not defined in all devices.
579 * @retval None
580 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)581 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
582 {
583 SET_BIT(RCC->AHB2RSTR, Periphs);
584 }
585
586 /**
587 * @brief Release AHB2 peripherals reset.
588 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
589 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
590 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
591 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
592 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
593 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
594 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
595 * AHB2RSTR ADC12RST LL_AHB2_GRP1_ReleaseReset\n
596 * AHB2RSTR ADC345RST LL_AHB2_GRP1_ReleaseReset\n
597 * AHB2RSTR DAC1RST LL_AHB2_GRP1_ReleaseReset\n
598 * AHB2RSTR DAC2RST LL_AHB2_GRP1_ReleaseReset\n
599 * AHB2RSTR DAC3RST LL_AHB2_GRP1_ReleaseReset\n
600 * AHB2RSTR DAC4RST LL_AHB2_GRP1_ReleaseReset\n
601 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
602 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
603 * @param Periphs This parameter can be a combination of the following values:
604 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
605 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
606 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
607 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
608 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
609 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
610 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
611 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
612 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
613 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
614 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
615 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
616 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
617 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
618 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
619 *
620 * (*) value not defined in all devices.
621 * @retval None
622 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)623 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
624 {
625 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
626 }
627
628 /**
629 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
630 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
631 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
632 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
633 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
634 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
635 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
636 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
637 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
638 * AHB2SMENR CCMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
639 * AHB2SMENR ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
640 * AHB2SMENR ADC345SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
641 * AHB2SMENR DAC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
642 * AHB2SMENR DAC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
643 * AHB2SMENR DAC3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
644 * AHB2SMENR DAC4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
645 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
646 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
647 * @param Periphs This parameter can be a combination of the following values:
648 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
649 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
650 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
651 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
652 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
653 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
654 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
655 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
656 * @arg @ref LL_AHB2_GRP1_PERIPH_CCM
657 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
658 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
659 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
660 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
661 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
662 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
663 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
664 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
665 *
666 * (*) value not defined in all devices.
667 * @retval None
668 */
LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)669 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
670 {
671 __IO uint32_t tmpreg;
672 SET_BIT(RCC->AHB2SMENR, Periphs);
673 /* Delay after an RCC peripheral clock enabling */
674 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
675 (void)tmpreg;
676 }
677
678 /**
679 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
680 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
681 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
682 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
683 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
684 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
685 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
686 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
687 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
688 * AHB2SMENR CCMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
689 * AHB2SMENR ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
690 * AHB2SMENR ADC345SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
691 * AHB2SMENR DAC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
692 * AHB2SMENR DAC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
693 * AHB2SMENR DAC3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
694 * AHB2SMENR DAC4SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
695 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
696 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
697 * @param Periphs This parameter can be a combination of the following values:
698 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
699 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
700 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
701 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
702 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
703 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
704 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
705 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
706 * @arg @ref LL_AHB2_GRP1_PERIPH_CCM
707 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
708 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
709 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
710 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
711 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
712 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
713 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
714 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
715 *
716 * (*) value not defined in all devices.
717 * @retval None
718 */
LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)719 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
720 {
721 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
722 }
723
724 /**
725 * @}
726 */
727
728 /** @defgroup BUS_LL_EF_AHB3 AHB3
729 * @{
730 */
731
732 /**
733 * @brief Enable AHB3 peripherals clock.
734 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
735 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
736 * @param Periphs This parameter can be a combination of the following values:
737 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
738 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
739 *
740 * (*) value not defined in all devices.
741 * @retval None
742 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)743 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
744 {
745 __IO uint32_t tmpreg;
746 SET_BIT(RCC->AHB3ENR, Periphs);
747 /* Delay after an RCC peripheral clock enabling */
748 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
749 (void)tmpreg;
750 }
751
752 /**
753 * @brief Check if AHB3 peripheral clock is enabled or not
754 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
755 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
756 * @param Periphs This parameter can be a combination of the following values:
757 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
758 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
759 *
760 * (*) value not defined in all devices.
761 * @retval State of Periphs (1 or 0).
762 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)763 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
764 {
765 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
766 }
767
768 /**
769 * @brief Disable AHB3 peripherals clock.
770 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
771 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
772 * @param Periphs This parameter can be a combination of the following values:
773 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
774 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
775 *
776 * (*) value not defined in all devices.
777 * @retval None
778 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)779 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
780 {
781 CLEAR_BIT(RCC->AHB3ENR, Periphs);
782 }
783
784 /**
785 * @brief Force AHB3 peripherals reset.
786 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
787 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
788 * @param Periphs This parameter can be a combination of the following values:
789 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
790 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
791 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
792 *
793 * (*) value not defined in all devices.
794 * @retval None
795 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)796 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
797 {
798 SET_BIT(RCC->AHB3RSTR, Periphs);
799 }
800
801 /**
802 * @brief Release AHB3 peripherals reset.
803 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
804 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
805 * @param Periphs This parameter can be a combination of the following values:
806 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
807 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
808 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
809 *
810 * (*) value not defined in all devices.
811 * @retval None
812 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)813 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
814 {
815 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
816 }
817
818 /**
819 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
820 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
821 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
822 * @param Periphs This parameter can be a combination of the following values:
823 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
824 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
825 *
826 * (*) value not defined in all devices.
827 * @retval None
828 */
LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)829 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
830 {
831 __IO uint32_t tmpreg;
832 SET_BIT(RCC->AHB3SMENR, Periphs);
833 /* Delay after an RCC peripheral clock enabling */
834 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
835 (void)tmpreg;
836 }
837
838 /**
839 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
840 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
841 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
842 * @param Periphs This parameter can be a combination of the following values:
843 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
844 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
845 *
846 * (*) value not defined in all devices.
847 * @retval None
848 */
LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)849 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
850 {
851 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
852 }
853
854 /**
855 * @}
856 */
857
858 /** @defgroup BUS_LL_EF_APB1 APB1
859 * @{
860 */
861
862 /**
863 * @brief Enable APB1 peripherals clock.
864 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
865 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
866 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
867 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
868 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
869 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
870 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
871 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
872 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
873 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
874 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
875 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
876 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
877 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
878 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
879 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
880 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
881 * APB1ENR1 USBEN LL_APB1_GRP1_EnableClock\n
882 * APB1ENR1 FDCANEN LL_APB1_GRP1_EnableClock\n
883 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
884 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
885 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
886 * @param Periphs This parameter can be a combination of the following values:
887 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
888 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
889 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
890 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
891 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
892 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
893 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
894 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
895 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
896 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
897 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
898 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
899 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
900 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
901 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
902 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
903 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
904 * @arg @ref LL_APB1_GRP1_PERIPH_USB
905 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
906 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
907 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
908 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
909 *
910 * (*) value not defined in all devices.
911 * @retval None
912 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)913 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
914 {
915 __IO uint32_t tmpreg;
916 SET_BIT(RCC->APB1ENR1, Periphs);
917 /* Delay after an RCC peripheral clock enabling */
918 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
919 (void)tmpreg;
920 }
921
922 /**
923 * @brief Enable APB1 peripherals clock.
924 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
925 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
926 * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
927 * @param Periphs This parameter can be a combination of the following values:
928 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
929 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
930 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
931 *
932 * (*) value not defined in all devices.
933 * @retval None
934 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)935 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
936 {
937 __IO uint32_t tmpreg;
938 SET_BIT(RCC->APB1ENR2, Periphs);
939 /* Delay after an RCC peripheral clock enabling */
940 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
941 (void)tmpreg;
942 }
943
944 /**
945 * @brief Check if APB1 peripheral clock is enabled or not
946 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
947 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
948 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
949 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
950 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
951 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
952 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
953 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
954 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
955 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
956 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
957 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
958 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
959 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
960 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
961 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
962 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
963 * APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
964 * APB1ENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock\n
965 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
966 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
967 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
968 * @param Periphs This parameter can be a combination of the following values:
969 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
970 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
971 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
972 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
973 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
974 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
975 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
976 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
977 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
978 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
979 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
980 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
981 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
982 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
983 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
984 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
985 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
986 * @arg @ref LL_APB1_GRP1_PERIPH_USB
987 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
988 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
989 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
990 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
991 *
992 * (*) value not defined in all devices.
993 * @retval State of Periphs (1 or 0).
994 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)995 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
996 {
997 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
998 }
999
1000 /**
1001 * @brief Check if APB1 peripheral clock is enabled or not
1002 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
1003 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
1004 * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
1005 * @param Periphs This parameter can be a combination of the following values:
1006 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1007 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1008 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1009 *
1010 * (*) value not defined in all devices.
1011 * @retval State of Periphs (1 or 0).
1012 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1013 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1014 {
1015 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1016 }
1017
1018 /**
1019 * @brief Disable APB1 peripherals clock.
1020 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1021 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1022 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
1023 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
1024 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
1025 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
1026 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
1027 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
1028 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
1029 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1030 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
1031 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1032 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
1033 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
1034 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
1035 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1036 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1037 * APB1ENR1 USBEN LL_APB1_GRP1_DisableClock\n
1038 * APB1ENR1 FDCANEN LL_APB1_GRP1_DisableClock\n
1039 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
1040 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1041 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
1042 * @param Periphs This parameter can be a combination of the following values:
1043 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1044 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1045 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1046 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1047 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1048 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1049 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1050 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1051 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1052 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1053 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1054 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1055 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1056 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1057 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1058 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1059 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1060 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1061 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1062 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1063 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1064 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1065 *
1066 * (*) value not defined in all devices.
1067 * @retval None
1068 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1069 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1070 {
1071 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1072 }
1073
1074 /**
1075 * @brief Disable APB1 peripherals clock.
1076 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
1077 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
1078 * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
1079 * @param Periphs This parameter can be a combination of the following values:
1080 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1081 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1082 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1083 *
1084 * (*) value not defined in all devices.
1085 * @retval None
1086 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1087 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1088 {
1089 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1090 }
1091
1092 /**
1093 * @brief Force APB1 peripherals reset.
1094 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1095 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1096 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
1097 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
1098 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
1099 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
1100 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
1101 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1102 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
1103 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1104 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
1105 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
1106 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
1107 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1108 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
1109 * APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset\n
1110 * APB1RSTR1 FDCANRST LL_APB1_GRP1_ForceReset\n
1111 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
1112 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1113 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1114 * @param Periphs This parameter can be a combination of the following values:
1115 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1116 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1117 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1118 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1119 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1120 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1121 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1122 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1123 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1124 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1125 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1126 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1127 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1128 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1129 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1130 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1131 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1132 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1133 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1134 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1135 *
1136 * (*) value not defined in all devices.
1137 * @retval None
1138 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1139 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1140 {
1141 SET_BIT(RCC->APB1RSTR1, Periphs);
1142 }
1143
1144 /**
1145 * @brief Force APB1 peripherals reset.
1146 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1147 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
1148 * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ForceReset
1149 * @param Periphs This parameter can be a combination of the following values:
1150 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1151 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1152 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1153 *
1154 * (*) value not defined in all devices.
1155 * @retval None
1156 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1157 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1158 {
1159 SET_BIT(RCC->APB1RSTR2, Periphs);
1160 }
1161
1162 /**
1163 * @brief Release APB1 peripherals reset.
1164 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1165 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1166 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
1167 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
1168 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
1169 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
1170 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
1171 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1172 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
1173 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1174 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
1175 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
1176 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
1177 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1178 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
1179 * APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
1180 * APB1RSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset\n
1181 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
1182 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1183 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1184 * @param Periphs This parameter can be a combination of the following values:
1185 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1186 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1187 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1188 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1189 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1190 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1191 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1192 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1193 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1194 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1195 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1196 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1197 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1198 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1199 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1200 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1201 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1202 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1203 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1204 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1205 *
1206 * (*) value not defined in all devices.
1207 * @retval None
1208 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1209 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1210 {
1211 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1212 }
1213
1214 /**
1215 * @brief Release APB1 peripherals reset.
1216 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1217 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
1218 * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
1219 * @param Periphs This parameter can be a combination of the following values:
1220 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1221 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1222 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1223 *
1224 * (*) value not defined in all devices.
1225 * @retval None
1226 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1227 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1228 {
1229 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1230 }
1231
1232 /**
1233 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1234 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1235 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1236 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1237 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1238 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1239 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1240 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1241 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1242 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1243 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1244 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1245 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1246 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1247 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1248 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1249 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1250 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1251 * APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1252 * APB1SMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1253 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1254 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1255 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
1256 * @param Periphs This parameter can be a combination of the following values:
1257 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1258 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1259 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1260 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1261 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1262 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1263 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1264 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1265 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1266 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1267 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1268 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1269 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1270 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1271 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1272 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1273 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1274 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1275 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1276 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1277 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1278 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1279 *
1280 * (*) value not defined in all devices.
1281 * @retval None
1282 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)1283 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
1284 {
1285 __IO uint32_t tmpreg;
1286 SET_BIT(RCC->APB1SMENR1, Periphs);
1287 /* Delay after an RCC peripheral clock enabling */
1288 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1289 (void)tmpreg;
1290 }
1291
1292 /**
1293 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1294 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1295 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1296 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep
1297 * @param Periphs This parameter can be a combination of the following values:
1298 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1299 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1300 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
1301 *
1302 * (*) value not defined in all devices.
1303 * @retval None
1304 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)1305 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1306 {
1307 __IO uint32_t tmpreg;
1308 SET_BIT(RCC->APB1SMENR2, Periphs);
1309 /* Delay after an RCC peripheral clock enabling */
1310 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1311 (void)tmpreg;
1312 }
1313
1314 /**
1315 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1316 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1317 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1318 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1319 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1320 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1321 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1322 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1323 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1324 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1325 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1326 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1327 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1328 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1329 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1330 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1331 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1332 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1333 * APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1334 * APB1SMENR1 FDCANSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1335 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1336 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1337 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
1338 * @param Periphs This parameter can be a combination of the following values:
1339 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1340 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1341 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1342 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1343 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1344 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1345 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1346 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1347 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1348 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1349 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1350 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1351 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1352 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1353 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1354 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1355 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1356 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1357 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1358 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1359 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1360 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1361 *
1362 * (*) value not defined in all devices.
1363 * @retval None
1364 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)1365 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
1366 {
1367 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1368 }
1369
1370 /**
1371 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1372 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1373 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1374 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
1375 * @param Periphs This parameter can be a combination of the following values:
1376 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1377 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1378 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
1379 *
1380 * (*) value not defined in all devices.
1381 * @retval None
1382 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)1383 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1384 {
1385 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1386 }
1387
1388 /**
1389 * @}
1390 */
1391
1392 /** @defgroup BUS_LL_EF_APB2 APB2
1393 * @{
1394 */
1395
1396 /**
1397 * @brief Enable APB2 peripherals clock.
1398 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1399 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1400 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1401 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1402 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1403 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1404 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
1405 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1406 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1407 * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
1408 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1409 * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock
1410 * @param Periphs This parameter can be a combination of the following values:
1411 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1412 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1413 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1414 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1415 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1416 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1417 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1418 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1419 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1420 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1421 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1422 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1423 *
1424 * (*) value not defined in all devices.
1425 * @retval None
1426 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1427 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1428 {
1429 __IO uint32_t tmpreg;
1430 SET_BIT(RCC->APB2ENR, Periphs);
1431 /* Delay after an RCC peripheral clock enabling */
1432 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1433 (void)tmpreg;
1434 }
1435
1436 /**
1437 * @brief Check if APB2 peripheral clock is enabled or not
1438 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1439 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1440 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1441 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1442 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1443 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1444 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
1445 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1446 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1447 * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
1448 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1449 * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock
1450 * @param Periphs This parameter can be a combination of the following values:
1451 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1452 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1453 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1454 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1455 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1456 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1457 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1458 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1459 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1460 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1461 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1462 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1463 *
1464 * (*) value not defined in all devices.
1465 * @retval State of Periphs (1 or 0).
1466 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1467 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1468 {
1469 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1470 }
1471
1472 /**
1473 * @brief Disable APB2 peripherals clock.
1474 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1475 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1476 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1477 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1478 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1479 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1480 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
1481 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1482 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1483 * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
1484 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1485 * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock
1486 * @param Periphs This parameter can be a combination of the following values:
1487 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1488 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1489 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1490 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1491 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1492 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1493 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1494 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1495 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1496 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1497 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1498 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1499 *
1500 * (*) value not defined in all devices.
1501 * @retval None
1502 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1503 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1504 {
1505 CLEAR_BIT(RCC->APB2ENR, Periphs);
1506 }
1507
1508 /**
1509 * @brief Force APB2 peripherals reset.
1510 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1511 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1512 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1513 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1514 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1515 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1516 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
1517 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1518 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1519 * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
1520 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1521 * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
1522 * @param Periphs This parameter can be a combination of the following values:
1523 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1524 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1525 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1526 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1527 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1528 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1529 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1530 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1531 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1532 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1533 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1534 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1535 *
1536 * (*) value not defined in all devices.
1537 * @retval None
1538 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1539 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1540 {
1541 SET_BIT(RCC->APB2RSTR, Periphs);
1542 }
1543
1544 /**
1545 * @brief Release APB2 peripherals reset.
1546 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1547 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1548 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1549 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1550 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1551 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1552 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
1553 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1554 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1555 * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
1556 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1557 * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
1558 * @param Periphs This parameter can be a combination of the following values:
1559 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1560 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1561 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1562 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1563 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1564 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1565 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1566 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1567 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1568 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1569 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1570 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1571 *
1572 * (*) value not defined in all devices.
1573 * @retval None
1574 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1575 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1576 {
1577 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1578 }
1579
1580 /**
1581 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1582 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1583 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1584 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1585 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1586 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1587 * APB2SMENR SPI4SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1588 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1589 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1590 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1591 * APB2SMENR TIM20SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1592 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1593 * APB2SMENR HRTIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
1594 * @param Periphs This parameter can be a combination of the following values:
1595 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1596 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1597 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1598 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1599 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1600 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1601 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1602 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1603 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1604 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1605 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1606 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1607 *
1608 * (*) value not defined in all devices.
1609 * @retval None
1610 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1611 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1612 {
1613 __IO uint32_t tmpreg;
1614 SET_BIT(RCC->APB2SMENR, Periphs);
1615 /* Delay after an RCC peripheral clock enabling */
1616 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1617 (void)tmpreg;
1618 }
1619
1620 /**
1621 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1622 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1623 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1624 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1625 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1626 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1627 * APB2SMENR SPI4SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1628 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1629 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1630 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1631 * APB2SMENR TIM20SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1632 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1633 * APB2SMENR HRTIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
1634 * @param Periphs This parameter can be a combination of the following values:
1635 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1636 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1637 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1638 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1639 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1640 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1641 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1642 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1643 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1644 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1645 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1646 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1647 *
1648 * (*) value not defined in all devices.
1649 * @retval None
1650 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1651 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1652 {
1653 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1654 }
1655
1656 /**
1657 * @}
1658 */
1659
1660
1661 /**
1662 * @}
1663 */
1664
1665 /**
1666 * @}
1667 */
1668
1669 #endif /* defined(RCC) */
1670
1671 /**
1672 * @}
1673 */
1674
1675 #ifdef __cplusplus
1676 }
1677 #endif
1678
1679 #endif /* STM32G4xx_LL_BUS_H */
1680
1681
