1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB , APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB , APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2022 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file
30 * in the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32H5xx_LL_BUS_H
38 #define __STM32H5xx_LL_BUS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32h5xx.h"
46
47 /** @addtogroup STM32H5xx_LL_Driver
48 * @{
49 */
50
51 #if defined(RCC)
52
53 /** @defgroup BUS_LL BUS
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /* Private macros ------------------------------------------------------------*/
61
62 /* Exported types ------------------------------------------------------------*/
63 /* Exported constants --------------------------------------------------------*/
64 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
65 * @{
66 */
67
68 /** @defgroup BUS_LL_AHB_BRANCH_CLK_AHBx
69 * @{
70 */
71 #define LL_AHB_BRANCH_CLK_AHB1 RCC_CFGR2_AHB1DIS
72 #define LL_AHB_BRANCH_CLK_AHB2 RCC_CFGR2_AHB2DIS
73 #if defined(AHB4PERIPH_BASE)
74 #define LL_AHB_BRANCH_CLK_AHB4 RCC_CFGR2_AHB4DIS
75 #endif /* AHB4PERIPH_BASE */
76 /**
77 * @}
78 */
79
80 /** @defgroup BUS_LL_APB_BRANCH_CLK_APBx
81 * @{
82 */
83 #define LL_APB_BRANCH_CLK_APB1 RCC_CFGR2_APB1DIS
84 #define LL_APB_BRANCH_CLK_APB2 RCC_CFGR2_APB2DIS
85 #define LL_APB_BRANCH_CLK_APB3 RCC_CFGR2_APB3DIS
86 /**
87 * @}
88 */
89
90 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
91 * @{
92 */
93 #if defined(CORDIC)
94 #define LL_AHB1_GRP1_PERIPH_ALL 0xF13AD103U
95 #else
96 #define LL_AHB1_GRP1_PERIPH_ALL 0x91021103U
97 #endif /* CORDIC */
98 #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
99 #define LL_AHB1_GRP1_PERIPH_GPDMA2 RCC_AHB1ENR_GPDMA2EN
100 #if defined(CORDIC)
101 #define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
102 #endif /* CORDIC */
103 #if defined(FMAC)
104 #define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
105 #endif /* FMAC */
106 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLITFEN
107 #if defined(ETH)
108 #define LL_AHB1_GRP1_PERIPH_ETH RCC_AHB1ENR_ETHEN
109 #define LL_AHB1_GRP1_PERIPH_ETHTX RCC_AHB1ENR_ETHTXEN
110 #define LL_AHB1_GRP1_PERIPH_ETHRX RCC_AHB1ENR_ETHRXEN
111 #endif /* ETH */
112 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
113 #define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN
114 #define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_TZSC1EN
115 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPRAMEN
116 #define LL_AHB1_GRP1_PERIPH_ICACHE RCC_AHB1LPENR_ICACHELPEN
117 #if defined(DCACHE1)
118 #define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN
119 #endif /* DCACHE1 */
120 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN
121 /**
122 * @}
123 */
124
125 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
126 * @{
127 */
128 #if defined(GPIOE)
129 #define LL_AHB2_GRP1_PERIPH_ALL 0xC01F1DFFU
130 #else
131 #define LL_AHB2_GRP1_PERIPH_ALL 0x40060C8FU
132 #endif /* GPIOE */
133 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
134 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
135 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
136 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
137 #if defined(GPIOE)
138 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
139 #endif /* GPIOE */
140 #if defined(GPIOF)
141 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
142 #endif /* GPIOF */
143 #if defined(GPIOG)
144 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
145 #endif /* GPIOG */
146 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
147 #if defined(GPIOI)
148 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
149 #endif /* GPIOI */
150 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
151 #define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
152 #if defined(DCMI)
153 #define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR_DCMI_PSSIEN
154 #endif /* DCMI */
155 #if defined(AES)
156 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
157 #endif /* AES */
158 #if defined(HASH)
159 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
160 #endif /* HASH */
161 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
162 #if defined(PKA)
163 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN
164 #endif /* PKA */
165 #if defined(SAES)
166 #define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR_SAESEN
167 #endif /* SAES */
168 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR_SRAM2EN
169 #if defined(SRAM3_BASE)
170 #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR_SRAM3EN
171 #endif /* SRAM3_BASE */
172
173 /**
174 * @}
175 */
176 #if defined(AHB4PERIPH_BASE)
177 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
178 * @{
179 */
180 #define LL_AHB4_GRP1_PERIPH_ALL 0x00111880U
181 #define LL_AHB4_GRP1_PERIPH_OTFDEC RCC_AHB4ENR_OTFDEC1EN
182 #define LL_AHB4_GRP1_PERIPH_SDMMC1 RCC_AHB4ENR_SDMMC1EN
183 #if defined(SDMMC2)
184 #define LL_AHB4_GRP1_PERIPH_SDMMC2 RCC_AHB4ENR_SDMMC2EN
185 #endif /* SDMMC2*/
186 #define LL_AHB4_GRP1_PERIPH_FMC RCC_AHB4ENR_FMCEN
187 #define LL_AHB4_GRP1_PERIPH_OSPI1 RCC_AHB4ENR_OCTOSPI1EN
188 /**
189 * @}
190 */
191 #endif /* AHB4PERIPH_BASE */
192
193 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
194 * @{
195 */
196 #if defined(TIM4)
197 #define LL_APB1_GRP1_PERIPH_ALL 0xDFFEC9FFU
198 #else
199 #define LL_APB1_GRP1_PERIPH_ALL 0x01E7E833U
200 #endif /* TIM4 */
201 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
202 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
203 #if defined(TIM4)
204 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
205 #endif /* TIM4*/
206 #if defined(TIM5)
207 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
208 #endif /* TIM5*/
209 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
210 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
211 #if defined(TIM12)
212 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
213 #endif /* TIM12*/
214 #if defined(TIM13)
215 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
216 #endif /* TIM13*/
217 #if defined(TIM14)
218 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
219 #endif /* TIM14*/
220 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1LENR_WWDGEN
221 #if defined(OPAMP1)
222 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1LENR_OPAMPEN
223 #endif /* OPAMP1 */
224 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
225 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
226 #if defined(COMP1)
227 #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1LENR_COMPEN
228 #endif /* COMP1 */
229 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
230 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
231 #if defined(UART4)
232 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
233 #endif /* UART4*/
234 #if defined(UART5)
235 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
236 #endif /* UART5*/
237 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
238 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
239 #define LL_APB1_GRP1_PERIPH_I3C1 RCC_APB1LENR_I3C1EN
240 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1LENR_CRSEN
241 #if defined(USART6)
242 #define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1LENR_USART6EN
243 #endif /* USART6*/
244 #if defined(USART10)
245 #define LL_APB1_GRP1_PERIPH_USART10 RCC_APB1LENR_USART10EN
246 #endif /* USART10*/
247 #if defined(USART11)
248 #define LL_APB1_GRP1_PERIPH_USART11 RCC_APB1LENR_USART11EN
249 #endif /* USART11*/
250 #if defined(CEC)
251 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
252 #endif /* CEC*/
253 #if defined(UART7)
254 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
255 #endif /* UART7 */
256 #if defined(UART8)
257 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
258 #endif /* UART8 */
259 /**
260 * @}
261 */
262
263
264 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
265 * @{
266 */
267 #if defined(UART9)
268 #define LL_APB1_GRP2_PERIPH_ALL 0x0080022BU
269 #else
270 #define LL_APB1_GRP2_PERIPH_ALL 0x00000228U
271 #endif /* UART9 */
272 #if defined(UART9)
273 #define LL_APB1_GRP2_PERIPH_UART9 RCC_APB1HENR_UART9EN
274 #endif /* UART9 */
275 #if defined(UART12)
276 #define LL_APB1_GRP2_PERIPH_UART12 RCC_APB1HENR_UART12EN
277 #endif /* UART12*/
278 #define LL_APB1_GRP2_PERIPH_DTS RCC_APB1HENR_DTSEN
279 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1HENR_LPTIM2EN
280 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
281 #if defined(UCPD1)
282 #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1HENR_UCPD1EN
283 #endif /* UCPD1 */
284 /**
285 * @}
286 */
287
288 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
289 * @{
290 */
291 #if defined(TIM8)
292 #define LL_APB2_GRP1_PERIPH_ALL 0x017F7800U
293 #else
294 #define LL_APB2_GRP1_PERIPH_ALL 0x01005800U
295 #endif /* TIM8 */
296 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
297 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
298 #if defined(TIM8)
299 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
300 #endif /* TIM8 */
301 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
302 #if defined(TIM15)
303 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
304 #endif /* TIM15 */
305 #if defined(TIM16)
306 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
307 #endif /* TIM16 */
308 #if defined(TIM17)
309 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
310 #endif /* TIM17 */
311 #if defined(SPI4)
312 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
313 #endif /* SPI4 */
314 #if defined(SPI6)
315 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
316 #endif /* SPI6 */
317 #if defined(SAI1)
318 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
319 #endif /* SAI1 */
320 #if defined(SAI2)
321 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
322 #endif /* SAI2 */
323 #define LL_APB2_GRP1_PERIPH_USB RCC_APB2ENR_USBEN
324 /**
325 * @}
326 */
327
328 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
329 * @{
330 */
331 #if defined(SPI5)
332 #define LL_APB3_GRP1_PERIPH_ALL 0x0030F9E2U
333 #else
334 #define LL_APB3_GRP1_PERIPH_ALL 0x00300A42U
335 #endif /* SPI5 */
336 #define LL_APB3_GRP1_PERIPH_SBS RCC_APB3ENR_SBSEN
337 #if defined(SPI5)
338 #define LL_APB3_GRP1_PERIPH_SPI5 RCC_APB3ENR_SPI5EN
339 #endif /* SPI5 */
340 #define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN
341 #if defined(I2C3)
342 #define LL_APB3_GRP1_PERIPH_I2C3 RCC_APB3ENR_I2C3EN
343 #endif /* I2C3 */
344 #if defined(I2C4)
345 #define LL_APB3_GRP1_PERIPH_I2C4 RCC_APB3ENR_I2C4EN
346 #endif /* I2C4 */
347 #if defined(I3C2)
348 #define LL_APB3_GRP1_PERIPH_I3C2 RCC_APB3ENR_I3C2EN
349 #endif /* I3C2 */
350 #define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN
351 #if defined(LPTIM3)
352 #define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_APB3ENR_LPTIM3EN
353 #endif /* LPTIM3 */
354 #if defined(LPTIM4)
355 #define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_APB3ENR_LPTIM4EN
356 #endif /* LPTIM4 */
357 #if defined(LPTIM5)
358 #define LL_APB3_GRP1_PERIPH_LPTIM5 RCC_APB3ENR_LPTIM5EN
359 #endif /* LPTIM5 */
360 #if defined(LPTIM6)
361 #define LL_APB3_GRP1_PERIPH_LPTIM6 RCC_APB3ENR_LPTIM6EN
362 #endif /* LPTIM6 */
363 #define LL_APB3_GRP1_PERIPH_VREF RCC_APB3ENR_VREFEN
364 #define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN
365 /**
366 * @}
367 */
368
369 /**
370 * @}
371 */
372
373 /* Exported macro ------------------------------------------------------------*/
374 /* Exported functions --------------------------------------------------------*/
375 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
376 * @{
377 */
378
379 /** @defgroup BUS_LL_EF_AHBx AHBx
380 * @{
381 */
382 /**
383 * @brief Disable of AHBx Clock Branch
384 * @rmtoll CFGR2 AHB1DIS LL_AHB_DisableClock\n
385 * CFGR2 AHB2DIS LL_AHB_DisableClock\n
386 * CFGR2 AHB4DIS LL_AHB_DisableClock
387 * @param AHBx This parameter can be a combination of the following values:
388 * @arg @ref LL_AHB_BRANCH_CLK_AHB1
389 * @arg @ref LL_AHB_BRANCH_CLK_AHB2
390 * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*)
391 *
392 * (*) : Not available for all stm32h5xxxx family lines.
393 * @retval None
394 */
LL_AHB_DisableClock(uint32_t AHBx)395 __STATIC_INLINE void LL_AHB_DisableClock(uint32_t AHBx)
396 {
397 SET_BIT(RCC->CFGR2, AHBx);
398 }
399
400 /**
401 * @brief Enable of AHBx Clock Branch
402 * @rmtoll CFGR2 AHB1DIS LL_AHB_EnableClock\n
403 * CFGR2 AHB2DIS LL_AHB_EnableClock\n
404 * CFGR2 AHB4DIS LL_AHB_EnableClock
405 * @param AHBx This parameter can be a combination of the following values:
406 * @arg @ref LL_AHB_BRANCH_CLK_AHB1
407 * @arg @ref LL_AHB_BRANCH_CLK_AHB2
408 * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*)
409 *
410 * (*) : Not available for all stm32h5xxxx family lines.
411 * @retval None
412 */
LL_AHB_EnableClock(uint32_t AHBx)413 __STATIC_INLINE void LL_AHB_EnableClock(uint32_t AHBx)
414 {
415 __IO uint32_t tmpreg;
416 CLEAR_BIT(RCC->CFGR2, AHBx);
417 /* Delay after AHBx clock branch enabling */
418 tmpreg = READ_BIT(RCC->CFGR2, AHBx);
419 (void)tmpreg;
420 }
421
422 /**
423 * @brief Check if AHBx clock branch is disabled or not
424 * @rmtoll CFGR2 AHB1DIS LL_AHB_IsDisabledClock\n
425 * CFGR2 AHB2DIS LL_AHB_IsDisabledClock\n
426 * CFGR2 AHB4DIS LL_AHB_IsDisabledClock
427 * @param AHBx This parameter can be a combination of the following values:
428 * @arg @ref LL_AHB_BRANCH_CLK_AHB1
429 * @arg @ref LL_AHB_BRANCH_CLK_AHB2
430 * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*)
431 *
432 * (*) : Not available for all stm32h5xxxx family lines.
433 * @retval State of AHBx bus (1 or 0).
434 */
LL_AHB_IsDisabledClock(uint32_t AHBx)435 __STATIC_INLINE uint32_t LL_AHB_IsDisabledClock(uint32_t AHBx)
436 {
437 return ((READ_BIT(RCC->CFGR2, AHBx) == AHBx) ? 1UL : 0UL);
438 }
439
440 /**
441 * @}
442 */
443
444 /** @defgroup BUS_LL_EF_APBx APBx
445 * @{
446 */
447 /**
448 * @brief Disable APBx Clock Branch
449 * @rmtoll CFGR2 APB1DIS LL_APB_DisableClock\n
450 * CFGR2 APB2DIS LL_APB_DisableClock\n
451 * CFGR2 APB3DIS LL_APB_DisableClock
452 * @param APBx This parameter can be a combination of the following values:
453 * @arg @ref LL_APB_BRANCH_CLOCK_APB1
454 * @arg @ref LL_APB_BRANCH_CLOCK_APB2
455 * @arg @ref LL_APB_BRANCH_CLOCK_APB3
456 * @retval None
457 */
LL_APB_DisableClock(uint32_t APBx)458 __STATIC_INLINE void LL_APB_DisableClock(uint32_t APBx)
459 {
460 SET_BIT(RCC->CFGR2, APBx);
461 }
462
463 /**
464 * @brief Enable of APBx Clock Branch
465 * @rmtoll CFGR2 APB1DIS LL_APB_EnableClock\n
466 * CFGR2 APB2DIS LL_APB_EnableClock\n
467 * CFGR2 APB3DIS LL_APB_EnableClock
468 * @param APBx This parameter can be a combination of the following values:
469 * @arg @ref LL_APB_BRANCH_CLOCK_APB1
470 * @arg @ref LL_APB_BRANCH_CLOCK_APB2
471 * @arg @ref LL_APB_BRANCH_CLOCK_APB3
472 * @retval None
473 */
LL_APB_EnableClock(uint32_t APBx)474 __STATIC_INLINE void LL_APB_EnableClock(uint32_t APBx)
475 {
476 __IO uint32_t tmpreg;
477 CLEAR_BIT(RCC->CFGR2, APBx);
478 /* Delay after APBx clock branch enabling */
479 tmpreg = READ_BIT(RCC->CFGR2, APBx);
480 (void)tmpreg;
481 }
482
483 /**
484 * @brief Check if APBx clock branch is disabled or not
485 * @rmtoll CFGR2 APB1DIS LL_APB_IsDisabledClock\n
486 * CFGR2 APB2DIS LL_APB_IsDisabledClock\n
487 * CFGR2 APB3DIS LL_APB_IsDisabledClock
488 * @param APBx This parameter can be a combination of the following values:
489 * @arg @ref LL_APB_BRANCH_CLK_APB1
490 * @arg @ref LL_APB_BRANCH_CLK_APB2
491 * @arg @ref LL_APB_BRANCH_CLK_APB3
492 * @retval State of APBx bus (1 or 0).
493 */
LL_APB_IsDisabledClock(uint32_t APBx)494 __STATIC_INLINE uint32_t LL_APB_IsDisabledClock(uint32_t APBx)
495 {
496 return ((READ_BIT(RCC->CFGR2, APBx) == APBx) ? 1UL : 0UL);
497 }
498
499 /**
500 * @}
501 */
502
503 /** @defgroup BUS_LL_EF_AHB1 AHB1
504 * @{
505 */
506 /**
507 * @brief Enable AHB1 peripherals clock.
508 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n
509 * AHB1ENR GPDMA2EN LL_AHB1_GRP1_EnableClock\n
510 * AHB1ENR FLITFEN LL_AHB1_GRP1_EnableClock\n
511 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
512 * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
513 * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
514 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n
515 * AHB1ENR ETHEN LL_AHB1_GRP1_EnableClock\n
516 * AHB1ENR ETHTXEN LL_AHB1_GRP1_EnableClock\n
517 * AHB1ENR ETHRXEN LL_AHB1_GRP1_EnableClock\n
518 * AHB1ENR TZSC1EN LL_AHB1_GRP1_EnableClock\n
519 * AHB1ENR BKPRAMEN LL_AHB1_GRP1_EnableClock\n
520 * AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n
521 * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock
522 * @param Periphs This parameter can be a combination of the following values:
523 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
524 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
525 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
526 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
527 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
528 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
529 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
530 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
531 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
532 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
533 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
534 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
535 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
536 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE (*)
537 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
538 *
539 * (*) : Not available for all stm32h5xxxx family lines.
540 * @retval None
541 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)542 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
543 {
544 __IO uint32_t tmpreg;
545 SET_BIT(RCC->AHB1ENR, Periphs);
546 /* Delay after an RCC peripheral clock enabling */
547 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
548 (void)tmpreg;
549 }
550
551 /**
552 * @brief Check if AHB1 peripheral clock is enabled or not
553 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n
554 * AHB1ENR GPDMA2EN LL_AHB1_GRP1_IsEnabledClock\n
555 * AHB1ENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
556 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
557 * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
558 * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
559 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n
560 * AHB1ENR ETHEN LL_AHB1_GRP1_IsEnabledClock\n
561 * AHB1ENR ETHTXEN LL_AHB1_GRP1_IsEnabledClock\n
562 * AHB1ENR ETHRXEN LL_AHB1_GRP1_IsEnabledClock\n
563 * AHB1ENR TZSC1EN LL_AHB1_GRP1_IsEnabledClock\n
564 * AHB1ENR BKPRAMEN LL_AHB1_GRP1_IsEnabledClock\n
565 * AHB1ENR DCACHE1EN LL_AHB1_GRP1_IsEnabledClock\n
566 * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock
567 * @param Periphs This parameter can be a combination of the following values:
568 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
569 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
570 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
571 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
572 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
573 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
574 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
575 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
576 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
577 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
578 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
579 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
580 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
581 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE (*)
582 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
583 *
584 * (*) : Not available for all stm32h5xxxx family lines.
585 * @retval State of Periphs (1 or 0).
586 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)587 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
588 {
589 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
590 }
591
592 /**
593 * @brief Disable AHB1 peripherals clock.
594 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n
595 * AHB1ENR GPDMA2EN LL_AHB1_GRP1_DisableClock\n
596 * AHB1ENR FLITFEN LL_AHB1_GRP1_DisableClock\n
597 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
598 * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
599 * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
600 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n
601 * AHB1ENR ETHEN LL_AHB1_GRP1_DisableClock\n
602 * AHB1ENR ETHTXEN LL_AHB1_GRP1_DisableClock\n
603 * AHB1ENR ETHRXEN LL_AHB1_GRP1_DisableClock\n
604 * AHB1ENR TZSC1EN LL_AHB1_GRP1_DisableClock\n
605 * AHB1ENR BKPRAMEN LL_AHB1_GRP1_DisableClock\n
606 * AHB1ENR DCACHE1EN LL_AHB1_GRP1_DisableClock\n
607 * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock
608 * @param Periphs This parameter can be a combination of the following values:
609 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
610 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
611 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
612 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
613 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
614 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
615 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
616 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
617 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
618 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
619 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
620 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
621 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
622 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE (*)
623 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
624 *
625 * (*) : Not available for all stm32h5xxxx family lines.
626 * @retval None
627 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)628 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
629 {
630 CLEAR_BIT(RCC->AHB1ENR, Periphs);
631 }
632
633 /**
634 * @brief Force AHB1 peripherals reset.
635 * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ForceReset\n
636 * AHB1RSTR GPDMA2RST LL_AHB1_GRP1_ForceReset\n
637 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
638 * AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset\n
639 * AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset\n
640 * AHB1RSTR RAMCFGRST LL_AHB1_GRP1_ForceReset\n
641 * AHB1RSTR ETHRST LL_AHB1_GRP1_ForceReset\n
642 * AHB1RSTR TZSC1RST LL_AHB1_GRP1_ForceReset
643 * @param Periphs This parameter can be a combination of the following values:
644 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
645 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
646 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
647 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
648 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
649 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
650 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
651 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
652 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
653 *
654 * (*) : Not available for all stm32h5xxxx family lines.
655 * @retval None
656 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)657 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
658 {
659 SET_BIT(RCC->AHB1RSTR, Periphs);
660 }
661
662 /**
663 * @brief Release AHB1 peripherals reset.
664 * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ReleaseReset\n
665 * AHB1RSTR GPDMA2RST LL_AHB1_GRP1_ReleaseReset\n
666 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
667 * AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset\n
668 * AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset\n
669 * AHB1RSTR RAMCFGRST LL_AHB1_GRP1_ReleaseReset\n
670 * AHB1RSTR ETHRST LL_AHB1_GRP1_ReleaseReset\n
671 * AHB1RSTR TZSC1RST LL_AHB1_GRP1_ReleaseReset
672 * @param Periphs This parameter can be a combination of the following values:
673 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
674 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
675 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
676 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
677 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
678 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
679 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
680 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
681 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
682 *
683 * (*) : Not available for all stm32h5xxxx family lines.
684 * @retval None
685 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)686 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
687 {
688 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
689 }
690
691 /**
692 * @brief Enable AHB1 peripheral clocks in Sleep mode
693 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
694 * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
695 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n
696 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n
697 * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_EnableClockSleep\n
698 * AHB1LPENR FMACLPEN LL_AHB1_GRP1_EnableClockSleep\n
699 * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_EnableClockSleep\n
700 * AHB1LPENR ETHLPEN LL_AHB1_GRP1_EnableClockSleep\n
701 * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_EnableClockSleep\n
702 * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_EnableClockSleep\n
703 * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_EnableClockSleep\n
704 * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n
705 * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_EnableClockSleep\n
706 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockSleep
707 * @param Periphs This parameter can be a combination of the following values:
708 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
709 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
710 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
711 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
712 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
713 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
714 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
715 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
716 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
717 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
718 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
719 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
720 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
721 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE (*)
722 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
723 *
724 * (*) : Not available for all stm32h5xxxx family lines.
725 * @retval None
726 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)727 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
728 {
729 __IO uint32_t tmpreg;
730 SET_BIT(RCC->AHB1LPENR, Periphs);
731 /* Delay after an RCC peripheral clock enabling */
732 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
733 (void)tmpreg;
734 }
735
736 /**
737 * @brief Check if AHB1 peripheral clocks in Sleep mode is enabled or not
738 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
739 * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
740 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
741 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
742 * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
743 * AHB1LPENR FMACLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
744 * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
745 * AHB1LPENR ETHLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
746 * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
747 * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
748 * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
749 * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
750 * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
751 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_IsEnabledClockSleep
752 * @param Periphs This parameter can be a combination of the following values:
753 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
754 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
755 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
756 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
757 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
758 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
759 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
760 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
761 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
762 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
763 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
764 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
765 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
766 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE (*)
767 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
768 *
769 * (*) : Not available for all stm32h5xxxx family lines.
770 * @retval State of Periphs (1 or 0).
771 */
LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)772 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)
773 {
774 return ((READ_BIT(RCC->AHB1LPENR, Periphs) == Periphs) ? 1UL : 0UL);
775 }
776
777 /**
778 * @brief Disable AHB1 peripheral clocks in Sleep mode
779 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
780 * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
781 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n
782 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n
783 * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_DisableClockSleep\n
784 * AHB1LPENR FMACLPEN LL_AHB1_GRP1_DisableClockSleep\n
785 * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_DisableClockSleep\n
786 * AHB1LPENR ETHLPEN LL_AHB1_GRP1_DisableClockSleep\n
787 * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_DisableClockSleep\n
788 * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_DisableClockSleep\n
789 * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_DisableClockSleep\n
790 * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n
791 * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_DisableClockSleep\n
792 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockSleep
793 * @param Periphs This parameter can be a combination of the following values:
794 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
795 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
796 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
797 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
798 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
799 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
800 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
801 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
802 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
803 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
804 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
805 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
806 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
807 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE (*)
808 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
809 *
810 * (*) : Not available for all stm32h5xxxx family lines.
811 * @retval None
812 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)813 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
814 {
815 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
816 }
817
818 /**
819 * @}
820 */
821
822 /** @defgroup BUS_LL_EF_AHB2 AHB2
823 * @{
824 */
825 /**
826 * @brief Enable AHB2 peripherals clock.
827 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
828 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
829 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
830 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
831 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
832 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
833 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
834 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
835 * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
836 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
837 * AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock\n
838 * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n
839 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
840 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
841 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
842 * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n
843 * AHB2ENR SAESEN LL_AHB2_GRP1_EnableClock\n
844 * AHB2ENR SRAM2EN LL_AHB2_GRP1_EnableClock\n
845 * AHB2ENR SRAM3EN LL_AHB2_GRP1_EnableClock
846 * @param Periphs This parameter can be a combination of the following values:
847 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
848 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
849 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
850 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
851 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
852 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
853 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
854 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
855 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
856 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
857 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
858 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
859 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
860 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
861 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
862 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
863 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
864 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
865 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
866 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
867 *
868 * (*) : Not available for all stm32h5xxxx family lines.
869 * @retval None
870 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)871 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
872 {
873 __IO uint32_t tmpreg;
874 SET_BIT(RCC->AHB2ENR, Periphs);
875 /* Delay after an RCC peripheral clock enabling */
876 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
877 (void)tmpreg;
878 }
879
880 /**
881 * @brief Check if AHB2 peripheral clock is enabled or not
882 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
883 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
884 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
885 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
886 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
887 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
888 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
889 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
890 * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
891 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
892 * AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock\n
893 * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n
894 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
895 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
896 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
897 * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n
898 * AHB2ENR SAESEN LL_AHB2_GRP1_IsEnabledClock\n
899 * AHB2ENR SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
900 * AHB2ENR SRAM3EN LL_AHB2_GRP1_IsEnabledClock
901 * @param Periphs This parameter can be a combination of the following values:
902 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
903 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
904 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
905 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
906 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
907 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
908 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
909 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
910 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
911 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
912 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
913 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
914 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
915 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
916 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
917 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
918 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
919 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
920 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
921 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
922 *
923 * (*) : Not available for all stm32h5xxxx family lines.
924 * @retval State of Periphs (1 or 0).
925 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)926 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
927 {
928 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
929 }
930
931 /**
932 * @brief Disable AHB2 peripherals clock.
933 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
934 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
935 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
936 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
937 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
938 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
939 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
940 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
941 * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
942 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
943 * AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock\n
944 * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n
945 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
946 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
947 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
948 * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n
949 * AHB2ENR SAESEN LL_AHB2_GRP1_DisableClock\n
950 * AHB2ENR SRAM2EN LL_AHB2_GRP1_DisableClock\n
951 * AHB2ENR SRAM3EN LL_AHB2_GRP1_DisableClock
952 * @param Periphs This parameter can be a combination of the following values:
953 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
954 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
955 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
956 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
957 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
958 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
959 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
960 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
961 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
962 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
963 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
964 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
965 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
966 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
967 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
968 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
969 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
970 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
971 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
972 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
973 *
974 * (*) : Not available for all stm32h5xxxx family lines.
975 * @retval None
976 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)977 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
978 {
979 CLEAR_BIT(RCC->AHB2ENR, Periphs);
980 }
981
982 /**
983 * @brief Force AHB2 peripherals reset.
984 * @rmtoll AHB2RST GPIOARST LL_AHB2_GRP1_ForceReset\n
985 * AHB2RST GPIOBRST LL_AHB2_GRP1_ForceReset\n
986 * AHB2RST GPIOCRST LL_AHB2_GRP1_ForceReset\n
987 * AHB2RST GPIODRST LL_AHB2_GRP1_ForceReset\n
988 * AHB2RST GPIOERST LL_AHB2_GRP1_ForceReset\n
989 * AHB2RST GPIOFRST LL_AHB2_GRP1_ForceReset\n
990 * AHB2RST GPIOGRST LL_AHB2_GRP1_ForceReset\n
991 * AHB2RST GPIOHRST LL_AHB2_GRP1_ForceReset\n
992 * AHB2RST GPIOIRST LL_AHB2_GRP1_ForceReset\n
993 * AHB2RST ADCRST LL_AHB2_GRP1_ForceReset\n
994 * AHB2RST DAC1RST LL_AHB2_GRP1_ForceReset\n
995 * AHB2RST DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n
996 * AHB2RST AESRST LL_AHB2_GRP1_ForceReset\n
997 * AHB2RST HASHRST LL_AHB2_GRP1_ForceReset\n
998 * AHB2RST RNGRST LL_AHB2_GRP1_ForceReset\n
999 * AHB2RST PKARST LL_AHB2_GRP1_ForceReset\n
1000 * AHB2RST SAESRST LL_AHB2_GRP1_ForceReset
1001 * @param Periphs This parameter can be a combination of the following values:
1002 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1003 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1004 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1005 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1006 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1007 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1008 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1009 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1010 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1011 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1012 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1013 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1014 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1015 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1016 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1017 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1018 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1019 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1020 *
1021 * (*) : Not available for all stm32h5xxxx family lines.
1022 * @retval None
1023 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)1024 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
1025 {
1026 SET_BIT(RCC->AHB2RSTR, Periphs);
1027 }
1028
1029 /**
1030 * @brief Release AHB2 peripherals reset.
1031 * @rmtoll AHB2RST GPIOARST LL_AHB2_GRP1_ReleaseReset\n
1032 * AHB2RST GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
1033 * AHB2RST GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
1034 * AHB2RST GPIODRST LL_AHB2_GRP1_ReleaseReset\n
1035 * AHB2RST GPIOERST LL_AHB2_GRP1_ReleaseReset\n
1036 * AHB2RST GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
1037 * AHB2RST GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
1038 * AHB2RST GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
1039 * AHB2RST GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
1040 * AHB2RST ADCRST LL_AHB2_GRP1_ReleaseReset\n
1041 * AHB2RST DAC1RST LL_AHB2_GRP1_ReleaseReset\n
1042 * AHB2RST DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n
1043 * AHB2RST AESRST LL_AHB2_GRP1_ReleaseReset\n
1044 * AHB2RST HASHRST LL_AHB2_GRP1_ReleaseReset\n
1045 * AHB2RST RNGRST LL_AHB2_GRP1_ReleaseReset\n
1046 * AHB2RST PKARST LL_AHB2_GRP1_ReleaseReset\n
1047 * AHB2RST SAESRST LL_AHB2_GRP1_ReleaseReset
1048 * @param Periphs This parameter can be a combination of the following values:
1049 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1050 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1051 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1052 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1053 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1054 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1055 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1056 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1057 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1058 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1059 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1060 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1061 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1062 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1063 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1064 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1065 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1066 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1067 *
1068 * (*) : Not available for all stm32h5xxxx family lines.
1069 * @retval None
1070 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)1071 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
1072 {
1073 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
1074 }
1075
1076 /**
1077 * @brief Enable AHB2 peripheral clocks in Sleep mode
1078 * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_EnableClockSleep\n
1079 * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_EnableClockSleep\n
1080 * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_EnableClockSleep\n
1081 * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_EnableClockSleep\n
1082 * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_EnableClockSleep\n
1083 * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_EnableClockSleep\n
1084 * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_EnableClockSleep\n
1085 * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_EnableClockSleep\n
1086 * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_EnableClockSleep\n
1087 * AHB2LPENR ADCLPEN LL_AHB2_GRP1_EnableClockSleep\n
1088 * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_EnableClockSleep\n
1089 * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_EnableClockSleep\n
1090 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockSleep\n
1091 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n
1092 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n
1093 * AHB2LPENR PKALPEN LL_AHB2_GRP1_EnableClockSleep\n
1094 * AHB2LPENR SAESLPEN LL_AHB2_GRP1_EnableClockSleep\n
1095 * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n
1096 * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep
1097 * @param Periphs This parameter can be a combination of the following values:
1098 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1099 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1100 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1101 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1102 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1103 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1104 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1105 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1106 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1107 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1108 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1109 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1110 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1111 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1112 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1113 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1114 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1115 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1116 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
1117 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1118 *
1119 * (*) : Not available for all stm32h5xxxx family lines.
1120 * @retval None
1121 */
LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)1122 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
1123 {
1124 __IO uint32_t tmpreg;
1125 SET_BIT(RCC->AHB2LPENR, Periphs);
1126 /* Delay after an RCC peripheral clock enabling */
1127 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
1128 (void)tmpreg;
1129 }
1130
1131 /**
1132 * @brief Check if AHB2 peripheral clocks in Sleep mode is enabled or not
1133 * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1134 * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1135 * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1136 * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1137 * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1138 * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1139 * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1140 * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1141 * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1142 * AHB2LPENR ADCLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1143 * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1144 * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1145 * AHB2LPENR AESLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1146 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1147 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1148 * AHB2LPENR PKALPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1149 * AHB2LPENR SAESLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1150 * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1151 * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_IsEnabledClockSleep
1152 * @param Periphs This parameter can be a combination of the following values:
1153 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1154 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1155 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1156 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1157 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1158 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1159 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1160 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1161 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1162 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1163 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1164 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1165 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1166 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1167 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1168 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1169 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1170 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1171 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
1172 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1173 *
1174 * (*) : Not available for all stm32h5xxxx family lines.
1175 * @retval State of Periphs (1 or 0).
1176 */
LL_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)1177 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1178 {
1179 return ((READ_BIT(RCC->AHB2LPENR, Periphs) == Periphs) ? 1UL : 0UL);
1180 }
1181
1182 /**
1183 * @brief Disable AHB2 peripheral clocks in Sleep mode
1184 * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_DisableClockSleep\n
1185 * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_DisableClockSleep\n
1186 * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_DisableClockSleep\n
1187 * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_DisableClockSleep\n
1188 * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_DisableClockSleep\n
1189 * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_DisableClockSleep\n
1190 * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_DisableClockSleep\n
1191 * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_DisableClockSleep\n
1192 * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_DisableClockSleep\n
1193 * AHB2LPENR ADCLPEN LL_AHB2_GRP1_DisableClockSleep\n
1194 * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_DisableClockSleep\n
1195 * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_DisableClockSleep\n
1196 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockSleep\n
1197 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n
1198 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n
1199 * AHB2LPENR PKALPEN LL_AHB2_GRP1_DisableClockSleep\n
1200 * AHB2LPENR SAESLPEN LL_AHB2_GRP1_DisableClockSleep\n
1201 * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n
1202 * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep
1203 * @param Periphs This parameter can be a combination of the following values:
1204 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1205 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1206 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1207 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1208 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1209 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1210 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1211 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1212 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1213 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1214 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1215 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1216 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1217 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1218 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1219 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1220 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1221 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1222 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
1223 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1224 *
1225 * (*) : Not available for all stm32h5xxxx family lines.
1226 * @retval None
1227 */
LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)1228 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
1229 {
1230 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
1231 }
1232
1233 /**
1234 * @}
1235 */
1236
1237 #if defined(AHB4PERIPH_BASE)
1238 /** @defgroup BUS_LL_EF_AHB4 AHB4
1239 * @{
1240 */
1241 /**
1242 * @brief Enable AHB4 peripherals clock.
1243 * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_EnableClock\n
1244 * AHB4ENR SDMMC1EN LL_AHB4_GRP1_EnableClock\n
1245 * AHB4ENR SDMMC2EN LL_AHB4_GRP1_EnableClock\n
1246 * AHB4ENR FMCEN LL_AHB4_GRP1_EnableClock\n
1247 * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_EnableClock
1248 * @param Periphs This parameter can be a combination of the following values:
1249 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1250 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1251 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1252 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*)
1253 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1254 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1255 *
1256 * (*) : Not available for all stm32h5xxxx family lines.
1257 * @retval None
1258 */
LL_AHB4_GRP1_EnableClock(uint32_t Periphs)1259 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
1260 {
1261 __IO uint32_t tmpreg;
1262 SET_BIT(RCC->AHB4ENR, Periphs);
1263 /* Delay after an RCC peripheral clock enabling */
1264 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
1265 (void)tmpreg;
1266 }
1267
1268 /**
1269 * @brief Check if AHB4 peripheral clock is enabled or not
1270 * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_IsEnabledClock\n
1271 * AHB4ENR SDMMC1EN LL_AHB4_GRP1_IsEnabledClock\n
1272 * AHB4ENR SDMMC2EN LL_AHB4_GRP1_IsEnabledClock\n
1273 * AHB4ENR FMCEN LL_AHB4_GRP1_IsEnabledClock\n
1274 * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_IsEnabledClock
1275 * @param Periphs This parameter can be a combination of the following values:
1276 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1277 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1278 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1279 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1280 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1281 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1282 * @retval State of Periphs (1 or 0).
1283 */
LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)1284 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
1285 {
1286 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL);
1287 }
1288
1289 /**
1290 * @brief Disable AHB4 peripherals clock.
1291 * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_DisableClock\n
1292 * AHB4ENR SDMMC1EN LL_AHB4_GRP1_DisableClock\n
1293 * AHB4ENR SDMMC2EN LL_AHB4_GRP1_DisableClock\n
1294 * AHB4ENR FMCEN LL_AHB4_GRP1_DisableClock\n
1295 * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_DisableClock
1296 * @param Periphs This parameter can be a combination of the following values:
1297 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1298 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1299 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1300 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1301 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1302 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1303 * @retval None
1304 */
LL_AHB4_GRP1_DisableClock(uint32_t Periphs)1305 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
1306 {
1307 CLEAR_BIT(RCC->AHB4ENR, Periphs);
1308 }
1309
1310 /**
1311 * @brief Force AHB4 peripherals reset.
1312 * @rmtoll AHB4RSTR OTFDEC1RST LL_AHB4_GRP1_ForceReset\n
1313 * AHB4RSTR SDMMC1RST LL_AHB4_GRP1_ForceReset\n
1314 * AHB4RSTR SDMMC2RST LL_AHB4_GRP1_ForceReset\n
1315 * AHB4RSTR FMCRST LL_AHB4_GRP1_ForceReset\n
1316 * AHB4RSTR OCTOSPI1RST LL_AHB4_GRP1_ForceReset
1317 * @param Periphs This parameter can be a combination of the following values:
1318 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1319 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1320 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1321 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1322 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1323 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1324 * @retval None
1325 */
LL_AHB4_GRP1_ForceReset(uint32_t Periphs)1326 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
1327 {
1328 SET_BIT(RCC->AHB4RSTR, Periphs);
1329 }
1330
1331 /**
1332 * @brief Release AHB4 peripherals reset.
1333 * @rmtoll AHB4RSTR OTFDEC1RST LL_AHB4_GRP1_ReleaseReset\n
1334 * AHB4RSTR SDMMC1RST LL_AHB4_GRP1_ReleaseReset\n
1335 * AHB4RSTR SDMMC2RST LL_AHB4_GRP1_ReleaseReset\n
1336 * AHB4RSTR FMCRST LL_AHB4_GRP1_ReleaseReset\n
1337 * AHB4RSTR OCTOSPI1RST LL_AHB4_GRP1_ReleaseReset
1338 * @param Periphs This parameter can be a combination of the following values:
1339 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1340 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1341 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1342 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1343 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1344 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1345 * @retval None
1346 */
LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)1347 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
1348 {
1349 CLEAR_BIT(RCC->AHB4RSTR, Periphs);
1350 }
1351
1352 /**
1353 * @brief Enable AHB4 peripheral clocks in Sleep mode
1354 * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_EnableClockSleep\n
1355 * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_EnableClockSleep\n
1356 * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_EnableClockSleep\n
1357 * AHB4LPENR FMCLPEN LL_AHB4_GRP1_EnableClockSleep\n
1358 * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_EnableClockSleep
1359 * @param Periphs This parameter can be a combination of the following values:
1360 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1361 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1362 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1363 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1364 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1365 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1366 * @retval None
1367 */
LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)1368 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
1369 {
1370 __IO uint32_t tmpreg;
1371 SET_BIT(RCC->AHB4LPENR, Periphs);
1372 /* Delay after an RCC peripheral clock enabling */
1373 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
1374 (void)tmpreg;
1375 }
1376
1377 /**
1378 * @brief Check if AHB4 peripheral clocks in Sleep mode is enabled or not
1379 * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n
1380 * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n
1381 * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n
1382 * AHB4LPENR FMCLPEN LL_AHB4_GRP1_IsEnabledClockSleep\n
1383 * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_IsEnabledClockSleep
1384 * @param Periphs This parameter can be a combination of the following values:
1385 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1386 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1387 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1388 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1389 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1390 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1391 * @retval State of Periphs (1 or 0).
1392 */
LL_AHB4_GRP1_IsEnabledClockSleep(uint32_t Periphs)1393 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1394 {
1395 return ((READ_BIT(RCC->AHB4LPENR, Periphs) == Periphs) ? 1UL : 0UL);
1396 }
1397
1398 /**
1399 * @brief Disable AHB4 peripheral clocks in Sleep and Stop modes
1400 * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_DisableClockSleep\n
1401 * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_DisableClockSleep\n
1402 * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_DisableClockSleep\n
1403 * AHB4LPENR FMCLPEN LL_AHB4_GRP1_DisableClockSleep\n
1404 * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_DisableClockSleep
1405 * @param Periphs This parameter can be a combination of the following values:
1406 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1407 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1408 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1409 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1410 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1411 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1412 * @retval None
1413 */
LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)1414 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
1415 {
1416 CLEAR_BIT(RCC->AHB4LPENR, Periphs);
1417 }
1418
1419 /**
1420 * @}
1421 */
1422 #endif /* AHB4PERIPH_BASE */
1423
1424 /** @defgroup BUS_LL_EF_APB1 APB1
1425 * @{
1426 */
1427
1428 /**
1429 * @brief Enable APB1 peripherals clock.
1430 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n
1431 * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n
1432 * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n
1433 * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n
1434 * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n
1435 * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n
1436 * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n
1437 * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n
1438 * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n
1439 * APB1LENR WWDGEN LL_APB1_GRP1_EnableClock\n
1440 * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n
1441 * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n
1442 * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n
1443 * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n
1444 * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n
1445 * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n
1446 * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n
1447 * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n
1448 * APB1LENR I3C1EN LL_APB1_GRP1_EnableClock\n
1449 * APB1LENR CRSEN LL_APB1_GRP1_EnableClock\n
1450 * APB1LENR USART6EN LL_APB1_GRP1_EnableClock\n
1451 * APB1LENR USART10EN LL_APB1_GRP1_EnableClock\n
1452 * APB1LENR USART11EN LL_APB1_GRP1_EnableClock\n
1453 * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n
1454 * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n
1455 * APB1LENR UART8EN LL_APB1_GRP1_EnableClock
1456 * @param Periphs This parameter can be a combination of the following values:
1457 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1458 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1459 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1460 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1461 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1462 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1463 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1464 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1465 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1466 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1467 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1468 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1469 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1470 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1471 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1472 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1473 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1474 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1475 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1476 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1477 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1478 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1479 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1480 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1481 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1482 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1483 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1484 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1485 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1486 *
1487 * (*) : Not available for all stm32h5xxxx family lines.
1488 * @retval None
1489 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1490 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1491 {
1492 __IO uint32_t tmpreg;
1493 SET_BIT(RCC->APB1LENR, Periphs);
1494 /* Delay after an RCC peripheral clock enabling */
1495 tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
1496 (void)tmpreg;
1497 }
1498
1499 /**
1500 * @brief Enable APB1 peripherals clock.
1501 * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_EnableClock\n
1502 * APB1HENR UART12EN LL_APB1_GRP2_EnableClock\n
1503 * APB1HENR DTSEN LL_APB1_GRP2_EnableClock\n
1504 * APB1HENR LPTIM2EN LL_APB1_GRP2_EnableClock\n
1505 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock\n
1506 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock\n
1507 * APB1HENR UCPD1EN LL_APB1_GRP2_EnableClock
1508 * @param Periphs This parameter can be a combination of the following values:
1509 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1510 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1511 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1512 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1513 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1514 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1515 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1516 *
1517 * (*) : Not available for all stm32h5xxxx family lines.
1518 * @retval None
1519 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)1520 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
1521 {
1522 __IO uint32_t tmpreg;
1523 SET_BIT(RCC->APB1HENR, Periphs);
1524 /* Delay after an RCC peripheral clock enabling */
1525 tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
1526 (void)tmpreg;
1527 }
1528
1529 /**
1530 * @brief Check if APB1 peripheral clock is enabled or not
1531 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1532 * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1533 * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1534 * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1535 * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1536 * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1537 * APB1LENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1538 * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1539 * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1540 * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1541 * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1542 * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1543 * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1544 * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1545 * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1546 * APB1LENR I3C1EN LL_APB1_GRP1_IsEnabledClock\n
1547 * APB1LENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
1548 * APB1LENR USART6EN LL_APB1_GRP1_IsEnabledClock\n
1549 * APB1LENR USART10EN LL_APB1_GRP1_IsEnabledClock\n
1550 * APB1LENR USART11EN LL_APB1_GRP1_IsEnabledClock\n
1551 * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1552 * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1553 * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock
1554 * @param Periphs This parameter can be a combination of the following values:
1555 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1556 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1557 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1558 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1559 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1560 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1561 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1562 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1563 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1564 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1565 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1566 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1567 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1568 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1569 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1570 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1571 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1572 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1573 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1574 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1575 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1576 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1577 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1578 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1579 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1580 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1581 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1582 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1583 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1584 *
1585 * (*) : Not available for all stm32h5xxxx family lines.
1586 * @retval State of Periphs (1 or 0).
1587 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1588 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1589 {
1590 return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1UL : 0UL);
1591 }
1592
1593 /**
1594 * @brief Check if APB1 peripheral clock is enabled or not
1595 * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_IsEnabledClock\n
1596 * APB1HENR UART12EN LL_APB1_GRP2_IsEnabledClock\n
1597 * APB1HENR DTSEN LL_APB1_GRP2_IsEnabledClock\n
1598 * APB1HENR LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n
1599 * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock\n
1600 * APB1HENR UCPD1EN LL_APB1_GRP2_IsEnabledClock
1601 * @param Periphs This parameter can be a combination of the following values:
1602 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1603 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1604 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1605 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1606 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1607 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1608 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1609 *
1610 * (*) : Not available for all stm32h5xxxx family lines.
1611 * @retval State of Periphs (1 or 0).
1612 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1613 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1614 {
1615 return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1UL : 0UL);
1616 }
1617
1618 /**
1619 * @brief Disable APB1 peripherals clock.
1620 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n
1621 * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n
1622 * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n
1623 * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n
1624 * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n
1625 * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n
1626 * APB1LENR WWDGEN LL_APB1_GRP1_DisableClock\n
1627 * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n
1628 * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n
1629 * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n
1630 * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n
1631 * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n
1632 * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n
1633 * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n
1634 * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n
1635 * APB1LENR I3C1EN LL_APB1_GRP1_DisableClock\n
1636 * APB1LENR CRSEN LL_APB1_GRP1_DisableClock\n
1637 * APB1LENR USART6EN LL_APB1_GRP1_DisableClock\n
1638 * APB1LENR USART10EN LL_APB1_GRP1_DisableClock\n
1639 * APB1LENR USART11EN LL_APB1_GRP1_DisableClock\n
1640 * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n
1641 * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n
1642 * APB1LENR UART8EN LL_APB1_GRP1_DisableClock
1643 * @param Periphs This parameter can be a combination of the following values:
1644 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1645 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1646 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1647 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1648 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1649 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1650 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1651 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1652 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1653 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1654 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1655 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1656 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1657 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1658 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1659 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1660 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1661 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1662 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1663 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1664 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1665 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1666 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1667 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1668 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1669 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1670 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1671 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1672 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1673 *
1674 * (*) : Not available for all stm32h5xxxx family lines.
1675 * @retval None
1676 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1677 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1678 {
1679 CLEAR_BIT(RCC->APB1LENR, Periphs);
1680 }
1681
1682 /**
1683 * @brief Disable APB1 peripherals clock.
1684 * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_DisableClock\n
1685 * APB1HENR UART12EN LL_APB1_GRP2_DisableClock\n
1686 * APB1HENR DTSEN LL_APB1_GRP2_DisableClock\n
1687 * APB1HENR LPTIM2EN LL_APB1_GRP2_DisableClock\n
1688 * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock\n
1689 * APB1HENR UCPD1EN LL_APB1_GRP2_DisableClock
1690 * @param Periphs This parameter can be a combination of the following values:
1691 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1692 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1693 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1694 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1695 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1696 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1697 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1698 *
1699 * (*) : Not available for all stm32h5xxxx family lines.
1700 * @retval None
1701 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1702 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1703 {
1704 CLEAR_BIT(RCC->APB1HENR, Periphs);
1705 }
1706
1707 /**
1708 * @brief Force APB1 peripherals reset.
1709 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1710 * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1711 * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1712 * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1713 * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1714 * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1715 * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1716 * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1717 * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n
1718 * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n
1719 * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n
1720 * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n
1721 * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1722 * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1723 * APB1LRSTR I3C1RST LL_APB1_GRP1_ForceReset\n
1724 * APB1LRSTR CRSRST LL_APB1_GRP1_ForceReset\n
1725 * APB1LRSTR USART6RST LL_APB1_GRP1_ForceReset\n
1726 * APB1LRSTR USART10RST LL_APB1_GRP1_ForceReset\n
1727 * APB1LRSTR USART11RST LL_APB1_GRP1_ForceReset\n
1728 * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n
1729 * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n
1730 * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset
1731 * @param Periphs This parameter can be a combination of the following values:
1732 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1733 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1734 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1735 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1736 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1737 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1738 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1739 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1740 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1741 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1742 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1743 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1744 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1745 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1746 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1747 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1748 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1749 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1750 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1751 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1752 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1753 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1754 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1755 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1756 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1757 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1758 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1759 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1760 *
1761 * (*) : Not available for all stm32h5xxxx family lines.
1762 * @retval None
1763 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1764 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1765 {
1766 SET_BIT(RCC->APB1LRSTR, Periphs);
1767 }
1768
1769 /**
1770 * @brief Force APB1 peripherals reset.
1771 * @rmtoll APB1HRSTR UART9RST LL_APB1_GRP2_ForceReset\n
1772 * APB1HRSTR UART12RST LL_APB1_GRP2_ForceReset\n
1773 * APB1HRSTR DTSRST LL_APB1_GRP2_ForceReset\n
1774 * APB1HRSTR LPTIM2RST LL_APB1_GRP2_ForceReset\n
1775 * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset\n
1776 * APB1HRSTR UCPD1RST LL_APB1_GRP2_ForceReset
1777 * @param Periphs This parameter can be a combination of the following values:
1778 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1779 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1780 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1781 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1782 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1783 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1784 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1785 *
1786 * (*) : Not available for all stm32h5xxxx family lines.
1787 * @retval None
1788 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1789 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1790 {
1791 SET_BIT(RCC->APB1HRSTR, Periphs);
1792 }
1793
1794 /**
1795 * @brief Release APB1 peripherals reset.
1796 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1797 * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1798 * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1799 * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1800 * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1801 * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1802 * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1803 * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1804 * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1805 * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1806 * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1807 * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1808 * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1809 * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1810 * APB1LRSTR I3C1RST LL_APB1_GRP1_ReleaseReset\n
1811 * APB1LRSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
1812 * APB1LRSTR USART6RST LL_APB1_GRP1_ReleaseReset\n
1813 * APB1LRSTR USART10RST LL_APB1_GRP1_ReleaseReset\n
1814 * APB1LRSTR USART11RST LL_APB1_GRP1_ReleaseReset\n
1815 * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1816 * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1817 * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset
1818 * @param Periphs This parameter can be a combination of the following values:
1819 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1820 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1821 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1822 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1823 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1824 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1825 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1826 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1827 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1828 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1829 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1830 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1831 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1832 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1833 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1834 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1835 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1836 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1837 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1838 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1839 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1840 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1841 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1842 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1843 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1844 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1845 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1846 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1847 *
1848 * (*) : Not available for all stm32h5xxxx family lines.
1849 * @retval None
1850 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1851 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1852 {
1853 CLEAR_BIT(RCC->APB1LRSTR, Periphs);
1854 }
1855
1856 /**
1857 * @brief Release APB1 peripherals reset.
1858 * @rmtoll APB1HRSTR UART9RST LL_APB1_GRP2_ReleaseReset\n
1859 * APB1HRSTR UART12RST LL_APB1_GRP2_ReleaseReset\n
1860 * APB1HRSTR DTSRST LL_APB1_GRP2_ReleaseReset\n
1861 * APB1HRSTR LPTIM2RST LL_APB1_GRP2_ReleaseReset\n
1862 * APB1HRSTR FDCAN LL_APB1_GRP2_ReleaseReset\n
1863 * APB1HRSTR UCPD1RST LL_APB1_GRP2_ReleaseReset
1864 * @param Periphs This parameter can be a combination of the following values:
1865 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1866 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1867 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1868 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1869 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1870 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1871 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1872 *
1873 * (*) : Not available for all stm32h5xxxx family lines.
1874 * @retval None
1875 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1876 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1877 {
1878 CLEAR_BIT(RCC->APB1HRSTR, Periphs);
1879 }
1880
1881 /**
1882 * @brief Enable APB1 peripheral clocks in Sleep mode
1883 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
1884 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
1885 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
1886 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
1887 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
1888 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
1889 * APB1LLPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
1890 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
1891 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
1892 * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
1893 * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
1894 * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
1895 * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
1896 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
1897 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
1898 * APB1LLPENR I3C1LPEN LL_APB1_GRP1_EnableClockSleep\n
1899 * APB1LLPENR CRSLPEN LL_APB1_GRP1_EnableClockSleep\n
1900 * APB1LLPENR USART6LPEN LL_APB1_GRP1_EnableClockSleep\n
1901 * APB1LLPENR USART10LPEN LL_APB1_GRP1_EnableClockSleep\n
1902 * APB1LLPENR USART11LPEN LL_APB1_GRP1_EnableClockSleep\n
1903 * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n
1904 * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n
1905 * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep
1906 * @param Periphs This parameter can be a combination of the following values:
1907 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1908 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1909 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1910 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1911 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1912 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1913 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1914 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1915 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1916 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1917 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1918 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1919 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1920 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1921 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1922 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1923 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1924 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1925 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1926 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1927 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1928 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1929 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1930 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1931 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1932 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1933 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1934 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1935 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1936 *
1937 * (*) : Not available for all stm32h5xxxx family lines.
1938 * @retval None
1939 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)1940 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
1941 {
1942 __IO uint32_t tmpreg;
1943 SET_BIT(RCC->APB1LLPENR, Periphs);
1944 /* Delay after an RCC peripheral clock enabling */
1945 tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
1946 (void)tmpreg;
1947 }
1948
1949 /**
1950 * @brief Check if APB1 peripheral clocks in Sleep mode is enabled or not
1951 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1952 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1953 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1954 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1955 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1956 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1957 * APB1LLPENR WWDGLPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1958 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1959 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1960 * APB1LLPENR USART2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1961 * APB1LLPENR USART3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1962 * APB1LLPENR UART4LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1963 * APB1LLPENR UART5LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1964 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1965 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1966 * APB1LLPENR I3C1LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1967 * APB1LLPENR CRSLPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1968 * APB1LLPENR USART6LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1969 * APB1LLPENR USART10LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1970 * APB1LLPENR USART11LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1971 * APB1LLPENR CECLPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1972 * APB1LLPENR UART7LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1973 * APB1LLPENR UART8LPEN LL_APB1_GRP1_IsEnabledClockSleep
1974 * @param Periphs This parameter can be a combination of the following values:
1975 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1976 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1977 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1978 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1979 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1980 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1981 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1982 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1983 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1984 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1985 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1986 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1987 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1988 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1989 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1990 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1991 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1992 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1993 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1994 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1995 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1996 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1997 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1998 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1999 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
2000 * @arg @ref LL_APB1_GRP1_PERIPH_USART11
2001 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
2002 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
2003 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
2004 *
2005 * (*) : Not available for all stm32h5xxxx family lines.
2006 * @retval State of Periphs (1 or 0).
2007 */
LL_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)2008 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2009 {
2010 return ((READ_BIT(RCC->APB1LLPENR, Periphs) == Periphs) ? 1UL : 0UL);
2011 }
2012
2013 /**
2014 * @brief Disable APB1 peripheral clocks in Sleep mode
2015 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2016 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2017 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2018 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2019 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2020 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2021 * APB1LLPENR WWDGLPEN LL_APB1_GRP1_DisableClockStopSleep\n
2022 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2023 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2024 * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2025 * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2026 * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2027 * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2028 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2029 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2030 * APB1LLPENR I3C1LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2031 * APB1LLPENR CRSLPEN LL_APB1_GRP1_DisableClockStopSleep\n
2032 * APB1LLPENR USART6LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2033 * APB1LLPENR USART10LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2034 * APB1LLPENR USART11LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2035 * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockStopSleep\n
2036 * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockStopSleep\n
2037 * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockStopSleep
2038 * @param Periphs This parameter can be a combination of the following values:
2039 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
2040 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2041 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2042 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
2043 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
2044 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2045 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2046 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
2047 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
2048 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
2049 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2050 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2051 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2052 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
2053 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
2054 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2055 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2056 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
2057 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
2058 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2059 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2060 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2061 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2062 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2063 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
2064 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
2065 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
2066 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
2067 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
2068 *
2069 * (*) : Not available for all stm32h5xxxx family lines.
2070 * @retval None
2071 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)2072 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
2073 {
2074 CLEAR_BIT(RCC->APB1LLPENR, Periphs);
2075 }
2076
2077 /**
2078 * @brief Enable APB1 peripheral clocks in Sleep mode
2079 * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_EnableClockSleep\n
2080 * APB1HLPENR UART12LPEN LL_APB1_GRP2_EnableClockSleep\n
2081 * APB1HLPENR DTSLPEN LL_APB1_GRP2_EnableClockSleep\n
2082 * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_EnableClockSleep\n
2083 * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_EnableClockSleep\n
2084 * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_EnableClockSleep\n
2085 * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_EnableClockSleep
2086 * @param Periphs This parameter can be a combination of the following values:
2087 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2088 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
2089 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
2090 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
2091 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2092 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN12 (*)
2093 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 (*)
2094 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2095 *
2096 * (*) : Not available for all stm32h5xxxx family lines.
2097 * @retval None
2098 */
LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)2099 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
2100 {
2101 __IO uint32_t tmpreg;
2102 SET_BIT(RCC->APB1HLPENR, Periphs);
2103 /* Delay after an RCC peripheral clock enabling */
2104 tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
2105 (void)tmpreg;
2106 }
2107
2108 /**
2109 * @brief Check if APB1 peripheral clocks in Sleep mode is enabled or not
2110 * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2111 * APB1HLPENR UART12LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2112 * APB1HLPENR DTSLPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2113 * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2114 * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2115 * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2116 * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_IsEnabledClockSleep
2117 * @param Periphs This parameter can be a combination of the following values:
2118 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2119 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
2120 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
2121 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
2122 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2123 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN12 (*)
2124 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 (*)
2125 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2126 *
2127 * (*) : Not available for all stm32h5xxxx family lines.
2128 * @retval State of Periphs (1 or 0).
2129 */
LL_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs)2130 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs)
2131 {
2132 return ((READ_BIT(RCC->APB1HLPENR, Periphs) == Periphs) ? 1UL : 0UL);
2133 }
2134
2135 /**
2136 * @brief Disable APB1 peripheral clocks in Sleep mode
2137 * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_DisableClockSleep\n
2138 * APB1HLPENR UART12LPEN LL_APB1_GRP2_DisableClockSleep\n
2139 * APB1HLPENR DTSLPEN LL_APB1_GRP2_DisableClockSleep\n
2140 * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_DisableClockSleep\n
2141 * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_DisableClockSleep\n
2142 * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_DisableClockSleep\n
2143 * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_DisableClockSleep
2144 * @param Periphs This parameter can be a combination of the following values:
2145 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2146 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
2147 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
2148 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
2149 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2150 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN12 (*)
2151 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 (*)
2152 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2153 *
2154 * (*) : Not available for all stm32h5xxxx family lines.
2155 * @retval None
2156 */
LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)2157 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
2158 {
2159 CLEAR_BIT(RCC->APB1HLPENR, Periphs);
2160 }
2161
2162 /**
2163 * @}
2164 */
2165
2166 /** @defgroup BUS_LL_EF_APB2 APB2
2167 * @{
2168 */
2169
2170 /**
2171 * @brief Enable APB2 peripherals clock.
2172 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
2173 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
2174 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
2175 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
2176 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
2177 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
2178 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
2179 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
2180 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
2181 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
2182 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
2183 * APB2ENR USBEN LL_APB2_GRP1_EnableClock
2184 * @param Periphs This parameter can be a combination of the following values:
2185 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2186 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2187 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2188 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2189 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2190 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2191 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2192 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2193 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2194 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2195 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2196 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2197 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2198 *
2199 * (*) : Not available for all stm32h5xxxx family lines.
2200 * @retval None
2201 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)2202 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
2203 {
2204 __IO uint32_t tmpreg;
2205 SET_BIT(RCC->APB2ENR, Periphs);
2206 /* Delay after an RCC peripheral clock enabling */
2207 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
2208 (void)tmpreg;
2209 }
2210
2211 /**
2212 * @brief Check if APB2 peripheral clock is enabled or not
2213 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
2214 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
2215 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
2216 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
2217 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
2218 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
2219 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
2220 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
2221 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
2222 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
2223 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
2224 * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock
2225 * @param Periphs This parameter can be a combination of the following values:
2226 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2227 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2228 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2229 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2230 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2231 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2232 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2233 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2234 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2235 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2236 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2237 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2238 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2239 *
2240 * (*) : Not available for all stm32h5xxxx family lines.
2241 * @retval State of Periphs (1 or 0).
2242 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2243 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2244 {
2245 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
2246 }
2247
2248 /**
2249 * @brief Disable APB2 peripherals clock.
2250 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
2251 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
2252 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
2253 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
2254 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
2255 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
2256 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
2257 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
2258 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
2259 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
2260 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
2261 * APB2ENR USBEN LL_APB2_GRP1_DisableClock
2262 * @param Periphs This parameter can be a combination of the following values:
2263 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2264 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2265 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2266 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2267 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2268 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2269 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2270 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2271 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2272 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2273 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2274 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2275 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2276 *
2277 * (*) : Not available for all stm32h5xxxx family lines.
2278 * @retval None
2279 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)2280 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2281 {
2282 CLEAR_BIT(RCC->APB2ENR, Periphs);
2283 }
2284
2285 /**
2286 * @brief Force APB2 peripherals reset.
2287 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
2288 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
2289 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
2290 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
2291 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
2292 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
2293 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
2294 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
2295 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
2296 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
2297 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
2298 * APB2RSTR USBRST LL_APB2_GRP1_ForceReset
2299 * @param Periphs This parameter can be a combination of the following values:
2300 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2301 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2302 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2303 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2304 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2305 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2306 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2307 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2308 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2309 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2310 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2311 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2312 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2313 *
2314 * (*) : Not available for all stm32h5xxxx family lines.
2315 * @retval None
2316 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)2317 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
2318 {
2319 SET_BIT(RCC->APB2RSTR, Periphs);
2320 }
2321
2322 /**
2323 * @brief Release APB2 peripherals reset.
2324 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
2325 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
2326 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
2327 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
2328 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
2329 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
2330 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
2331 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
2332 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
2333 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
2334 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
2335 * APB2RSTR USBRST LL_APB2_GRP1_ReleaseReset
2336 * @param Periphs This parameter can be a combination of the following values:
2337 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2338 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2339 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2340 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2341 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
2342 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2343 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2344 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2345 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2346 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2347 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2348 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2349 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2350 *
2351 * (*) : Not available for all stm32h5xxxx family lines.
2352 * @retval None
2353 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)2354 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
2355 {
2356 CLEAR_BIT(RCC->APB2RSTR, Periphs);
2357 }
2358
2359 /**
2360 * @brief Enable APB2 peripheral clocks in Sleep mode
2361 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2362 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2363 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n
2364 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n
2365 * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n
2366 * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n
2367 * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n
2368 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n
2369 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockSleep\n
2370 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2371 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n
2372 * APB2LPENR USBLPEN LL_APB2_GRP1_EnableClockSleep
2373 * @param Periphs This parameter can be a combination of the following values:
2374 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2375 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2376 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2377 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2378 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2379 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2380 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2381 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2382 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2383 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2384 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2385 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2386 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2387 *
2388 * (*) : Not available for all stm32h5xxxx family lines.
2389 * @retval None
2390 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)2391 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2392 {
2393 __IO uint32_t tmpreg;
2394 SET_BIT(RCC->APB2LPENR, Periphs);
2395 /* Delay after an RCC peripheral clock enabling */
2396 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2397 (void)tmpreg;
2398 }
2399
2400
2401 /**
2402 * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not
2403 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2404 * APB2LPENR SPI1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2405 * APB2LPENR TIM8LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2406 * APB2LPENR USART1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2407 * APB2LPENR TIM15LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2408 * APB2LPENR TIM16LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2409 * APB2LPENR TIM17LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2410 * APB2LPENR SPI4LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2411 * APB2LPENR SPI6LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2412 * APB2LPENR SAI1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2413 * APB2LPENR SAI2LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2414 * APB2LPENR USBLPEN LL_APB2_GRP1_IsEnabledClockSleep
2415 * @param Periphs This parameter can be a combination of the following values:
2416 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2417 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2418 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2419 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2420 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2421 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2422 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2423 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2424 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2425 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2426 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2427 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2428 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2429 *
2430 * (*) : Not available for all stm32h5xxxx family lines.
2431 * @retval State of Periphs (1 or 0).
2432 */
LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)2433 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2434 {
2435 return ((READ_BIT(RCC->APB2LPENR, Periphs) == Periphs) ? 1UL : 0UL);
2436 }
2437
2438 /**
2439 * @brief Disable APB2 peripheral clocks in Sleep mode
2440 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2441 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2442 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n
2443 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n
2444 * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n
2445 * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n
2446 * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n
2447 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n
2448 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockSleep\n
2449 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2450 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n
2451 * APB2LPENR USBLPEN LL_APB2_GRP1_DisableClockSleep
2452 * @param Periphs This parameter can be a combination of the following values:
2453 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2454 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2455 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2456 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2457 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2458 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2459 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2460 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2461 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2462 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2463 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2464 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2465 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2466 *
2467 * (*) : Not available for all stm32h5xxxx family lines.
2468 * @retval None
2469 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)2470 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2471 {
2472 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2473 }
2474
2475 /**
2476 * @}
2477 */
2478
2479
2480 /** @defgroup BUS_LL_EF_APB3 APB3
2481 * @{
2482 */
2483
2484 /**
2485 * @brief Enable APB3 peripherals clock.
2486 * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_EnableClock\n
2487 * APB3ENR SPI5EN LL_APB3_GRP1_EnableClock\n
2488 * APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock\n
2489 * APB3ENR I2C3EN LL_APB3_GRP1_EnableClock\n
2490 * APB3ENR I2C4EN LL_APB3_GRP1_EnableClock\n
2491 * APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock\n
2492 * APB3ENR LPTIM3EN LL_APB3_GRP1_EnableClock\n
2493 * APB3ENR LPTIM4EN LL_APB3_GRP1_EnableClock\n
2494 * APB3ENR LPTIM5EN LL_APB3_GRP1_EnableClock\n
2495 * APB3ENR LPTIM6EN LL_APB3_GRP1_EnableClock\n
2496 * APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n
2497 * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock
2498 * @param Periphs This parameter can be a combination of the following values:
2499 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2500 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2501 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2502 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2503 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2504 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2505 * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*)
2506 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2507 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2508 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2509 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2510 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2511 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2512 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2513 *
2514 * (*) : Not available for all stm32h5xxxx family lines.
2515 * @retval None
2516 */
LL_APB3_GRP1_EnableClock(uint32_t Periphs)2517 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
2518 {
2519 __IO uint32_t tmpreg;
2520 SET_BIT(RCC->APB3ENR, Periphs);
2521 /* Delay after an RCC peripheral clock enabling */
2522 tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
2523 (void)tmpreg;
2524 }
2525
2526 /**
2527 * @brief Check if APB3 peripheral clock is enabled or not
2528 * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_IsEnabledClock\n
2529 * APB3ENR SPI5EN LL_APB3_GRP1_IsEnabledClock\n
2530 * APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock\n
2531 * APB3ENR I2C3EN LL_APB3_GRP1_IsEnabledClock\n
2532 * APB3ENR I2C4EN LL_APB3_GRP1_IsEnabledClock\n
2533 * APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock\n
2534 * APB3ENR LPTIM3EN LL_APB3_GRP1_IsEnabledClock\n
2535 * APB3ENR LPTIM4EN LL_APB3_GRP1_IsEnabledClock\n
2536 * APB3ENR LPTIM5EN LL_APB3_GRP1_IsEnabledClock\n
2537 * APB3ENR LPTIM6EN LL_APB3_GRP1_IsEnabledClock\n
2538 * APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n
2539 * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock
2540 * @param Periphs This parameter can be a combination of the following values:
2541 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2542 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2543 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2544 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2545 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2546 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2547 * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*)
2548 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2549 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2550 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2551 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2552 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2553 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2554 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2555 *
2556 * (*) : Not available for all stm32h5xxxx family lines.
2557 * @retval State of Periphs (1 or 0).
2558 */
LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)2559 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
2560 {
2561 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
2562 }
2563
2564 /**
2565 * @brief Disable APB2 peripherals clock.
2566 * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_DisableClock\n
2567 * APB3ENR SPI5EN LL_APB3_GRP1_DisableClock\n
2568 * APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock\n
2569 * APB3ENR I2C3EN LL_APB3_GRP1_DisableClock\n
2570 * APB3ENR I2C4EN LL_APB3_GRP1_DisableClock\n
2571 * APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock\n
2572 * APB3ENR LPTIM3EN LL_APB3_GRP1_DisableClock\n
2573 * APB3ENR LPTIM4EN LL_APB3_GRP1_DisableClock\n
2574 * APB3ENR LPTIM5EN LL_APB3_GRP1_DisableClock\n
2575 * APB3ENR LPTIM6EN LL_APB3_GRP1_DisableClock\n
2576 * APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n
2577 * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock
2578 * @param Periphs This parameter can be a combination of the following values:
2579 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2580 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2581 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2582 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2583 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2584 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2585 * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*)
2586 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2587 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2588 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2589 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2590 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2591 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2592 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2593 *
2594 * (*) : Not available for all stm32h5xxxx family lines.
2595 * @retval None
2596 */
LL_APB3_GRP1_DisableClock(uint32_t Periphs)2597 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
2598 {
2599 CLEAR_BIT(RCC->APB3ENR, Periphs);
2600 }
2601
2602 /**
2603 * @brief Force APB3 peripherals reset.
2604 * @rmtoll APB3RSTR SPI5RST LL_APB3_GRP1_ForceReset\n
2605 * APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset\n
2606 * APB3RSTR I2C3RST LL_APB3_GRP1_ForceReset\n
2607 * APB3RSTR I2C4RST LL_APB3_GRP1_ForceReset\n
2608 * APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset\n
2609 * APB3RSTR LPTIM3RST LL_APB3_GRP1_ForceReset\n
2610 * APB3RSTR LPTIM4RST LL_APB3_GRP1_ForceReset\n
2611 * APB3RSTR LPTIM5RST LL_APB3_GRP1_ForceReset\n
2612 * APB3RSTR LPTIM6RST LL_APB3_GRP1_ForceReset\n
2613 * APB3RSTR VREFRST LL_APB3_GRP1_ForceReset
2614 * @param Periphs This parameter can be a combination of the following values:
2615 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2616 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2617 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2618 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2619 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2620 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2621 * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*)
2622 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2623 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2624 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2625 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2626 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2627 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2628 *
2629 * (*) : Not available for all stm32h5xxxx family lines.
2630 * @retval None
2631 */
LL_APB3_GRP1_ForceReset(uint32_t Periphs)2632 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
2633 {
2634 SET_BIT(RCC->APB3RSTR, Periphs);
2635 }
2636
2637 /**
2638 * @brief Release APB3 peripherals reset.
2639 * @rmtoll APB3RSTR SPI5RST LL_APB3_GRP1_ReleaseReset\n
2640 * APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset\n
2641 * APB3RSTR I2C3RST LL_APB3_GRP1_ReleaseReset\n
2642 * APB3RSTR I2C4RST LL_APB3_GRP1_ReleaseReset\n
2643 * APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset\n
2644 * APB3RSTR LPTIM3RST LL_APB3_GRP1_ReleaseReset\n
2645 * APB3RSTR LPTIM4RST LL_APB3_GRP1_ReleaseReset\n
2646 * APB3RSTR LPTIM5RST LL_APB3_GRP1_ReleaseReset\n
2647 * APB3RSTR LPTIM6RST LL_APB3_GRP1_ReleaseReset\n
2648 * APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset
2649 * @param Periphs This parameter can be a combination of the following values:
2650 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2651 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2652 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2653 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2654 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2655 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2656 * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*)
2657 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2658 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2659 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2660 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2661 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2662 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2663 *
2664 * (*) : Not available for all stm32h5xxxx family lines.
2665 * @retval None
2666 */
LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)2667 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
2668 {
2669 CLEAR_BIT(RCC->APB3RSTR, Periphs);
2670 }
2671
2672 /**
2673 * @brief Enable APB3 peripheral clocks in Sleep mode
2674 * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_EnableClockSleep\n
2675 * APB3LPENR SPI5LPEN LL_APB3_GRP1_EnableClockSleep\n
2676 * APB3LPENR LPUART1LPEN LL_APB3_GRP1_EnableClockSleep\n
2677 * APB3LPENR I2C3LPEN LL_APB3_GRP1_EnableClockSleep\n
2678 * APB3LPENR I2C4LPEN LL_APB3_GRP1_EnableClockSleep\n
2679 * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_EnableClockSleep\n
2680 * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_EnableClockSleep\n
2681 * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_EnableClockSleep\n
2682 * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_EnableClockSleep\n
2683 * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_EnableClockSleep\n
2684 * APB3LPENR VREFLPEN LL_APB3_GRP1_EnableClockSleep\n
2685 * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_EnableClockSleep
2686 * @param Periphs This parameter can be a combination of the following values:
2687 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2688 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2689 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2690 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2691 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2692 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2693 * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*)
2694 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2695 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2696 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2697 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2698 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2699 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2700 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2701 *
2702 * (*) : Not available for all stm32h5xxxx family lines.
2703 * @retval None
2704 */
LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)2705 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
2706 {
2707 __IO uint32_t tmpreg;
2708 SET_BIT(RCC->APB3LPENR, Periphs);
2709 /* Delay after an RCC peripheral clock enabling */
2710 tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
2711 (void)tmpreg;
2712 }
2713
2714
2715 /**
2716 * @brief Check if APB3 peripheral clocks in Sleep mode is enabled or not
2717 * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2718 * APB3LPENR SPI5LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2719 * APB3LPENR LPUART1LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2720 * APB3LPENR I2C3LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2721 * APB3LPENR I2C4LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2722 * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2723 * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2724 * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2725 * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2726 * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2727 * APB3LPENR VREFLPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2728 * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_IsEnabledClockSleep
2729 * @param Periphs This parameter can be a combination of the following values:
2730 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2731 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2732 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2733 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2734 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2735 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2736 * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*)
2737 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2738 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2739 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2740 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2741 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2742 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2743 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2744 *
2745 * (*) : Not available for all stm32h5xxxx family lines.
2746 * @retval State of Periphs (1 or 0).
2747 */
LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)2748 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2749 {
2750 return ((READ_BIT(RCC->APB3LPENR, Periphs) == Periphs) ? 1UL : 0UL);
2751 }
2752
2753 /**
2754 * @brief Disable APB3 peripheral clocks in Sleep mode
2755 * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_DisableClockSleep\n
2756 * APB3LPENR SPI5LPEN LL_APB3_GRP1_DisableClockSleep\n
2757 * APB3LPENR LPUART1LPEN LL_APB3_GRP1_DisableClockSleep\n
2758 * APB3LPENR I2C3LPEN LL_APB3_GRP1_DisableClockSleep\n
2759 * APB3LPENR I2C4LPEN LL_APB3_GRP1_DisableClockSleep\n
2760 * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_DisableClockSleep\n
2761 * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_DisableClockSleep\n
2762 * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_DisableClockSleep\n
2763 * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_DisableClockSleep\n
2764 * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_DisableClockSleep\n
2765 * APB3LPENR VREFLPEN LL_APB3_GRP1_DisableClockSleep\n
2766 * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_DisableClockSleep
2767 * @param Periphs This parameter can be a combination of the following values:
2768 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2769 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2770 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2771 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2772 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2773 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2774 * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*)
2775 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2776 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2777 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2778 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2779 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2780 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2781 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2782 *
2783 * (*) : Not available for all stm32h5xxxx family lines.
2784 * @retval None
2785 */
LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)2786 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
2787 {
2788 CLEAR_BIT(RCC->APB3LPENR, Periphs);
2789 }
2790
2791 /**
2792 * @}
2793 */
2794
2795 /**
2796 * @}
2797 */
2798 #endif /* defined(RCC) */
2799
2800 /**
2801 * @}
2802 */
2803
2804 #ifdef __cplusplus
2805 }
2806 #endif
2807
2808 #endif /* __STM32H5xx_LL_BUS_H */
2809
