1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32F7xx_LL_BUS_H
37 #define __STM32F7xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32f7xx.h"
45
46 /** @addtogroup STM32F7xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /* Private macros ------------------------------------------------------------*/
60 /* Exported types ------------------------------------------------------------*/
61 /* Exported constants --------------------------------------------------------*/
62 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
63 * @{
64 */
65
66 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
67 * @{
68 */
69 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
70 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
71 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
72 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
73 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
74 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
75 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
76 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
77 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
78 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
79 #if defined(GPIOJ)
80 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
81 #endif /* GPIOJ */
82 #if defined(GPIOK)
83 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
84 #endif /* GPIOK */
85 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
86 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
87 #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN
88 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
89 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
90 #if defined(DMA2D)
91 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
92 #endif /* DMA2D */
93 #if defined(ETH)
94 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
95 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
96 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
97 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
98 #endif /* ETH */
99 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
100 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
101 #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN
102 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
103 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
104 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
105 /**
106 * @}
107 */
108
109 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
110 * @{
111 */
112 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
113 #if defined(DCMI)
114 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
115 #endif /* DCMI */
116 #if defined(JPEG)
117 #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN
118 #endif /* JPEG */
119 #if defined(CRYP)
120 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
121 #endif /* CRYP */
122 #if defined(AES)
123 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
124 #endif /* AES */
125 #if defined(HASH)
126 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
127 #endif /* HASH */
128 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
129 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
130 /**
131 * @}
132 */
133
134 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
135 * @{
136 */
137 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
138 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
139 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
140 /**
141 * @}
142 */
143
144 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
145 * @{
146 */
147 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
148 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
149 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
150 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
151 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
152 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
153 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
154 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
155 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
156 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
157 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
158 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
159 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
160 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
161 #if defined(SPDIFRX)
162 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
163 #endif /* SPDIFRX */
164 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
165 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
166 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
167 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
168 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
169 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
170 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
171 #if defined(I2C4)
172 #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN
173 #endif /* I2C4 */
174 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
175 #if defined(CAN2)
176 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
177 #endif /* CAN2 */
178 #if defined(CAN3)
179 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
180 #endif /* CAN3 */
181 #if defined(CEC)
182 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
183 #endif /* CEC */
184 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
185 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
186 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
187 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
188 #if defined(RCC_APB1ENR_RTCEN)
189 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN
190 #endif /* RCC_APB1ENR_RTCEN */
191 /**
192 * @}
193 */
194
195 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
196 * @{
197 */
198 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
199 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
200 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
201 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
202 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
203 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
204 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
205 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
206 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
207 #if defined(SDMMC2)
208 #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN
209 #endif /* SDMMC2 */
210 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
211 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
212 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
213 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
214 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
215 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
216 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
217 #if defined(SPI6)
218 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
219 #endif /* SPI6 */
220 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
221 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
222 #if defined(LTDC)
223 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
224 #endif /* LTDC */
225 #if defined(DSI)
226 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
227 #endif /* DSI */
228 #if defined(DFSDM1_Channel0)
229 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
230 #endif /* DFSDM1_Channel0 */
231 #if defined(MDIOS)
232 #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN
233 #endif /* MDIOS */
234 #if defined(USB_HS_PHYC)
235 #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN
236 #endif /* USB_HS_PHYC */
237 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
238 /**
239 * @}
240 */
241
242 /**
243 * @}
244 */
245
246 /* Exported macro ------------------------------------------------------------*/
247 /* Exported functions --------------------------------------------------------*/
248 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
249 * @{
250 */
251
252 /** @defgroup BUS_LL_EF_AHB1 AHB1
253 * @{
254 */
255
256 /**
257 * @brief Enable AHB1 peripherals clock.
258 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
259 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
260 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
261 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
262 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
263 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
264 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
265 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
266 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
267 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
268 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
269 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
270 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
271 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n
272 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
273 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
274 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
275 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
276 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
277 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
278 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
279 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
280 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
281 * @param Periphs This parameter can be a combination of the following values:
282 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
283 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
284 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
285 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
286 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
287 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
288 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
289 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
290 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
291 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
292 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
293 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
294 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
295 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
296 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
297 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
298 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
299 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
300 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
301 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
302 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
303 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
304 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
305 *
306 * (*) value not defined in all devices.
307 * @retval None
308 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)309 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
310 {
311 __IO uint32_t tmpreg;
312 SET_BIT(RCC->AHB1ENR, Periphs);
313 /* Delay after an RCC peripheral clock enabling */
314 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
315 (void)tmpreg;
316 }
317
318 /**
319 * @brief Check if AHB1 peripheral clock is enabled or not
320 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
321 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
322 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
323 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
324 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
325 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
326 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
327 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
328 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
329 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
330 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
331 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
332 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
333 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n
334 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
335 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
336 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
337 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
338 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
339 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
340 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
341 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
342 * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock
343 * @param Periphs This parameter can be a combination of the following values:
344 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
345 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
346 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
347 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
348 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
349 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
350 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
351 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
352 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
353 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
354 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
355 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
356 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
357 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
358 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
359 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
360 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
361 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
362 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
363 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
364 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
365 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
366 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
367 *
368 * (*) value not defined in all devices.
369 * @retval State of Periphs (1 or 0).
370 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)371 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
372 {
373 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
374 }
375
376 /**
377 * @brief Disable AHB1 peripherals clock.
378 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
379 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
380 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
381 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
382 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
383 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
384 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
385 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
386 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
387 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
388 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
389 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
390 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
391 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n
392 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
393 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
394 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
395 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
396 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
397 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
398 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
399 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
400 * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock
401 * @param Periphs This parameter can be a combination of the following values:
402 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
403 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
404 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
405 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
406 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
407 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
410 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
411 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
412 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
413 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
414 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
415 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
416 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
417 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
418 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
419 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
420 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
421 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
422 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
423 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
424 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
425 *
426 * (*) value not defined in all devices.
427 * @retval None
428 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)429 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
430 {
431 CLEAR_BIT(RCC->AHB1ENR, Periphs);
432 }
433
434 /**
435 * @brief Force AHB1 peripherals reset.
436 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
437 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
438 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
439 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
440 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
441 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
442 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
443 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
444 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
445 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
446 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
447 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
448 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
449 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
450 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
451 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
452 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
453 * @param Periphs This parameter can be a combination of the following values:
454 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
455 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
456 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
457 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
458 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
459 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
460 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
461 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
462 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
463 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
464 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
465 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
466 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
467 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
468 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
469 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
470 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
471 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
472 *
473 * (*) value not defined in all devices.
474 * @retval None
475 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)476 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
477 {
478 SET_BIT(RCC->AHB1RSTR, Periphs);
479 }
480
481 /**
482 * @brief Release AHB1 peripherals reset.
483 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
484 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
485 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
486 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
487 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
488 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
489 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
490 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
491 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
492 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
493 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
494 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
495 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
496 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
497 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
498 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
499 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
500 * @param Periphs This parameter can be a combination of the following values:
501 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
502 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
503 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
504 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
505 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
506 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
507 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
508 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
509 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
510 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
511 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
512 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
513 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
514 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
515 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
516 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
517 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
518 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
519 *
520 * (*) value not defined in all devices.
521 * @retval None
522 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)523 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
524 {
525 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
526 }
527
528 /**
529 * @brief Enable AHB1 peripheral clocks in low-power mode
530 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
531 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
532 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
533 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
534 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
535 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
536 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
537 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
538 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
539 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
540 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
541 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
542 * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n
543 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
544 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
545 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
546 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
547 * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
548 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
549 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
550 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
551 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
552 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
553 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
554 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
555 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
556 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
557 * @param Periphs This parameter can be a combination of the following values:
558 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
559 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
560 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
561 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
562 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
563 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
564 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
565 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
566 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
567 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
568 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
569 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
570 * @arg @ref LL_AHB1_GRP1_PERIPH_AXI
571 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
572 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
573 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
574 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
575 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
576 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
577 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
578 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
579 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
580 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
581 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
582 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
583 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
584 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
585 *
586 * (*) value not defined in all devices.
587 * @retval None
588 */
LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)589 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
590 {
591 __IO uint32_t tmpreg;
592 SET_BIT(RCC->AHB1LPENR, Periphs);
593 /* Delay after an RCC peripheral clock enabling */
594 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
595 (void)tmpreg;
596 }
597
598 /**
599 * @brief Disable AHB1 peripheral clocks in low-power mode
600 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
601 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
602 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
603 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
604 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
605 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
606 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
607 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
608 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
609 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
610 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
611 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
612 * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n
613 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
614 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
615 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
616 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
617 * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
618 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
619 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
620 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
621 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
622 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
623 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
624 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
625 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
626 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
627 * @param Periphs This parameter can be a combination of the following values:
628 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
629 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
630 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
631 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
632 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
633 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
634 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
635 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
636 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
637 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
638 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
639 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
640 * @arg @ref LL_AHB1_GRP1_PERIPH_AXI
641 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
642 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
643 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
644 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
645 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
646 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
647 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
648 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
649 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
650 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
651 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
652 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
653 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
654 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
655 *
656 * (*) value not defined in all devices.
657 * @retval None
658 */
LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)659 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
660 {
661 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
662 }
663
664 /**
665 * @}
666 */
667
668 /** @defgroup BUS_LL_EF_AHB2 AHB2
669 * @{
670 */
671
672 /**
673 * @brief Enable AHB2 peripherals clock.
674 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
675 * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n
676 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
677 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
678 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
679 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
680 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
681 * @param Periphs This parameter can be a combination of the following values:
682 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
683 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
684 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
685 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
686 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
687 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
688 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
689 *
690 * (*) value not defined in all devices.
691 * @retval None
692 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)693 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
694 {
695 __IO uint32_t tmpreg;
696 SET_BIT(RCC->AHB2ENR, Periphs);
697 /* Delay after an RCC peripheral clock enabling */
698 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
699 (void)tmpreg;
700 }
701
702 /**
703 * @brief Check if AHB2 peripheral clock is enabled or not
704 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
705 * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n
706 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
707 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
708 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
709 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
710 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
711 * @param Periphs This parameter can be a combination of the following values:
712 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
713 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
714 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
715 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
716 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
717 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
718 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
719 *
720 * (*) value not defined in all devices.
721 * @retval State of Periphs (1 or 0).
722 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)723 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
724 {
725 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
726 }
727
728 /**
729 * @brief Disable AHB2 peripherals clock.
730 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
731 * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n
732 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
733 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
734 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
735 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
736 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
737 * @param Periphs This parameter can be a combination of the following values:
738 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
739 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
740 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
741 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
742 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
743 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
744 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
745 *
746 * (*) value not defined in all devices.
747 * @retval None
748 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)749 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
750 {
751 CLEAR_BIT(RCC->AHB2ENR, Periphs);
752 }
753
754 /**
755 * @brief Force AHB2 peripherals reset.
756 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
757 * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n
758 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
759 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
760 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
761 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
762 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
763 * @param Periphs This parameter can be a combination of the following values:
764 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
765 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
766 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
767 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
768 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
769 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
770 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
771 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
772 *
773 * (*) value not defined in all devices.
774 * @retval None
775 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)776 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
777 {
778 SET_BIT(RCC->AHB2RSTR, Periphs);
779 }
780
781 /**
782 * @brief Release AHB2 peripherals reset.
783 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
784 * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n
785 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
786 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
787 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
788 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
789 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
790 * @param Periphs This parameter can be a combination of the following values:
791 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
792 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
793 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
794 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
795 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
796 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
797 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
798 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
799 *
800 * (*) value not defined in all devices.
801 * @retval None
802 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)803 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
804 {
805 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
806 }
807
808 /**
809 * @brief Enable AHB2 peripheral clocks in low-power mode
810 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
811 * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
812 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
813 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
814 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
815 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
816 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
817 * @param Periphs This parameter can be a combination of the following values:
818 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
819 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
820 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
821 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
822 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
823 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
824 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
825 *
826 * (*) value not defined in all devices.
827 * @retval None
828 */
LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)829 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
830 {
831 __IO uint32_t tmpreg;
832 SET_BIT(RCC->AHB2LPENR, Periphs);
833 /* Delay after an RCC peripheral clock enabling */
834 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
835 (void)tmpreg;
836 }
837
838 /**
839 * @brief Disable AHB2 peripheral clocks in low-power mode
840 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
841 * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
842 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
843 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
844 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
845 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
846 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
847 * @param Periphs This parameter can be a combination of the following values:
848 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
849 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
850 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
851 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
852 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
853 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
854 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
855 *
856 * (*) value not defined in all devices.
857 * @retval None
858 */
LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)859 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
860 {
861 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
862 }
863
864 /**
865 * @}
866 */
867
868 /** @defgroup BUS_LL_EF_AHB3 AHB3
869 * @{
870 */
871
872 /**
873 * @brief Enable AHB3 peripherals clock.
874 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
875 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
876 * @param Periphs This parameter can be a combination of the following values:
877 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
878 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
879 *
880 * (*) value not defined in all devices.
881 * @retval None
882 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)883 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
884 {
885 __IO uint32_t tmpreg;
886 SET_BIT(RCC->AHB3ENR, Periphs);
887 /* Delay after an RCC peripheral clock enabling */
888 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
889 (void)tmpreg;
890 }
891
892 /**
893 * @brief Check if AHB3 peripheral clock is enabled or not
894 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
895 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
896 * @param Periphs This parameter can be a combination of the following values:
897 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
898 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
899 *
900 * (*) value not defined in all devices.
901 * @retval State of Periphs (1 or 0).
902 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)903 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
904 {
905 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
906 }
907
908 /**
909 * @brief Disable AHB3 peripherals clock.
910 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
911 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
912 * @param Periphs This parameter can be a combination of the following values:
913 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
914 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
915 *
916 * (*) value not defined in all devices.
917 * @retval None
918 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)919 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
920 {
921 CLEAR_BIT(RCC->AHB3ENR, Periphs);
922 }
923
924 /**
925 * @brief Force AHB3 peripherals reset.
926 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
927 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
928 * @param Periphs This parameter can be a combination of the following values:
929 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
930 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
931 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
932 *
933 * (*) value not defined in all devices.
934 * @retval None
935 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)936 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
937 {
938 SET_BIT(RCC->AHB3RSTR, Periphs);
939 }
940
941 /**
942 * @brief Release AHB3 peripherals reset.
943 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
944 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
945 * @param Periphs This parameter can be a combination of the following values:
946 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
947 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
948 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
949 *
950 * (*) value not defined in all devices.
951 * @retval None
952 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)953 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
954 {
955 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
956 }
957
958 /**
959 * @brief Enable AHB3 peripheral clocks in low-power mode
960 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
961 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
962 * @param Periphs This parameter can be a combination of the following values:
963 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
964 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
965 *
966 * (*) value not defined in all devices.
967 * @retval None
968 */
LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)969 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
970 {
971 __IO uint32_t tmpreg;
972 SET_BIT(RCC->AHB3LPENR, Periphs);
973 /* Delay after an RCC peripheral clock enabling */
974 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
975 (void)tmpreg;
976 }
977
978 /**
979 * @brief Disable AHB3 peripheral clocks in low-power mode
980 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
981 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
982 * @param Periphs This parameter can be a combination of the following values:
983 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
984 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
985 *
986 * (*) value not defined in all devices.
987 * @retval None
988 */
LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)989 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
990 {
991 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
992 }
993
994 /**
995 * @}
996 */
997
998 /** @defgroup BUS_LL_EF_APB1 APB1
999 * @{
1000 */
1001
1002 /**
1003 * @brief Enable APB1 peripherals clock.
1004 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
1005 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
1006 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
1007 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
1008 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
1009 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
1010 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
1011 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
1012 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
1013 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1014 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
1015 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
1016 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
1017 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1018 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
1019 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
1020 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
1021 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
1022 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
1023 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
1024 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
1025 * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n
1026 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
1027 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
1028 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
1029 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
1030 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
1031 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
1032 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
1033 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
1034 * APB1ENR RTCEN LL_APB1_GRP1_EnableClock
1035 * @param Periphs This parameter can be a combination of the following values:
1036 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1037 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1038 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1039 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1040 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1041 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1042 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1043 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1044 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1045 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1046 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1047 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1048 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1049 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1050 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1051 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1052 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1053 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1054 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1055 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1056 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1057 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1058 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1059 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1060 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1061 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1062 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1063 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1064 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1065 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1066 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1067 *
1068 * (*) value not defined in all devices.
1069 * @retval None
1070 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1071 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1072 {
1073 __IO uint32_t tmpreg;
1074 SET_BIT(RCC->APB1ENR, Periphs);
1075 /* Delay after an RCC peripheral clock enabling */
1076 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
1077 (void)tmpreg;
1078 }
1079
1080 /**
1081 * @brief Check if APB1 peripheral clock is enabled or not
1082 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1083 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1084 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1085 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1086 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1087 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1088 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1089 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1090 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1091 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1092 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1093 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1094 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1095 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1096 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1097 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1098 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1099 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1100 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1101 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1102 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1103 * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n
1104 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1105 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1106 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
1107 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1108 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
1109 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
1110 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1111 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
1112 * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock
1113 * @param Periphs This parameter can be a combination of the following values:
1114 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1115 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1116 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1117 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1118 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1119 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1120 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1121 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1122 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1123 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1124 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1125 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1126 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1127 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1128 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1129 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1130 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1131 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1132 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1133 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1134 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1135 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1136 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1137 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1138 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1139 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1140 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1141 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1142 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1143 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1144 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1145 *
1146 * (*) value not defined in all devices.
1147 * @retval State of Periphs (1 or 0).
1148 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1149 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1150 {
1151 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
1152 }
1153
1154 /**
1155 * @brief Disable APB1 peripherals clock.
1156 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
1157 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
1158 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
1159 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
1160 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
1161 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
1162 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
1163 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
1164 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
1165 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1166 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
1167 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
1168 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
1169 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1170 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
1171 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
1172 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
1173 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
1174 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
1175 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
1176 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
1177 * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n
1178 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
1179 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
1180 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
1181 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
1182 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
1183 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
1184 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
1185 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
1186 * APB1ENR RTCEN LL_APB1_GRP1_DisableClock
1187 * @param Periphs This parameter can be a combination of the following values:
1188 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1189 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1190 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1191 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1192 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1193 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1194 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1195 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1196 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1197 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1198 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1199 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1200 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1201 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1202 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1203 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1204 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1205 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1206 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1207 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1208 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1209 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1210 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1211 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1212 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1213 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1214 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1215 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1216 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1217 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1218 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1219 *
1220 * (*) value not defined in all devices.
1221 * @retval None
1222 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1223 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1224 {
1225 CLEAR_BIT(RCC->APB1ENR, Periphs);
1226 }
1227
1228 /**
1229 * @brief Force APB1 peripherals reset.
1230 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1231 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1232 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1233 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1234 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1235 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1236 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1237 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1238 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1239 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
1240 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
1241 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1242 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1243 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1244 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
1245 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
1246 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
1247 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
1248 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1249 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1250 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1251 * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n
1252 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
1253 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
1254 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
1255 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
1256 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
1257 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
1258 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
1259 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
1260 * @param Periphs This parameter can be a combination of the following values:
1261 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1262 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1263 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1264 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1265 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1266 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1267 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1268 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1269 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1270 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1271 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1272 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1273 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1274 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1275 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1276 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1277 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1278 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1279 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1280 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1281 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1282 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1283 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1284 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1285 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1286 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1287 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1288 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1289 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1290 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1291 *
1292 * (*) value not defined in all devices.
1293 * @retval None
1294 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1295 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1296 {
1297 SET_BIT(RCC->APB1RSTR, Periphs);
1298 }
1299
1300 /**
1301 * @brief Release APB1 peripherals reset.
1302 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1303 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1304 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1305 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1306 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1307 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1308 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
1309 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
1310 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
1311 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
1312 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
1313 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1314 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1315 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
1316 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1317 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1318 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1319 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1320 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1321 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1322 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
1323 * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n
1324 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
1325 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
1326 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
1327 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1328 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
1329 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
1330 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1331 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
1332 * @param Periphs This parameter can be a combination of the following values:
1333 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1334 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1335 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1336 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1337 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1338 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1339 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1340 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1341 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1342 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1343 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1344 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1345 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1346 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1347 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1348 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1349 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1350 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1351 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1352 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1353 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1354 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1355 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1356 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1357 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1358 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1359 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1360 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1361 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1362 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1363 *
1364 * (*) value not defined in all devices.
1365 * @retval None
1366 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1367 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1368 {
1369 CLEAR_BIT(RCC->APB1RSTR, Periphs);
1370 }
1371
1372 /**
1373 * @brief Enable APB1 peripheral clocks in low-power mode
1374 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1375 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1376 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1377 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1378 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
1379 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1380 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
1381 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
1382 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
1383 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1384 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
1385 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1386 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1387 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
1388 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1389 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1390 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1391 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1392 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1393 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1394 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1395 * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1396 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1397 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1398 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1399 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
1400 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
1401 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
1402 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1403 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
1404 * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower
1405 * @param Periphs This parameter can be a combination of the following values:
1406 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1407 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1408 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1409 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1410 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1411 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1412 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1413 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1414 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1415 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1416 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1417 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1418 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1419 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1420 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1421 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1422 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1423 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1424 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1425 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1426 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1427 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1428 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1429 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1430 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1431 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1432 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1433 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1434 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1435 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1436 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1437 *
1438 * (*) value not defined in all devices.
1439 * @retval None
1440 */
LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)1441 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
1442 {
1443 __IO uint32_t tmpreg;
1444 SET_BIT(RCC->APB1LPENR, Periphs);
1445 /* Delay after an RCC peripheral clock enabling */
1446 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
1447 (void)tmpreg;
1448 }
1449
1450 /**
1451 * @brief Disable APB1 peripheral clocks in low-power mode
1452 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1453 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1454 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1455 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1456 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
1457 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1458 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
1459 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
1460 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
1461 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1462 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
1463 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1464 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1465 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
1466 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1467 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1468 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1469 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1470 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1471 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1472 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1473 * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1474 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1475 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1476 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1477 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
1478 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
1479 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
1480 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1481 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
1482 * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower
1483 * @param Periphs This parameter can be a combination of the following values:
1484 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1485 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1486 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1487 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1488 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1489 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1490 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1491 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1492 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1493 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1494 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1495 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1496 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1497 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1498 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1499 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1500 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1501 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1502 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1503 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1504 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1505 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1506 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1507 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1508 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1509 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1510 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1511 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1512 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1513 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1514 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1515 *
1516 * (*) value not defined in all devices.
1517 * @retval None
1518 */
LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)1519 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
1520 {
1521 CLEAR_BIT(RCC->APB1LPENR, Periphs);
1522 }
1523
1524 /**
1525 * @}
1526 */
1527
1528 /** @defgroup BUS_LL_EF_APB2 APB2
1529 * @{
1530 */
1531
1532 /**
1533 * @brief Enable APB2 peripherals clock.
1534 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1535 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1536 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1537 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
1538 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
1539 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
1540 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
1541 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
1542 * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n
1543 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1544 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1545 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1546 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1547 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
1548 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
1549 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
1550 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
1551 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1552 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1553 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1554 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
1555 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1556 * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n
1557 * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock
1558 * @param Periphs This parameter can be a combination of the following values:
1559 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1560 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1561 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1562 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1563 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1564 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1565 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1566 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1567 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1568 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1569 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1570 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1571 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1572 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1573 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1574 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1575 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1576 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1577 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1578 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1579 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1580 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1581 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1582 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1583 *
1584 * (*) value not defined in all devices.
1585 * @retval None
1586 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1587 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1588 {
1589 __IO uint32_t tmpreg;
1590 SET_BIT(RCC->APB2ENR, Periphs);
1591 /* Delay after an RCC peripheral clock enabling */
1592 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1593 (void)tmpreg;
1594 }
1595
1596 /**
1597 * @brief Check if APB2 peripheral clock is enabled or not
1598 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1599 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1600 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1601 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
1602 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
1603 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
1604 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
1605 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
1606 * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n
1607 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1608 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1609 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1610 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1611 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
1612 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
1613 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
1614 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
1615 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1616 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1617 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1618 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
1619 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1620 * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n
1621 * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock
1622 * @param Periphs This parameter can be a combination of the following values:
1623 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1624 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1625 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1626 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1627 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1628 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1629 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1630 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1631 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1632 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1633 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1634 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1635 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1636 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1637 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1638 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1639 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1640 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1641 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1642 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1643 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1644 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1645 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1646 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1647 *
1648 * (*) value not defined in all devices.
1649 * @retval State of Periphs (1 or 0).
1650 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1651 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1652 {
1653 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
1654 }
1655
1656 /**
1657 * @brief Disable APB2 peripherals clock.
1658 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1659 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1660 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1661 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
1662 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
1663 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
1664 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
1665 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
1666 * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n
1667 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1668 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1669 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1670 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
1671 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
1672 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
1673 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
1674 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
1675 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1676 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1677 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1678 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
1679 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1680 * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n
1681 * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock
1682 * @param Periphs This parameter can be a combination of the following values:
1683 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1684 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1685 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1686 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1687 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1688 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1689 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1690 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1691 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1692 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1693 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1694 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1695 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1696 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1697 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1698 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1699 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1700 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1701 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1702 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1703 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1704 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1705 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1706 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1707 *
1708 * (*) value not defined in all devices.
1709 * @retval None
1710 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1711 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1712 {
1713 CLEAR_BIT(RCC->APB2ENR, Periphs);
1714 }
1715
1716 /**
1717 * @brief Force APB2 peripherals reset.
1718 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1719 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1720 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1721 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
1722 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1723 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
1724 * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n
1725 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1726 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1727 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1728 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
1729 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
1730 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
1731 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
1732 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
1733 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1734 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1735 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1736 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
1737 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1738 * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n
1739 * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset
1740 * @param Periphs This parameter can be a combination of the following values:
1741 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1742 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1744 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1745 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1746 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1747 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1748 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1749 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1750 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1751 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1752 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1753 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1754 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1755 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1756 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1757 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1758 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1759 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1760 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1761 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1762 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1763 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1764 *
1765 * (*) value not defined in all devices.
1766 * @retval None
1767 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1768 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1769 {
1770 SET_BIT(RCC->APB2RSTR, Periphs);
1771 }
1772
1773 /**
1774 * @brief Release APB2 peripherals reset.
1775 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1776 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1777 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1778 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
1779 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1780 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
1781 * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n
1782 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1783 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1784 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1785 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
1786 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
1787 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
1788 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
1789 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
1790 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1791 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1792 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1793 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
1794 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1795 * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n
1796 * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset
1797 * @param Periphs This parameter can be a combination of the following values:
1798 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1799 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1800 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1801 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1802 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1803 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1804 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1805 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1806 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1807 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1808 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1809 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1810 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1811 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1812 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1813 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1814 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1815 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1816 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1817 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1818 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1819 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1820 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1821 *
1822 * (*) value not defined in all devices.
1823 * @retval None
1824 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1825 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1826 {
1827 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1828 }
1829
1830 /**
1831 * @brief Enable APB2 peripheral clocks in low-power mode
1832 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1833 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
1834 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1835 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1836 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1837 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1838 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
1839 * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1840 * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1841 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1842 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
1843 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
1844 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1845 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1846 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
1847 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
1848 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1849 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1850 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1851 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
1852 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1853 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1854 * APB2LPENR MDIOLPEN LL_APB2_GRP1_EnableClockLowPower
1855 * @param Periphs This parameter can be a combination of the following values:
1856 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1857 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1858 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1859 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1860 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1861 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1862 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1863 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1864 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1865 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1866 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1867 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1868 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1869 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1870 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1871 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1872 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1873 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1874 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1875 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1876 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1877 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1878 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1879 *
1880 * (*) value not defined in all devices.
1881 * @retval None
1882 */
LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)1883 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
1884 {
1885 __IO uint32_t tmpreg;
1886 SET_BIT(RCC->APB2LPENR, Periphs);
1887 /* Delay after an RCC peripheral clock enabling */
1888 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
1889 (void)tmpreg;
1890 }
1891
1892 /**
1893 * @brief Disable APB2 peripheral clocks in low-power mode
1894 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1895 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
1896 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1897 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
1898 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1899 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1900 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
1901 * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1902 * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1903 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1904 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
1905 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
1906 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
1907 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
1908 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
1909 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
1910 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
1911 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1912 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1913 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
1914 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
1915 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1916 * APB2LPENR MDIOLPEN LL_APB2_GRP1_DisableClockLowPower
1917 * @param Periphs This parameter can be a combination of the following values:
1918 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1919 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1920 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1921 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1922 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1923 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1924 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1925 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1926 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1927 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1928 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1929 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1930 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1931 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1932 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1933 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1934 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1935 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1936 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1937 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1938 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1939 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1940 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1941 *
1942 * (*) value not defined in all devices.
1943 * @retval None
1944 */
LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)1945 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
1946 {
1947 CLEAR_BIT(RCC->APB2LPENR, Periphs);
1948 }
1949
1950 /**
1951 * @}
1952 */
1953
1954 /**
1955 * @}
1956 */
1957
1958 /**
1959 * @}
1960 */
1961
1962 #endif /* defined(RCC) */
1963
1964 /**
1965 * @}
1966 */
1967
1968 #ifdef __cplusplus
1969 }
1970 #endif
1971
1972 #endif /* __STM32F7xx_LL_BUS_H */
1973
1974
