1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2022 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ##### RCC Limitations #####
20 ==============================================================================
21 [..]
22 A delay between an RCC peripheral clock enable and the effective peripheral
23 enabling should be taken into account in order to manage the peripheral read/write
24 from/to registers.
25 (+) This delay depends on the peripheral mapping.
26 (++) AHB & APB peripherals, 1 dummy read is necessary
27
28 [..]
29 Workarounds:
30 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
31 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
32
33 @endverbatim
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32C0xx_LL_BUS_H
39 #define STM32C0xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32c0xx.h"
47
48 /** @addtogroup STM32C0xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60
61 /* Private constants ---------------------------------------------------------*/
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
68 * @{
69 */
70
71 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
72 * @{
73 */
74 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
75 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
76 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
77 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN
78 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
79 /**
80 * @}
81 */
82
83
84 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
85 * @{
86 */
87 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
88 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
89 #define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN
90 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
91 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
92 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN
93 #define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN
94 #define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
95
96 /**
97 * @}
98 */
99
100 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
101 * @{
102 */
103 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
104 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
105 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APBENR2_TIM1EN
106 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APBENR2_SPI1EN
107 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APBENR2_USART1EN
108 #define LL_APB2_GRP1_PERIPH_TIM14 RCC_APBENR2_TIM14EN
109 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APBENR2_TIM16EN
110 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APBENR2_TIM17EN
111 #define LL_APB2_GRP1_PERIPH_ADC RCC_APBENR2_ADCEN
112
113 /**
114 * @}
115 */
116
117 /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
118 * @{
119 */
120 #define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
121 #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
122 #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
123 #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN
124 #if defined(STM32C031xx)
125 #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN
126 #endif
127 #define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN
128
129 /**
130 * @}
131 */
132
133 /**
134 * @}
135 */
136
137 /* Exported macro ------------------------------------------------------------*/
138 /* Exported functions --------------------------------------------------------*/
139 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
140 * @{
141 */
142
143 /** @defgroup BUS_LL_EF_AHB1 AHB1
144 * @{
145 */
146
147 /**
148 * @brief Enable AHB1 peripherals clock.
149 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
150 * AHBENR FLASHEN LL_AHB1_GRP1_EnableClock\n
151 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
152 * @param Periphs This parameter can be a combination of the following values:
153 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
154 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
155 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
156 * @retval None
157 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)158 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
159 {
160 __IO uint32_t tmpreg;
161 SET_BIT(RCC->AHBENR, Periphs);
162 /* Delay after an RCC peripheral clock enabling */
163 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
164 (void)tmpreg;
165 }
166
167 /**
168 * @brief Check if AHB1 peripheral clock is enabled or not
169 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
170 * AHBENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
171 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
172 * @param Periphs This parameter can be a combination of the following values:
173 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
174 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
175 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
176 * @retval State of Periphs (1 or 0).
177 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)178 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
179 {
180 return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL);
181 }
182
183 /**
184 * @brief Disable AHB1 peripherals clock.
185 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
186 * AHBENR FLASHEN LL_AHB1_GRP1_DisableClock\n
187 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
188 * @param Periphs This parameter can be a combination of the following values:
189 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
190 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
191 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
192 * @retval None
193 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)194 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
195 {
196 CLEAR_BIT(RCC->AHBENR, Periphs);
197 }
198
199 /**
200 * @brief Force AHB1 peripherals reset.
201 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
202 * AHBRSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
203 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
204 * @param Periphs This parameter can be a combination of the following values:
205 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
206 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
207 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
208 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
209 * @retval None
210 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)211 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
212 {
213 SET_BIT(RCC->AHBRSTR, Periphs);
214 }
215
216 /**
217 * @brief Release AHB1 peripherals reset.
218 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
219 * AHBRSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
220 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
221 * @param Periphs This parameter can be a combination of the following values:
222 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
223 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
224 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
225 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
226 * @retval None
227 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)228 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
229 {
230 CLEAR_BIT(RCC->AHBRSTR, Periphs);
231 }
232
233 /**
234 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
235 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
236 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
237 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
238 * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
239 * @param Periphs This parameter can be a combination of the following values:
240 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
241 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
242 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
243 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
244 * @retval None
245 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)246 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
247 {
248 __IO uint32_t tmpreg;
249 SET_BIT(RCC->AHBSMENR, Periphs);
250 /* Delay after an RCC peripheral clock enabling */
251 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
252 (void)tmpreg;
253 }
254
255 /**
256 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
257 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
258 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
259 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
260 * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
261 * @param Periphs This parameter can be a combination of the following values:
262 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
263 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
264 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
265 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
266 * @retval None
267 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)268 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
269 {
270 CLEAR_BIT(RCC->AHBSMENR, Periphs);
271 }
272
273 /**
274 * @}
275 */
276
277 /** @defgroup BUS_LL_EF_APB1 APB1
278 * @{
279 */
280
281 /**
282 * @brief Enable APB1 peripherals clock.
283 * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
284 * APBENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
285 * APBENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
286 * APBENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
287 * APBENR1 DBGEN LL_APB1_GRP1_EnableClock\n
288 * APBENR1 PWREN LL_APB1_GRP1_EnableClock\n
289 * @param Periphs This parameter can be a combination of the following values:
290 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
291 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
292 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
293 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
294 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
295 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
296 * @retval None
297 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)298 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
299 {
300 __IO uint32_t tmpreg;
301 SET_BIT(RCC->APBENR1, Periphs);
302 /* Delay after an RCC peripheral clock enabling */
303 tmpreg = READ_BIT(RCC->APBENR1, Periphs);
304 (void)tmpreg;
305 }
306
307 /**
308 * @brief Check if APB1 peripheral clock is enabled or not
309 * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
310 * APBENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
311 * APBENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
312 * APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
313 * APBENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
314 * APBENR1 DBGEN LL_APB1_GRP1_IsEnabledClock\n
315 * APBENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
316 * @param Periphs This parameter can be a combination of the following values:
317 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
318 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
319 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
320 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
321 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
322 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
323 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
324 * @retval State of Periphs (1 or 0).
325 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)326 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
327 {
328 return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
329 }
330
331 /**
332 * @brief Disable APB1 peripherals clock.
333 * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
334 * APBENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
335 * APBENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
336 * APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
337 * APBENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
338 * APBENR1 DBGEN LL_APB1_GRP1_DisableClock\n
339 * APBENR1 PWREN LL_APB1_GRP1_DisableClock\n
340 * @param Periphs This parameter can be a combination of the following values:
341 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
342 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
343 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
344 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
345 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
346 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
347 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
348 * @retval None
349 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)350 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
351 {
352 CLEAR_BIT(RCC->APBENR1, Periphs);
353 }
354
355 /**
356 * @brief Force APB1 peripherals reset.
357 * @rmtoll APBRSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
358 * APBRSTR1 RTCRST LL_APB1_GRP1_ForceReset\n
359 * APBRSTR1 WWDGRST LL_APB1_GRP1_ForceReset\n
360 * APBRSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
361 * APBRSTR1 DBGRST LL_APB1_GRP1_ForceReset\n
362 * APBRSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
363 * @param Periphs This parameter can be a combination of the following values:
364 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
365 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
366 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
367 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
368 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
369 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
370 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
371 * @retval None
372 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)373 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
374 {
375 SET_BIT(RCC->APBRSTR1, Periphs);
376 }
377
378 /**
379 * @brief Release APB1 peripherals reset.
380 * @rmtoll APBRSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
381 * APBRSTR1 RTCRST LL_APB1_GRP1_ReleaseReset\n
382 * APBRSTR1 WWDGRST LL_APB1_GRP1_ReleaseReset\n
383 * APBRSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
384 * APBRSTR1 DBGRST LL_APB1_GRP1_ReleaseReset\n
385 * APBRSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
386 * @param Periphs This parameter can be a combination of the following values:
387 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
388 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
389 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
390 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
391 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
392 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
393 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
394 * @retval None
395 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)396 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
397 {
398 CLEAR_BIT(RCC->APBRSTR1, Periphs);
399 }
400
401 /**
402 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
403 * @rmtoll APBSMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
404 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
405 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
406 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
407 * APBSMENR1 DBGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
408 * APBSMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
409 * @param Periphs This parameter can be a combination of the following values:
410 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
411 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
412 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
413 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
414 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
415 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
416 * @retval None
417 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)418 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
419 {
420 __IO uint32_t tmpreg;
421 SET_BIT(RCC->APBSMENR1, Periphs);
422 /* Delay after an RCC peripheral clock enabling */
423 tmpreg = READ_BIT(RCC->APBSMENR1, Periphs);
424 (void)tmpreg;
425 }
426
427 /**
428 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
429 * @rmtoll APBSMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
430 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
431 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
432 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
433 * APBSMENR1 DBGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
434 * APBSMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
435 * @param Periphs This parameter can be a combination of the following values:
436 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
437 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
438 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
439 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
440 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
441 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
442 * @retval None
443 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)444 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
445 {
446 CLEAR_BIT(RCC->APBSMENR1, Periphs);
447 }
448
449 /**
450 * @}
451 */
452
453 /** @defgroup BUS_LL_EF_APB2 APB2
454 * @{
455 */
456
457 /**
458 * @brief Enable APB2 peripherals clock.
459 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_EnableClock\n
460 * APBENR2 TIM1EN LL_APB2_GRP1_EnableClock\n
461 * APBENR2 SPI1EN LL_APB2_GRP1_EnableClock\n
462 * APBENR2 USART1EN LL_APB2_GRP1_EnableClock\n
463 * APBENR2 TIM14EN LL_APB2_GRP1_EnableClock\n
464 * APBENR2 TIM16EN LL_APB2_GRP1_EnableClock\n
465 * APBENR2 TIM17EN LL_APB2_GRP1_EnableClock\n
466 * APBENR2 ADCEN LL_APB2_GRP1_EnableClock
467 * @param Periphs This parameter can be a combination of the following values:
468 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
469 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
470 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
471 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
472 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
473 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
474 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
475 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
476 * @retval None
477 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)478 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
479 {
480 __IO uint32_t tmpreg;
481 SET_BIT(RCC->APBENR2, Periphs);
482 /* Delay after an RCC peripheral clock enabling */
483 tmpreg = READ_BIT(RCC->APBENR2, Periphs);
484 (void)tmpreg;
485 }
486
487 /**
488 * @brief Check if APB2 peripheral clock is enabled or not
489 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
490 * APBENR2 TIM1EN LL_APB2_GRP1_IsEnabledClock\n
491 * APBENR2 SPI1EN LL_APB2_GRP1_IsEnabledClock\n
492 * APBENR2 USART1EN LL_APB2_GRP1_IsEnabledClock\n
493 * APBENR2 TIM14EN LL_APB2_GRP1_IsEnabledClock\n
494 * APBENR2 TIM16EN LL_APB2_GRP1_IsEnabledClock\n
495 * APBENR2 TIM17EN LL_APB2_GRP1_IsEnabledClock\n
496 * APBENR2 ADCEN LL_APB2_GRP1_IsEnabledClock
497 * @param Periphs This parameter can be a combination of the following values:
498 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
499 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
500 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
501 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
502 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
503 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
504 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
505 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
506 * @retval State of Periphs (1 or 0).
507 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)508 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
509 {
510 return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
511 }
512
513 /**
514 * @brief Disable APB2 peripherals clock.
515 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_DisableClock\n
516 * APBENR2 TIM1EN LL_APB2_GRP1_DisableClock\n
517 * APBENR2 SPI1EN LL_APB2_GRP1_DisableClock\n
518 * APBENR2 USART1EN LL_APB2_GRP1_DisableClock\n
519 * APBENR2 TIM14EN LL_APB2_GRP1_DisableClock\n
520 * APBENR2 TIM16EN LL_APB2_GRP1_DisableClock\n
521 * APBENR2 TIM17EN LL_APB2_GRP1_DisableClock\n
522 * APBENR2 ADCEN LL_APB2_GRP1_DisableClock
523 * @param Periphs This parameter can be a combination of the following values:
524 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
525 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
526 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
527 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
528 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
529 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
530 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
531 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
532 * @retval None
533 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)534 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
535 {
536 CLEAR_BIT(RCC->APBENR2, Periphs);
537 }
538
539 /**
540 * @brief Force APB2 peripherals reset.
541 * @rmtoll APBRSTR2 SYSCFGRST LL_APB2_GRP1_ForceReset\n
542 * APBRSTR2 TIM1RST LL_APB2_GRP1_ForceReset\n
543 * APBRSTR2 SPI1RST LL_APB2_GRP1_ForceReset\n
544 * APBRSTR2 USART1RST LL_APB2_GRP1_ForceReset\n
545 * APBRSTR2 TIM14RST LL_APB2_GRP1_ForceReset\n
546 * APBRSTR2 TIM16RST LL_APB2_GRP1_ForceReset\n
547 * APBRSTR2 TIM17RST LL_APB2_GRP1_ForceReset\n
548 * APBRSTR2 ADCRST LL_APB2_GRP1_ForceReset
549 * @param Periphs This parameter can be a combination of the following values:
550 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
551 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
552 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
553 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
554 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
555 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
556 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
557 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
558 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
559 * @retval None
560 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)561 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
562 {
563 SET_BIT(RCC->APBRSTR2, Periphs);
564 }
565
566 /**
567 * @brief Release APB2 peripherals reset.
568 * @rmtoll APBRSTR2 SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
569 * APBRSTR2 TIM1RST LL_APB2_GRP1_ReleaseReset\n
570 * APBRSTR2 SPI1RST LL_APB2_GRP1_ReleaseReset\n
571 * APBRSTR2 USART1RST LL_APB2_GRP1_ReleaseReset\n
572 * APBRSTR2 TIM14RST LL_APB2_GRP1_ReleaseReset\n
573 * APBRSTR2 TIM16RST LL_APB2_GRP1_ReleaseReset\n
574 * APBRSTR2 TIM17RST LL_APB2_GRP1_ReleaseReset\n
575 * APBRSTR2 ADCRST LL_APB2_GRP1_ReleaseReset
576 * @param Periphs This parameter can be a combination of the following values:
577 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
578 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
579 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
580 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
581 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
582 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
583 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
584 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
585 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
586 * @retval None
587 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)588 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
589 {
590 CLEAR_BIT(RCC->APBRSTR2, Periphs);
591 }
592
593 /**
594 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
595 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
596 * APBSMENR2 TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
597 * APBSMENR2 SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
598 * APBSMENR2 USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
599 * APBSMENR2 TIM14SMEN LL_APB2_GRP1_EnableClockStopSleep\n
600 * APBSMENR2 TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
601 * APBSMENR2 TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
602 * APBSMENR2 ADCSMEN LL_APB2_GRP1_EnableClockStopSleep
603 * @param Periphs This parameter can be a combination of the following values:
604 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
605 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
606 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
607 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
608 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
609 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
610 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
611 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
612 * @retval None
613 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)614 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
615 {
616 __IO uint32_t tmpreg;
617 SET_BIT(RCC->APBSMENR2, Periphs);
618 /* Delay after an RCC peripheral clock enabling */
619 tmpreg = READ_BIT(RCC->APBSMENR2, Periphs);
620 (void)tmpreg;
621 }
622
623 /**
624 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
625 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
626 * APBSMENR2 TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
627 * APBSMENR2 SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
628 * APBSMENR2 USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
629 * APBSMENR2 TIM14SMEN LL_APB2_GRP1_DisableClockStopSleep\n
630 * APBSMENR2 TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
631 * APBSMENR2 TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
632 * APBSMENR2 ADCSMEN LL_APB2_GRP1_DisableClockStopSleep
633 * @param Periphs This parameter can be a combination of the following values:
634 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
635 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
636 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
637 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
638 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
639 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
640 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
641 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
642 * @retval None
643 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)644 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
645 {
646 CLEAR_BIT(RCC->APBSMENR2, Periphs);
647 }
648
649 /**
650 * @}
651 */
652
653 /** @defgroup BUS_LL_EF_IOP IOP
654 * @{
655 */
656
657 /**
658 * @brief Enable IOP peripherals clock.
659 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n
660 * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n
661 * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n
662 * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n
663 * IOPENR GPIOFEN LL_IOP_GRP1_EnableClock
664 * @param Periphs This parameter can be a combination of the following values:
665 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
666 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
667 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
668 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
669 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
670 * @retval None
671 */
LL_IOP_GRP1_EnableClock(uint32_t Periphs)672 __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
673 {
674 __IO uint32_t tmpreg;
675 SET_BIT(RCC->IOPENR, Periphs);
676 /* Delay after an RCC peripheral clock enabling */
677 tmpreg = READ_BIT(RCC->IOPENR, Periphs);
678 (void)tmpreg;
679 }
680
681 /**
682 * @brief Check if IOP peripheral clock is enabled or not
683 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n
684 * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n
685 * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n
686 * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n
687 * IOPENR GPIOFEN LL_IOP_GRP1_IsEnabledClock
688 * @param Periphs This parameter can be a combination of the following values:
689 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
690 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
691 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
692 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
693 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
694 * @retval State of Periphs (1 or 0).
695 */
LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)696 __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
697 {
698 return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
699 }
700
701 /**
702 * @brief Disable IOP peripherals clock.
703 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n
704 * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n
705 * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n
706 * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n
707 * IOPENR GPIOFEN LL_IOP_GRP1_DisableClock
708 * @param Periphs This parameter can be a combination of the following values:
709 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
710 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
711 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
712 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
713 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
714 * @retval None
715 */
LL_IOP_GRP1_DisableClock(uint32_t Periphs)716 __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
717 {
718 CLEAR_BIT(RCC->IOPENR, Periphs);
719 }
720
721 /**
722 * @brief Disable IOP peripherals clock.
723 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ForceReset\n
724 * IOPRSTR GPIOBRST LL_IOP_GRP1_ForceReset\n
725 * IOPRSTR GPIOCRST LL_IOP_GRP1_ForceReset\n
726 * IOPRSTR GPIODRST LL_IOP_GRP1_ForceReset\n
727 * IOPRSTR GPIOFRST LL_IOP_GRP1_ForceReset
728 * @param Periphs This parameter can be a combination of the following values:
729 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
730 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
731 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
732 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
733 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
734 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
735 * @retval None
736 */
LL_IOP_GRP1_ForceReset(uint32_t Periphs)737 __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
738 {
739 SET_BIT(RCC->IOPRSTR, Periphs);
740 }
741
742 /**
743 * @brief Release IOP peripherals reset.
744 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ReleaseReset\n
745 * IOPRSTR GPIOBRST LL_IOP_GRP1_ReleaseReset\n
746 * IOPRSTR GPIOCRST LL_IOP_GRP1_ReleaseReset\n
747 * IOPRSTR GPIODRST LL_IOP_GRP1_ReleaseReset\n
748 * IOPRSTR GPIOFRST LL_IOP_GRP1_ReleaseReset
749 * @param Periphs This parameter can be a combination of the following values:
750 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
751 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
752 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
753 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
754 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
755 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
756 * @retval None
757 */
LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)758 __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
759 {
760 CLEAR_BIT(RCC->IOPRSTR, Periphs);
761 }
762
763 /**
764 * @brief Enable IOP peripheral clocks in Sleep and Stop modes
765 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_EnableClockStopSleep\n
766 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_EnableClockStopSleep\n
767 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_EnableClockStopSleep\n
768 * IOPSMENR GPIODSMEN LL_IOP_GRP1_EnableClockStopSleep\n
769 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_EnableClockStopSleep
770 * @param Periphs This parameter can be a combination of the following values:
771 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
772 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
773 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
774 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
775 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
776 * @retval None
777 */
LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)778 __STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)
779 {
780 __IO uint32_t tmpreg;
781 SET_BIT(RCC->IOPSMENR, Periphs);
782 /* Delay after an RCC peripheral clock enabling */
783 tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
784 (void)tmpreg;
785 }
786
787 /**
788 * @brief Disable IOP peripheral clocks in Sleep and Stop modes
789 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_DisableClockStopSleep\n
790 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_DisableClockStopSleep\n
791 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_DisableClockStopSleep\n
792 * IOPSMENR GPIODSMEN LL_IOP_GRP1_DisableClockStopSleep\n
793 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_DisableClockStopSleep
794 * @param Periphs This parameter can be a combination of the following values:
795 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
796 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
797 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
798 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
799 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
800 * @retval None
801 */
LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)802 __STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)
803 {
804 CLEAR_BIT(RCC->IOPSMENR, Periphs);
805 }
806
807 /**
808 * @}
809 */
810
811
812 /**
813 * @}
814 */
815
816 /**
817 * @}
818 */
819
820 #endif /* defined(RCC) */
821
822 /**
823 * @}
824 */
825
826 #ifdef __cplusplus
827 }
828 #endif
829
830 #endif /* STM32C0xx_LL_BUS_H */
831
