1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2019 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef STM32L5xx_LL_BUS_H
37 #define STM32L5xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32l5xx.h"
45
46 /** @addtogroup STM32L5xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /* Private macros ------------------------------------------------------------*/
60
61 /* Exported types ------------------------------------------------------------*/
62 /* Exported constants --------------------------------------------------------*/
63 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
64 * @{
65 */
66
67 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
68 * @{
69 */
70 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
71 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
72 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
73 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
74 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
75 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
76 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
77 #define LL_AHB1_GRP1_PERIPH_GTZC RCC_AHB1ENR_GTZCEN
78 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
79 #define LL_AHB1_GRP1_PERIPH_ICACHE RCC_AHB1SMENR_ICACHESMEN
80 /**
81 * @}
82 */
83
84 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
85 * @{
86 */
87 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
88 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
89 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
90 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
91 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
92 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
93 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
94 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
95 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
96 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
97 #if defined(AES)
98 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
99 #endif /* AES */
100 #if defined(HASH)
101 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
102 #endif /* HASH */
103 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
104 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN
105 #define LL_AHB2_GRP1_PERIPH_OTFDEC1 RCC_AHB2ENR_OTFDEC1EN
106 #define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN
107 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
108 /**
109 * @}
110 */
111
112 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
113 * @{
114 */
115 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
116 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
117 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
118 /**
119 * @}
120 */
121
122 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
123 * @{
124 */
125 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
126 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
127 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
128 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
129 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
130 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
131 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
132 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
133 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
134 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
135 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
136 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
137 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
138 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
139 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
140 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
141 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
142 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
143 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
144 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
145 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
146 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
147 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
148 /**
149 * @}
150 */
151
152
153 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
154 * @{
155 */
156 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
157 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
158 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
159 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
160 #define LL_APB1_GRP2_PERIPH_LPTIM3 RCC_APB1ENR2_LPTIM3EN
161 #define LL_APB1_GRP2_PERIPH_FDCAN1 RCC_APB1ENR2_FDCAN1EN
162 #define LL_APB1_GRP2_PERIPH_USB RCC_APB1ENR2_USBFSEN
163 #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
164 /**
165 * @}
166 */
167
168 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
169 * @{
170 */
171 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
172 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
173 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
174 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
175 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
176 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
177 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
178 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
179 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
180 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
181 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
182 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
183 /**
184 * @}
185 */
186
187 /**
188 * @}
189 */
190
191 /* Exported macro ------------------------------------------------------------*/
192 /* Exported functions --------------------------------------------------------*/
193 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
194 * @{
195 */
196
197 /** @defgroup BUS_LL_EF_AHB1 AHB1
198 * @{
199 */
200
201 /**
202 * @brief Enable AHB1 peripherals clock.
203 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
204 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
205 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
206 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
207 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
208 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
209 * AHB1ENR GTZCEN LL_AHB1_GRP1_EnableClock
210 * @param Periphs This parameter can be a combination of the following values:
211 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
212 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
213 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
214 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
215 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
216 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
217 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
218 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
219 * @retval None
220 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)221 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
222 {
223 __IO uint32_t tmpreg;
224 SET_BIT(RCC->AHB1ENR, Periphs);
225 /* Delay after an RCC peripheral clock enabling */
226 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
227 (void)tmpreg;
228 }
229
230 /**
231 * @brief Check if AHB1 peripheral clock is enabled or not
232 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
233 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
234 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
235 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
236 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
237 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
238 * AHB1ENR GTZCEN LL_AHB1_GRP1_IsEnabledClock
239 * @param Periphs This parameter can be a combination of the following values:
240 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
241 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
242 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
243 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
244 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
245 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
246 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
247 * @retval State of Periphs (1 or 0).
248 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)249 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
250 {
251 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
252 }
253
254 /**
255 * @brief Disable AHB1 peripherals clock.
256 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
257 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
258 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
259 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
260 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
261 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
262 * AHB1ENR GTZCEN LL_AHB1_GRP1_DisableClock
263 * @param Periphs This parameter can be a combination of the following values:
264 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
265 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
266 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
267 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
268 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
269 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
270 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
271 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
272 * @retval None
273 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)274 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
275 {
276 CLEAR_BIT(RCC->AHB1ENR, Periphs);
277 }
278
279 /**
280 * @brief Force AHB1 peripherals reset.
281 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
282 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
283 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
284 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
285 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
286 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
287 * @param Periphs This parameter can be a combination of the following values:
288 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
289 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
290 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
291 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
292 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
293 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
294 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
295 * @retval None
296 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)297 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
298 {
299 SET_BIT(RCC->AHB1RSTR, Periphs);
300 }
301
302 /**
303 * @brief Release AHB1 peripherals reset.
304 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
305 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
306 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
307 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
308 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
309 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
310 * @param Periphs This parameter can be a combination of the following values:
311 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
312 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
313 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
314 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
315 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
316 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
317 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
318 * @retval None
319 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)320 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
321 {
322 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
323 }
324
325 /**
326 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
327 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
328 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
329 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
330 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
331 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
332 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
333 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
334 * AHB1SMENR GTZCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
335 * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_EnableClockStopSleep
336 * @param Periphs This parameter can be a combination of the following values:
337 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
338 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
339 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
340 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
341 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
342 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
343 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
344 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
345 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
346 * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE
347 * @retval None
348 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)349 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
350 {
351 __IO uint32_t tmpreg;
352 SET_BIT(RCC->AHB1SMENR, Periphs);
353 /* Delay after an RCC peripheral clock enabling */
354 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
355 (void)tmpreg;
356 }
357
358 /**
359 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
360 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
361 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
362 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
363 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
364 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
365 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
366 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
367 * AHB1SMENR GTZCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
368 * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_DisableClockStopSleep
369 * @param Periphs This parameter can be a combination of the following values:
370 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
371 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
372 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
373 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
374 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
375 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
376 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
377 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
378 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
379 * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE
380 * @retval None
381 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)382 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
383 {
384 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
385 }
386
387 /**
388 * @}
389 */
390
391 /** @defgroup BUS_LL_EF_AHB2 AHB2
392 * @{
393 */
394
395 /**
396 * @brief Enable AHB2 peripherals clock.
397 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
398 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
399 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
400 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
401 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
402 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
403 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
404 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
405 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
406 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
407 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
408 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
409 * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n
410 * AHB2ENR OTFDEC1EN LL_AHB2_GRP1_EnableClock\n
411 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock
412 * @param Periphs This parameter can be a combination of the following values:
413 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
414 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
415 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
416 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
417 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
418 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
419 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
420 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
421 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
422 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
423 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
424 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
425 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
426 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
427 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
428 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
429 *
430 * (*) value not defined in all devices.
431 * @retval None
432 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)433 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
434 {
435 __IO uint32_t tmpreg;
436 SET_BIT(RCC->AHB2ENR, Periphs);
437 /* Delay after an RCC peripheral clock enabling */
438 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
439 (void)tmpreg;
440 }
441
442 /**
443 * @brief Check if AHB2 peripheral clock is enabled or not
444 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
445 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
446 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
447 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
448 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
449 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
450 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
451 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
452 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
453 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
454 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
455 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
456 * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n
457 * AHB2ENR OTFDEC1EN LL_AHB2_GRP1_IsEnabledClock\n
458 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock
459 * @param Periphs This parameter can be a combination of the following values:
460 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
461 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
462 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
463 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
464 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
465 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
466 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
467 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
468 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
469 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
470 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
471 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
472 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
473 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
474 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
475 *
476 * (*) value not defined in all devices.
477 * @retval State of Periphs (1 or 0).
478 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)479 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
480 {
481 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
482 }
483
484 /**
485 * @brief Disable AHB2 peripherals clock.
486 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
487 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
488 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
489 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
490 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
491 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
492 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
493 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
494 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
495 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
496 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
497 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
498 * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n
499 * AHB2ENR OTFDEC1EN LL_AHB2_GRP1_DisableClock\n
500 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock
501 * @param Periphs This parameter can be a combination of the following values:
502 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
503 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
504 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
505 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
506 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
507 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
508 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
509 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
510 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
511 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
512 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
513 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
514 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
515 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
516 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
517 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
518 *
519 * (*) value not defined in all devices.
520 * @retval None
521 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)522 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
523 {
524 CLEAR_BIT(RCC->AHB2ENR, Periphs);
525 }
526
527 /**
528 * @brief Force AHB2 peripherals reset.
529 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
530 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
531 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
532 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
533 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
534 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
535 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
536 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
537 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
538 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
539 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
540 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
541 * AHB2RSTR PKARST LL_AHB2_GRP1_ForceReset\n
542 * AHB2RSTR OTFDEC1RST LL_AHB2_GRP1_ForceReset\n
543 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset
544 * @param Periphs This parameter can be a combination of the following values:
545 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
546 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
547 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
548 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
549 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
550 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
551 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
552 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
553 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
554 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
555 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
556 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
557 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
558 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
559 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
560 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
561 *
562 * (*) value not defined in all devices.
563 * @retval None
564 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)565 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
566 {
567 SET_BIT(RCC->AHB2RSTR, Periphs);
568 }
569
570 /**
571 * @brief Release AHB2 peripherals reset.
572 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
573 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
574 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
575 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
576 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
577 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
578 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
579 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
580 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
581 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
582 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
583 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
584 * AHB2RSTR PKARST LL_AHB2_GRP1_ReleaseReset\n
585 * AHB2RSTR OTFDEC1RST LL_AHB2_GRP1_ReleaseReset\n
586 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset
587 * @param Periphs This parameter can be a combination of the following values:
588 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
589 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
590 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
591 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
592 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
593 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
594 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
595 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
596 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
597 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
598 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
599 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
600 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
601 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
602 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
603 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
604 *
605 * (*) value not defined in all devices.
606 * @retval None
607 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)608 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
609 {
610 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
611 }
612
613 /**
614 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
615 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
616 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
617 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
618 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
619 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
620 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
621 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
622 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
623 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
624 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
625 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
626 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
627 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
628 * AHB2SMENR PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
629 * AHB2SMENR OTFDEC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
630 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep
631 * @param Periphs This parameter can be a combination of the following values:
632 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
633 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
634 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
635 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
636 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
637 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
638 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
639 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
640 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
641 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
642 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
643 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
644 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
645 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
646 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
647 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
648 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
649 *
650 * (*) value not defined in all devices.
651 * @retval None
652 */
LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)653 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
654 {
655 __IO uint32_t tmpreg;
656 SET_BIT(RCC->AHB2SMENR, Periphs);
657 /* Delay after an RCC peripheral clock enabling */
658 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
659 (void)tmpreg;
660 }
661
662 /**
663 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
664 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
665 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
666 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
667 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
668 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
669 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
670 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
671 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
672 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
673 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
674 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
675 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
676 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
677 * AHB2SMENR PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
678 * AHB2SMENR OTFDEC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
679 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep
680 * @param Periphs This parameter can be a combination of the following values:
681 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
682 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
683 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
684 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
685 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
686 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
687 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
688 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
689 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
690 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
691 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
692 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
693 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
694 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
695 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
696 * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*)
697 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
698 *
699 * (*) value not defined in all devices.
700 * @retval None
701 */
LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)702 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
703 {
704 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
705 }
706
707 /**
708 * @}
709 */
710
711 /** @defgroup BUS_LL_EF_AHB3 AHB3
712 * @{
713 */
714
715 /**
716 * @brief Enable AHB3 peripherals clock.
717 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
718 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock
719 * @param Periphs This parameter can be a combination of the following values:
720 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
721 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
722 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
723 * @retval None
724 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)725 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
726 {
727 __IO uint32_t tmpreg;
728 SET_BIT(RCC->AHB3ENR, Periphs);
729 /* Delay after an RCC peripheral clock enabling */
730 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
731 (void)tmpreg;
732 }
733
734 /**
735 * @brief Check if AHB3 peripheral clock is enabled or not
736 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
737 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock
738 * @param Periphs This parameter can be a combination of the following values:
739 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
740 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
741 * @retval State of Periphs (1 or 0).
742 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)743 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
744 {
745 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
746 }
747
748 /**
749 * @brief Disable AHB3 peripherals clock.
750 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
751 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock
752 * @param Periphs This parameter can be a combination of the following values:
753 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
754 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
755 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
756 * @retval None
757 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)758 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
759 {
760 CLEAR_BIT(RCC->AHB3ENR, Periphs);
761 }
762
763 /**
764 * @brief Force AHB3 peripherals reset.
765 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
766 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset
767 * @param Periphs This parameter can be a combination of the following values:
768 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
769 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
770 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
771 * @retval None
772 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)773 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
774 {
775 SET_BIT(RCC->AHB3RSTR, Periphs);
776 }
777
778 /**
779 * @brief Release AHB3 peripherals reset.
780 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
781 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset
782 * @param Periphs This parameter can be a combination of the following values:
783 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
784 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
785 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
786 * @retval None
787 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)788 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
789 {
790 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
791 }
792
793 /**
794 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
795 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
796 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep
797 * @param Periphs This parameter can be a combination of the following values:
798 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
799 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
800 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
801 * @retval None
802 */
LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)803 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
804 {
805 __IO uint32_t tmpreg;
806 SET_BIT(RCC->AHB3SMENR, Periphs);
807 /* Delay after an RCC peripheral clock enabling */
808 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
809 (void)tmpreg;
810 }
811
812 /**
813 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
814 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
815 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep
816 * @param Periphs This parameter can be a combination of the following values:
817 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
818 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
819 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
820 * @retval None
821 */
LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)822 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
823 {
824 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
825 }
826
827 /**
828 * @}
829 */
830
831 /** @defgroup BUS_LL_EF_APB1 APB1
832 * @{
833 */
834
835 /**
836 * @brief Enable APB1 peripherals clock.
837 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
838 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
839 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
840 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
841 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
842 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
843 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
844 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
845 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
846 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
847 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
848 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
849 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
850 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
851 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
852 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
853 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
854 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
855 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
856 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
857 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
858 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
859 * @param Periphs This parameter can be a combination of the following values:
860 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
861 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
862 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
863 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
864 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
865 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
866 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
867 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
868 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
869 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
870 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
871 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
872 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
873 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
874 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
875 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
876 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
877 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
878 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
879 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
880 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
881 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
882 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
883 * @retval None
884 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)885 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
886 {
887 __IO uint32_t tmpreg;
888 SET_BIT(RCC->APB1ENR1, Periphs);
889 /* Delay after an RCC peripheral clock enabling */
890 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
891 (void)tmpreg;
892 }
893
894 /**
895 * @brief Enable APB1 peripherals clock.
896 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
897 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
898 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock\n
899 * APB1ENR2 LPTIM3EN LL_APB1_GRP2_EnableClock\n
900 * APB1ENR2 FDCAN1EN LL_APB1_GRP2_EnableClock\n
901 * APB1ENR2 USBFSEN LL_APB1_GRP2_EnableClock\n
902 * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
903 * @param Periphs This parameter can be a combination of the following values:
904 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
905 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
906 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
907 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
908 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
909 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
910 * @arg @ref LL_APB1_GRP2_PERIPH_USB
911 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
912 * @retval None
913 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)914 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
915 {
916 __IO uint32_t tmpreg;
917 SET_BIT(RCC->APB1ENR2, Periphs);
918 /* Delay after an RCC peripheral clock enabling */
919 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
920 (void)tmpreg;
921 }
922
923 /**
924 * @brief Check if APB1 peripheral clock is enabled or not
925 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
926 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
927 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
928 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
929 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
930 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
931 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
932 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
933 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
934 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
935 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
936 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
937 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
938 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
939 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
940 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
941 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
942 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
943 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
944 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
945 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
946 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
947 * @param Periphs This parameter can be a combination of the following values:
948 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
949 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
950 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
951 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
952 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
953 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
954 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
955 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
956 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
957 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
958 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
959 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
960 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
961 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
962 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
963 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
964 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
965 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
966 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
967 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
968 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
969 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
970 * @retval State of Periphs (1 or 0).
971 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)972 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
973 {
974 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
975 }
976
977 /**
978 * @brief Check if APB1 peripheral clock is enabled or not
979 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
980 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
981 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n
982 * APB1ENR2 LPTIM3EN LL_APB1_GRP2_IsEnabledClock\n
983 * APB1ENR2 FDCAN1EN LL_APB1_GRP2_IsEnabledClock\n
984 * APB1ENR2 USBFSEN LL_APB1_GRP2_IsEnabledClock\n
985 * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
986 * @param Periphs This parameter can be a combination of the following values:
987 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
988 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
989 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
990 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
991 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
992 * @arg @ref LL_APB1_GRP2_PERIPH_USB
993 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
994 * @retval State of Periphs (1 or 0).
995 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)996 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
997 {
998 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
999 }
1000
1001 /**
1002 * @brief Disable APB1 peripherals clock.
1003 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1004 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1005 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
1006 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
1007 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
1008 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
1009 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
1010 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
1011 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1012 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
1013 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1014 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
1015 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
1016 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
1017 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1018 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1019 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1020 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
1021 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
1022 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
1023 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
1024 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
1025 * @param Periphs This parameter can be a combination of the following values:
1026 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1027 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1028 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1029 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1030 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1031 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1033 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1034 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1035 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1036 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1037 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1038 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1039 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1040 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1041 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1042 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1043 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1044 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1045 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1046 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1047 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1048 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1049 * @retval None
1050 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1051 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1052 {
1053 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1054 }
1055
1056 /**
1057 * @brief Disable APB1 peripherals clock.
1058 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
1059 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
1060 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock\n
1061 * APB1ENR2 LPTIM3EN LL_APB1_GRP2_DisableClock\n
1062 * APB1ENR2 FDCAN1EN LL_APB1_GRP2_DisableClock\n
1063 * APB1ENR2 USBFSEN LL_APB1_GRP2_DisableClock\n
1064 * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
1065 * @param Periphs This parameter can be a combination of the following values:
1066 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1067 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1068 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
1069 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1070 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1071 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
1072 * @arg @ref LL_APB1_GRP2_PERIPH_USB
1073 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1074 * @retval None
1075 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1076 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1077 {
1078 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1079 }
1080
1081 /**
1082 * @brief Force APB1 peripherals reset.
1083 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1084 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1085 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
1086 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
1087 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
1088 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
1089 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1090 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
1091 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1092 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
1093 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
1094 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
1095 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1096 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
1097 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1098 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
1099 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
1100 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
1101 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
1102 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1103 * @param Periphs This parameter can be a combination of the following values:
1104 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1105 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1106 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1107 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1108 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1109 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1110 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1111 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1112 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1113 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1114 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1115 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1116 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1117 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1118 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1119 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1120 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1121 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1122 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1123 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1124 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1125 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1126 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1127 * @retval None
1128 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1129 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1130 {
1131 SET_BIT(RCC->APB1RSTR1, Periphs);
1132 }
1133
1134 /**
1135 * @brief Force APB1 peripherals reset.
1136 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1137 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
1138 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset\n
1139 * APB1RSTR2 LPTIM3RST LL_APB1_GRP2_ForceReset\n
1140 * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_ForceReset\n
1141 * APB1RSTR2 USBFSRST LL_APB1_GRP2_ForceReset\n
1142 * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ForceReset
1143 * @param Periphs This parameter can be a combination of the following values:
1144 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1145 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1146 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
1147 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1148 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1149 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
1150 * @arg @ref LL_APB1_GRP2_PERIPH_USB
1151 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1152 * @retval None
1153 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1154 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1155 {
1156 SET_BIT(RCC->APB1RSTR2, Periphs);
1157 }
1158
1159 /**
1160 * @brief Release APB1 peripherals reset.
1161 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1162 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1163 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
1164 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
1165 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
1166 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
1167 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1168 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
1169 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1170 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
1171 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
1172 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
1173 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1174 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
1175 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1176 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
1177 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
1178 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
1179 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
1180 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1181 * @param Periphs This parameter can be a combination of the following values:
1182 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1183 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1184 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1185 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1186 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1187 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1188 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1189 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1190 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1191 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1192 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1193 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1194 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1195 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1196 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1197 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1198 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1199 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1200 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1201 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1202 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1203 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1204 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1205 * @retval None
1206 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1207 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1208 {
1209 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1210 }
1211
1212 /**
1213 * @brief Release APB1 peripherals reset.
1214 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1215 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
1216 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset\n
1217 * APB1RSTR2 LPTIM3RST LL_APB1_GRP2_ReleaseReset\n
1218 * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_ReleaseReset\n
1219 * APB1RSTR2 USBFSRST LL_APB1_GRP2_ReleaseReset\n
1220 * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
1221 * @param Periphs This parameter can be a combination of the following values:
1222 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1223 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1224 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
1225 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1226 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1227 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
1228 * @arg @ref LL_APB1_GRP2_PERIPH_USB
1229 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1230 * @retval None
1231 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1232 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1233 {
1234 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1235 }
1236
1237 /**
1238 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1239 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1240 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1241 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1242 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1243 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1244 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1245 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1246 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1247 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1248 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1249 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1250 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1251 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1252 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1253 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1254 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1255 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1256 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1257 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1258 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1259 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1260 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
1261 * @param Periphs This parameter can be a combination of the following values:
1262 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1263 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1264 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1265 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1266 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1267 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1268 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1269 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1270 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1271 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1272 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1273 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1274 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1275 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1276 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1277 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1278 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1279 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1280 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1281 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1282 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1283 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1284 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1285 * @retval None
1286 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)1287 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
1288 {
1289 __IO uint32_t tmpreg;
1290 SET_BIT(RCC->APB1SMENR1, Periphs);
1291 /* Delay after an RCC peripheral clock enabling */
1292 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1293 (void)tmpreg;
1294 }
1295
1296 /**
1297 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1298 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1299 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1300 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1301 * APB1SMENR2 LPTIM3SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1302 * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1303 * APB1SMENR2 USBFSSMEN LL_APB1_GRP2_EnableClockStopSleep\n
1304 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep
1305 * @param Periphs This parameter can be a combination of the following values:
1306 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1307 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1308 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
1309 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1310 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1311 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
1312 * @arg @ref LL_APB1_GRP2_PERIPH_USB
1313 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1314 * @retval None
1315 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)1316 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1317 {
1318 __IO uint32_t tmpreg;
1319 SET_BIT(RCC->APB1SMENR2, Periphs);
1320 /* Delay after an RCC peripheral clock enabling */
1321 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1322 (void)tmpreg;
1323 }
1324
1325 /**
1326 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1327 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1328 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1329 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1330 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1331 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1332 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1333 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1334 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1335 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1336 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1337 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1338 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1339 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1340 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1341 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1342 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1343 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1344 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1345 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1346 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1347 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1348 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
1349 * @param Periphs This parameter can be a combination of the following values:
1350 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1351 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1352 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1353 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1354 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1355 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1356 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1357 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1358 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1359 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1360 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1361 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1362 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1363 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1364 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1365 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1366 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1367 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1368 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1369 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1370 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1371 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1372 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1373 * @retval None
1374 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)1375 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
1376 {
1377 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1378 }
1379
1380 /**
1381 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1382 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1383 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1384 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1385 * APB1SMENR2 LPTIM3SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1386 * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1387 * APB1SMENR2 USBFSSMEN LL_APB1_GRP2_DisableClockStopSleep\n
1388 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
1389 * @param Periphs This parameter can be a combination of the following values:
1390 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1391 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1392 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4
1393 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1394 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1395 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
1396 * @arg @ref LL_APB1_GRP2_PERIPH_USB
1397 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1398 * @retval None
1399 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)1400 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1401 {
1402 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1403 }
1404
1405 /**
1406 * @}
1407 */
1408
1409 /** @defgroup BUS_LL_EF_APB2 APB2
1410 * @{
1411 */
1412
1413 /**
1414 * @brief Enable APB2 peripherals clock.
1415 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1416 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1417 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1418 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1419 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1420 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
1421 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1422 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1423 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1424 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1425 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock
1426 * @param Periphs This parameter can be a combination of the following values:
1427 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1428 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1429 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1430 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1431 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1432 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1433 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1434 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1435 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1436 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1437 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1438 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
1439 * @retval None
1440 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1441 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1442 {
1443 __IO uint32_t tmpreg;
1444 SET_BIT(RCC->APB2ENR, Periphs);
1445 /* Delay after an RCC peripheral clock enabling */
1446 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1447 (void)tmpreg;
1448 }
1449
1450 /**
1451 * @brief Check if APB2 peripheral clock is enabled or not
1452 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1453 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1454 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1455 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1456 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1457 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
1458 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1459 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1460 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1461 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1462 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock
1463 * @param Periphs This parameter can be a combination of the following values:
1464 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1465 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1466 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1467 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1468 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1469 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1470 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1471 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1472 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1473 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1474 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
1475 * @retval State of Periphs (1 or 0).
1476 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1477 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1478 {
1479 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1480 }
1481
1482 /**
1483 * @brief Disable APB2 peripherals clock.
1484 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1485 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1486 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1487 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1488 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1489 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
1490 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1491 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1492 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1493 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1494 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock
1495 * @param Periphs This parameter can be a combination of the following values:
1496 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1497 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1498 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1499 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1500 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1501 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1502 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1503 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1504 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1505 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1506 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1507 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
1508 * @retval None
1509 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1510 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1511 {
1512 CLEAR_BIT(RCC->APB2ENR, Periphs);
1513 }
1514
1515 /**
1516 * @brief Force APB2 peripherals reset.
1517 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1518 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1519 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1520 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1521 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1522 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
1523 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1524 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1525 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1526 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1527 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset
1528 * @param Periphs This parameter can be a combination of the following values:
1529 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1530 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1531 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1532 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1533 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1534 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1535 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1536 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1537 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1538 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1539 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1540 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
1541 * @retval None
1542 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1543 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1544 {
1545 SET_BIT(RCC->APB2RSTR, Periphs);
1546 }
1547
1548 /**
1549 * @brief Release APB2 peripherals reset.
1550 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1551 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1552 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1553 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1554 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1555 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
1556 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1557 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1558 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1559 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1560 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset
1561 * @param Periphs This parameter can be a combination of the following values:
1562 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1563 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1564 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1565 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1566 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1567 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1568 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1569 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1570 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1571 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1572 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1573 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
1574 * @retval None
1575 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1576 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1577 {
1578 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1579 }
1580
1581 /**
1582 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1583 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1584 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1585 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1586 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1587 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1588 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1589 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1590 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1591 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1592 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1593 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep
1594 * @param Periphs This parameter can be a combination of the following values:
1595 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1596 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1597 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1598 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1599 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1600 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1601 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1602 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1603 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1604 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1605 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1606 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
1607 * @retval None
1608 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1609 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1610 {
1611 __IO uint32_t tmpreg;
1612 SET_BIT(RCC->APB2SMENR, Periphs);
1613 /* Delay after an RCC peripheral clock enabling */
1614 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1615 (void)tmpreg;
1616 }
1617
1618 /**
1619 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1620 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1621 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1622 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1623 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1624 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1625 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1626 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1627 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1628 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1629 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1630 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep
1631 * @param Periphs This parameter can be a combination of the following values:
1632 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1633 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1634 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1635 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1636 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1637 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1638 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1639 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1640 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1641 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1642 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1643 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
1644 * @retval None
1645 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1646 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1647 {
1648 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1649 }
1650
1651 /**
1652 * @}
1653 */
1654
1655
1656 /**
1657 * @}
1658 */
1659
1660 /**
1661 * @}
1662 */
1663
1664 #endif /* defined(RCC) */
1665
1666 /**
1667 * @}
1668 */
1669
1670 #ifdef __cplusplus
1671 }
1672 #endif
1673
1674 #endif /* STM32L5xx_LL_BUS_H */
1675
1676
