1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ##### RCC Limitations #####
19 ==============================================================================
20 [..]
21 A delay between an RCC peripheral clock enable and the effective peripheral
22 enabling should be taken into account in order to manage the peripheral read/write
23 from/to registers.
24 (+) This delay depends on the peripheral mapping.
25 (++) AHB & APB peripherals, 1 dummy read is necessary
26
27 [..]
28 Workarounds:
29 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
30 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
31
32 @endverbatim
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32WBxx_LL_BUS_H
38 #define STM32WBxx_LL_BUS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32wbxx.h"
46
47 /** @addtogroup STM32WBxx_LL_Driver
48 * @{
49 */
50
51 #if defined(RCC)
52
53 /** @defgroup BUS_LL BUS
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61
62 /* Private macros ------------------------------------------------------------*/
63
64 /* Exported types ------------------------------------------------------------*/
65
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
68 * @{
69 */
70
71 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
72 * @{
73 */
74 #define LL_AHB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
75
76 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
77 #if defined(DMA2)
78 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
79 #endif /* DMA2 */
80 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
81 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
82 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
83 #if defined(TSC)
84 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
85 #endif /* TSC */
86 /**
87 * @}
88 */
89
90 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
91 * @{
92 */
93 #define LL_AHB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
94
95 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
96 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
97 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
98 #if defined(GPIOD)
99 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
100 #endif /* GPIOD */
101 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
102 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
103 #if defined(ADC_SUPPORT_5_MSPS)
104 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
105 #endif /* ADC_SUPPORT_5_MSPS */
106 #if defined(AES1)
107 #define LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN
108 #endif /* AES1 */
109 /**
110 * @}
111 */
112
113 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
114 * @{
115 */
116 #define LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
117 #if defined(QUADSPI)
118 #define LL_AHB3_GRP1_PERIPH_QUADSPI RCC_AHB3ENR_QUADSPIEN
119 #endif /* QUADSPI */
120 #define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN
121 #define LL_AHB3_GRP1_PERIPH_AES2 RCC_AHB3ENR_AES2EN
122 #define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN
123 #define LL_AHB3_GRP1_PERIPH_HSEM RCC_AHB3ENR_HSEMEN
124 #define LL_AHB3_GRP1_PERIPH_IPCC RCC_AHB3ENR_IPCCEN
125 #define LL_AHB3_GRP1_PERIPH_SRAM2 RCC_AHB3SMENR_SRAM2SMEN
126 #define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3ENR_FLASHEN
127 /**
128 * @}
129 */
130
131 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
132 * @{
133 */
134 #define LL_APB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
135 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
136 #if defined(LCD)
137 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
138 #endif /* LCD */
139 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
140 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
141 #if defined(SPI2)
142 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
143 #endif /* SPI2 */
144 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
145 #if defined(I2C3)
146 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
147 #endif /* I2C3 */
148 #if defined(CRS)
149 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
150 #endif /* CRS */
151 #if defined(USB)
152 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
153 #endif /* USB */
154 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
155 /**
156 * @}
157 */
158
159
160 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
161 * @{
162 */
163 #define LL_APB1_GRP2_PERIPH_ALL (0xFFFFFFFFU)
164
165 #if defined(LPUART1)
166 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
167 #endif /* LPUART1 */
168 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
169 /**
170 * @}
171 */
172
173 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
174 * @{
175 */
176 #define LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
177
178 #if defined(ADC_SUPPORT_2_5_MSPS)
179 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2ENR_ADCEN
180 #endif /* ADC_SUPPORT_2_5_MSPS */
181 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
182 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
183 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
184 #if defined(TIM16)
185 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
186 #endif /* TIM16 */
187 #if defined(TIM17)
188 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
189 #endif /* TIM17 */
190 #if defined(SAI1)
191 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
192 #endif /* SAI1 */
193 /**
194 * @}
195 */
196
197 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
198 * @{
199 */
200 #define LL_APB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
201 #define LL_APB3_GRP1_PERIPH_RF RCC_APB3RSTR_RFRST
202 /**
203 * @}
204 */
205
206
207 /** @defgroup BUS_LL_EC_C2_AHB1_GRP1_PERIPH C2 AHB1 GRP1 PERIPH
208 * @{
209 */
210 #define LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN
211 #if defined(DMA2)
212 #define LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN
213 #endif /* DMA2 */
214 #define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN
215 #define LL_C2_AHB1_GRP1_PERIPH_SRAM1 RCC_C2AHB1ENR_SRAM1EN
216 #define LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN
217 #if defined(TSC)
218 #define LL_C2_AHB1_GRP1_PERIPH_TSC RCC_C2AHB1ENR_TSCEN
219 #endif /* TSC */
220 /**
221 * @}
222 */
223
224
225 /** @defgroup BUS_LL_EC_C2_AHB2_GRP1_PERIPH C2 AHB2 GRP1 PERIPH
226 * @{
227 */
228 #define LL_C2_AHB2_GRP1_PERIPH_GPIOA RCC_C2AHB2ENR_GPIOAEN
229 #define LL_C2_AHB2_GRP1_PERIPH_GPIOB RCC_C2AHB2ENR_GPIOBEN
230 #define LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN
231 #if defined(GPIOD)
232 #define LL_C2_AHB2_GRP1_PERIPH_GPIOD RCC_C2AHB2ENR_GPIODEN
233 #endif /* GPIOD */
234 #define LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN
235 #define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN
236 #if defined(ADC_SUPPORT_5_MSPS)
237 #define LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN
238 #endif /* ADC_SUPPORT_5_MSPS */
239 #if defined(AES1)
240 #define LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN
241 #endif /* AES1 */
242 /**
243 * @}
244 */
245
246
247 /** @defgroup BUS_LL_EC_C2_AHB3_GRP1_PERIPH C2 AHB3 GRP1 PERIPH
248 * @{
249 */
250 #define LL_C2_AHB3_GRP1_PERIPH_PKA RCC_C2AHB3ENR_PKAEN
251 #define LL_C2_AHB3_GRP1_PERIPH_AES2 RCC_C2AHB3ENR_AES2EN
252 #define LL_C2_AHB3_GRP1_PERIPH_RNG RCC_C2AHB3ENR_RNGEN
253 #define LL_C2_AHB3_GRP1_PERIPH_HSEM RCC_C2AHB3ENR_HSEMEN
254 #define LL_C2_AHB3_GRP1_PERIPH_IPCC RCC_C2AHB3ENR_IPCCEN
255 #define LL_C2_AHB3_GRP1_PERIPH_FLASH RCC_C2AHB3ENR_FLASHEN
256 #define LL_C2_AHB3_GRP1_PERIPH_SRAM2 RCC_C2AHB3SMENR_SRAM2SMEN
257 /**
258 * @}
259 */
260
261
262 /** @defgroup BUS_LL_EC_C2_APB1_GRP1_PERIPH C2 APB1 GRP1 PERIPH
263 * @{
264 */
265 #define LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN
266 #if defined(LCD)
267 #define LL_C2_APB1_GRP1_PERIPH_LCD RCC_C2APB1ENR1_LCDEN
268 #endif /* LCD */
269 #define LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN
270 #if defined(SPI2)
271 #define LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN
272 #endif /* SPI2 */
273 #define LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN
274 #if defined(I2C3)
275 #define LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN
276 #define LL_C2_APB1_GRP1_PERIPH_CRS RCC_C2APB1ENR1_CRSEN
277 #define LL_C2_APB1_GRP1_PERIPH_USB RCC_C2APB1ENR1_USBEN
278 #endif /* I2C3 */
279 #define LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN
280 /**
281 * @}
282 */
283
284
285 /** @defgroup BUS_LL_EC_C2_APB1_GRP2_PERIPH C2 APB1 GRP2 PERIPH
286 * @{
287 */
288 #if defined(LPUART1)
289 #define LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN
290 #endif /* LPUART1 */
291 #define LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN
292 /**
293 * @}
294 */
295
296
297 /** @defgroup BUS_LL_EC_C2_APB2_GRP1_PERIPH C2 APB2 GRP1 PERIPH
298 * @{
299 */
300 #if defined(ADC_SUPPORT_2_5_MSPS)
301 #define LL_C2_APB2_GRP1_PERIPH_ADC RCC_C2APB2ENR_ADCEN
302 #endif /* ADC_SUPPORT_5_MSPS */
303 #define LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN
304 #define LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN
305 #define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN
306 #if defined(TIM16)
307 #define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN
308 #endif /* TIM16 */
309 #if defined(TIM17)
310 #define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN
311 #endif /* TIM17 */
312 #if defined(SAI1)
313 #define LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN
314 #endif /* SAI1 */
315 /**
316 * @}
317 */
318
319
320 /** @defgroup BUS_LL_EC_C2_APB3_GRP1_PERIPH C2 APB3 GRP1 PERIPH
321 * @{
322 */
323 #define LL_C2_APB3_GRP1_PERIPH_BLE RCC_C2APB3ENR_BLEEN
324 #if defined(RCC_802_SUPPORT)
325 #define LL_C2_APB3_GRP1_PERIPH_802 RCC_C2APB3ENR_802EN
326 #endif /* RCC_802_SUPPORT */
327 /**
328 * @}
329 */
330
331
332 /**
333 * @}
334 */
335
336 /* Exported macro ------------------------------------------------------------*/
337
338 /* Exported functions --------------------------------------------------------*/
339
340 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
341 * @{
342 */
343
344 /** @defgroup BUS_LL_EF_AHB1 AHB1
345 * @{
346 */
347
348 /**
349 * @brief Enable AHB1 peripherals clock.
350 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
351 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
352 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
353 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
354 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
355 * @param Periphs This parameter can be a combination of the following values:
356 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
357 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
358 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
359 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
360 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
361 * @note (*) Not supported by all the devices
362 * @retval None
363 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)364 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
365 {
366 __IO uint32_t tmpreg;
367 SET_BIT(RCC->AHB1ENR, Periphs);
368 /* Delay after an RCC peripheral clock enabling */
369 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
370 (void)tmpreg;
371 }
372
373 /**
374 * @brief Check if AHB1 peripheral clock is enabled or not
375 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
376 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
377 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
378 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
379 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
380 * @param Periphs This parameter can be a combination of the following values:
381 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
382 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
383 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
384 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
385 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
386 * @note (*) Not supported by all the devices
387 * @retval uint32_t
388 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)389 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
390 {
391 return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
392 }
393
394 /**
395 * @brief Disable AHB1 peripherals clock.
396 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
397 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
398 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
399 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
400 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
401 * @param Periphs This parameter can be a combination of the following values:
402 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
403 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
404 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
405 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
406 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
407 * @note (*) Not supported by all the devices
408 * @retval None
409 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)410 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
411 {
412 CLEAR_BIT(RCC->AHB1ENR, Periphs);
413 }
414
415 /**
416 * @brief Force AHB1 peripherals reset.
417 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
418 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
419 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
420 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
421 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
422 * @param Periphs This parameter can be a combination of the following values:
423 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
424 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
425 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
426 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
427 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
428 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
429 * @note (*) Not supported by all the devices
430 * @retval None
431 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)432 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
433 {
434 SET_BIT(RCC->AHB1RSTR, Periphs);
435 }
436
437 /**
438 * @brief Release AHB1 peripherals reset.
439 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
440 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
441 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
442 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
443 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
444 * @param Periphs This parameter can be a combination of the following values:
445 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
446 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
447 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
448 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
449 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
450 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
451 * @note (*) Not supported by all the devices
452 * @retval None
453 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)454 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
455 {
456 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
457 }
458
459 /**
460 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
461 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockSleep\n
462 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockSleep\n
463 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockSleep\n
464 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockSleep\n
465 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n
466 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep
467 * @param Periphs This parameter can be a combination of the following values:
468 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
469 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
470 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
471 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
472 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
473 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
474 * @note (*) Not supported by all the devices
475 * @retval None
476 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)477 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
478 {
479 __IO uint32_t tmpreg;
480 SET_BIT(RCC->AHB1SMENR, Periphs);
481 /* Delay after an RCC peripheral clock enabling */
482 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
483 (void)tmpreg;
484 }
485
486 /**
487 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
488 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockSleep\n
489 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockSleep\n
490 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockSleep\n
491 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockSleep\n
492 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n
493 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep
494 * @param Periphs This parameter can be a combination of the following values:
495 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
496 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
497 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
498 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
499 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
500 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
501 * @note (*) Not supported by all the devices
502 * @retval None
503 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)504 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
505 {
506 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
507 }
508
509 /**
510 * @}
511 */
512
513 /** @defgroup BUS_LL_EF_AHB2 AHB2
514 * @{
515 */
516
517 /**
518 * @brief Enable AHB2 peripherals clock.
519 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
520 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
521 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
522 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
523 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
524 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
525 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
526 * AHB2ENR AES1EN LL_AHB2_GRP1_EnableClock
527 * @param Periphs This parameter can be a combination of the following values:
528 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
529 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
530 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
531 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
532 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
533 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
534 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
535 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
536 * @note (*) Not supported by all the devices
537 * @retval None
538 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)539 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
540 {
541 __IO uint32_t tmpreg;
542 SET_BIT(RCC->AHB2ENR, Periphs);
543 /* Delay after an RCC peripheral clock enabling */
544 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
545 (void)tmpreg;
546 }
547
548 /**
549 * @brief Check if AHB2 peripheral clock is enabled or not
550 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
551 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
552 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
553 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
554 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
555 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
556 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
557 * AHB2ENR AES1EN LL_AHB2_GRP1_IsEnabledClock
558 * @param Periphs This parameter can be a combination of the following values:
559 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
560 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
561 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
562 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
563 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
564 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
565 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
566 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
567 * @note (*) Not supported by all the devices
568 * @retval uint32_t
569 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)570 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
571 {
572 return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
573 }
574
575 /**
576 * @brief Disable AHB2 peripherals clock.
577 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
578 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
579 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
580 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
581 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
582 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
583 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
584 * AHB2ENR AES1EN LL_AHB2_GRP1_DisableClock
585 * @param Periphs This parameter can be a combination of the following values:
586 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
587 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
588 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
589 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
590 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
591 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
592 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
593 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
594 * @note (*) Not supported by all the devices
595 * @retval None
596 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)597 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
598 {
599 CLEAR_BIT(RCC->AHB2ENR, Periphs);
600 }
601
602 /**
603 * @brief Force AHB2 peripherals reset.
604 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
605 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
606 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
607 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
608 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
609 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
610 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
611 * AHB2RSTR AES1RST LL_AHB2_GRP1_ForceReset
612 * @param Periphs This parameter can be a combination of the following values:
613 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
614 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
615 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
616 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
617 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
618 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
619 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
620 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
621 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
622 * @note (*) Not supported by all the devices
623 * @retval None
624 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)625 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
626 {
627 SET_BIT(RCC->AHB2RSTR, Periphs);
628 }
629
630 /**
631 * @brief Release AHB2 peripherals reset.
632 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
633 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
634 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
635 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
636 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
637 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
638 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
639 * AHB2RSTR AES1RST LL_AHB2_GRP1_ReleaseReset
640 * @param Periphs This parameter can be a combination of the following values:
641 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
642 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
643 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
644 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
645 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
646 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
647 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
648 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
649 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
650 * @note (*) Not supported by all the devices
651 * @retval None
652 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)653 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
654 {
655 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
656 }
657
658 /**
659 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
660 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockSleep\n
661 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockSleep\n
662 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockSleep\n
663 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockSleep\n
664 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockSleep\n
665 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockSleep\n
666 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockSleep\n
667 * AHB2SMENR AES1SMEN LL_AHB2_GRP1_EnableClockSleep
668 * @param Periphs This parameter can be a combination of the following values:
669 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
670 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
671 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
672 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
673 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
674 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
675 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
676 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
677 * @note (*) Not supported by all the devices
678 * @retval None
679 */
LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)680 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
681 {
682 __IO uint32_t tmpreg;
683 SET_BIT(RCC->AHB2SMENR, Periphs);
684 /* Delay after an RCC peripheral clock enabling */
685 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
686 (void)tmpreg;
687 }
688
689 /**
690 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode.
691 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockSleep\n
692 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockSleep\n
693 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockSleep\n
694 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockSleep\n
695 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockSleep\n
696 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockSleep\n
697 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockSleep\n
698 * AHB2SMENR AES1SMEN LL_AHB2_GRP1_DisableClockSleep
699 * @param Periphs This parameter can be a combination of the following values:
700 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
701 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
702 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
703 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
704 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
705 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
706 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC (*)
707 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
708 * @note (*) Not supported by all the devices
709 * @retval None
710 */
LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)711 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
712 {
713 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
714 }
715
716 /**
717 * @}
718 */
719
720 /** @defgroup BUS_LL_EF_AHB3 AHB3
721 * @{
722 */
723
724 /**
725 * @brief Enable AHB3 peripherals clock.
726 * @rmtoll AHB3ENR QUADSPIEN LL_AHB3_GRP1_EnableClock\n
727 * AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock\n
728 * AHB3ENR AES2EN LL_AHB3_GRP1_EnableClock\n
729 * AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock\n
730 * AHB3ENR HSEMEN LL_AHB3_GRP1_EnableClock\n
731 * AHB3ENR IPCCEN LL_AHB3_GRP1_EnableClock\n
732 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock
733 * @param Periphs This parameter can be a combination of the following values:
734 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
735 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
736 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
737 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
738 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
739 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
740 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
741 * @note (*) Not supported by all the devices
742 * @retval None
743 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)744 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
745 {
746 __IO uint32_t tmpreg;
747 SET_BIT(RCC->AHB3ENR, Periphs);
748 /* Delay after an RCC peripheral clock enabling */
749 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
750 (void)tmpreg;
751 }
752
753 /**
754 * @brief Check if AHB3 peripheral clock is enabled or not
755 * @rmtoll AHB3ENR QUADSPIEN LL_AHB3_GRP1_IsEnabledClock\n
756 * AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock\n
757 * AHB3ENR AES2EN LL_AHB3_GRP1_IsEnabledClock\n
758 * AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n
759 * AHB3ENR HSEMEN LL_AHB3_GRP1_IsEnabledClock\n
760 * AHB3ENR IPCCEN LL_AHB3_GRP1_IsEnabledClock\n
761 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock
762 * @param Periphs This parameter can be a combination of the following values:
763 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
764 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
765 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
766 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
767 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
768 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
769 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
770 * @note (*) Not supported by all the devices
771 * @retval uint32_t
772 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)773 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
774 {
775 return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
776 }
777
778 /**
779 * @brief Disable AHB3 peripherals clock.
780 * @rmtoll AHB3ENR QUADSPIEN LL_AHB3_GRP1_DisableClock\n
781 * AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock\n
782 * AHB3ENR AES2EN LL_AHB3_GRP1_DisableClock\n
783 * AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock\n
784 * AHB3ENR HSEMEN LL_AHB3_GRP1_DisableClock\n
785 * AHB3ENR IPCCEN LL_AHB3_GRP1_DisableClock\n
786 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock
787 * @param Periphs This parameter can be a combination of the following values:
788 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
789 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
790 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
791 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
792 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
793 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
794 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
795 * @note (*) Not supported by all the devices
796 * @retval None
797 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)798 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
799 {
800 CLEAR_BIT(RCC->AHB3ENR, Periphs);
801 }
802
803 /**
804 * @brief Force AHB3 peripherals reset.
805 * @rmtoll AHB3RSTR QUADSPIRST LL_AHB3_GRP1_ForceReset\n
806 * AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset\n
807 * AHB3RSTR AES2RST LL_AHB3_GRP1_ForceReset\n
808 * AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset\n
809 * AHB3RSTR HSEMRST LL_AHB3_GRP1_ForceReset\n
810 * AHB3RSTR IPCCRST LL_AHB3_GRP1_ForceReset\n
811 * AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset
812 * @param Periphs This parameter can be a combination of the following values:
813 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
814 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
815 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
816 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
817 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
818 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
819 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
820 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
821 * @note (*) Not supported by all the devices
822 * @retval None
823 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)824 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
825 {
826 SET_BIT(RCC->AHB3RSTR, Periphs);
827 }
828
829 /**
830 * @brief Release AHB3 peripherals reset.
831 * @rmtoll AHB3RSTR QUADSPIRST LL_AHB3_GRP1_ReleaseReset\n
832 * AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset\n
833 * AHB3RSTR AES2RST LL_AHB3_GRP1_ReleaseReset\n
834 * AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset\n
835 * AHB3RSTR HSEMRST LL_AHB3_GRP1_ReleaseReset\n
836 * AHB3RSTR IPCCRST LL_AHB3_GRP1_ReleaseReset\n
837 * AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset
838 * @param Periphs This parameter can be a combination of the following values:
839 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
840 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
841 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
842 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
843 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
844 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
845 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
846 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
847 * @note (*) Not supported by all the devices
848 * @retval None
849 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)850 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
851 {
852 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
853 }
854
855 /**
856 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode.
857 * @rmtoll AHB3SMENR QUADSPISMEN LL_AHB3_GRP1_EnableClockSleep\n
858 * AHB3SMENR PKASMEN LL_AHB3_GRP1_EnableClockSleep\n
859 * AHB3SMENR AES2SMEN LL_AHB3_GRP1_EnableClockSleep\n
860 * AHB3SMENR RNGSMEN LL_AHB3_GRP1_EnableClockSleep\n
861 * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_EnableClockSleep\n
862 * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_EnableClockSleep
863 * @param Periphs This parameter can be a combination of the following values:
864 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
865 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
866 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
867 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
868 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
869 * @note (*) Not supported by all the devices
870 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
871 * @retval None
872 */
LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)873 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
874 {
875 __IO uint32_t tmpreg;
876 SET_BIT(RCC->AHB3SMENR, Periphs);
877 /* Delay after an RCC peripheral clock enabling */
878 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
879 (void)tmpreg;
880 }
881
882 /**
883 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode.
884 * @rmtoll AHB3SMENR QUADSPISMEN LL_AHB3_GRP1_DisableClockSleep\n
885 * AHB3SMENR PKASMEN LL_AHB3_GRP1_DisableClockSleep\n
886 * AHB3SMENR AES2SMEN LL_AHB3_GRP1_DisableClockSleep\n
887 * AHB3SMENR RNGSMEN LL_AHB3_GRP1_DisableClockSleep\n
888 * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_DisableClockSleep\n
889 * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_DisableClockSleep
890 * @param Periphs This parameter can be a combination of the following values:
891 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI (*)
892 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
893 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
894 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
895 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
896 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
897 * @note (*) Not supported by all the devices
898 * @retval None
899 */
LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)900 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
901 {
902 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
903 }
904
905 /**
906 * @}
907 */
908
909 /** @defgroup BUS_LL_EF_APB1 APB1
910 * @{
911 */
912
913 /**
914 * @brief Enable APB1 peripherals clock.
915 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
916 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
917 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
918 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
919 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
920 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
921 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
922 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
923 * APB1ENR1 USBEN LL_APB1_GRP1_EnableClock\n
924 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
925 * @param Periphs This parameter can be a combination of the following values:
926 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
927 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
928 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
929 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
930 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
931 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
932 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
933 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
934 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
935 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
936 * @note (*) Not supported by all the devices
937 * @retval None
938 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)939 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
940 {
941 __IO uint32_t tmpreg;
942 SET_BIT(RCC->APB1ENR1, Periphs);
943 /* Delay after an RCC peripheral clock enabling */
944 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
945 (void)tmpreg;
946 }
947
948 /**
949 * @brief Enable APB1 peripherals clock.
950 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
951 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
952 * @param Periphs This parameter can be a combination of the following values:
953 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
954 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
955 * @note (*) Not supported by all the devices
956 * @retval None
957 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)958 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
959 {
960 __IO uint32_t tmpreg;
961 SET_BIT(RCC->APB1ENR2, Periphs);
962 /* Delay after an RCC peripheral clock enabling */
963 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
964 (void)tmpreg;
965 }
966
967 /**
968 * @brief Check if APB1 peripheral clock is enabled or not
969 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
970 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
971 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
972 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
973 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
974 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
975 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
976 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
977 * APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
978 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
979 * @param Periphs This parameter can be a combination of the following values:
980 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
981 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
982 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
983 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
984 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
985 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
986 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
987 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
988 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
989 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
990 * @note (*) Not supported by all the devices
991 * @retval uint32_t
992 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)993 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
994 {
995 return ((READ_BIT(RCC->APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
996 }
997
998 /**
999 * @brief Check if APB1 peripheral clock is enabled or not
1000 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
1001 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
1002 * @param Periphs This parameter can be a combination of the following values:
1003 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
1004 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1005 * @note (*) Not supported by all the devices
1006 * @retval uint32_t
1007 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1008 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1009 {
1010 return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
1011 }
1012
1013 /**
1014 * @brief Disable APB1 peripherals clock.
1015 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1016 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
1017 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
1018 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1019 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1020 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1021 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
1022 * APB1ENR1 USBEN LL_APB1_GRP1_DisableClock\n
1023 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
1024 * @param Periphs This parameter can be a combination of the following values:
1025 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1026 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1027 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1028 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1029 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1030 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1031 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1032 * @arg @ref LL_APB1_GRP1_PERIPH_ (*)
1033 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1034 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1035 * @note (*) Not supported by all the devices
1036 * @retval None
1037 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1038 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1039 {
1040 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1041 }
1042
1043 /**
1044 * @brief Disable APB1 peripherals clock.
1045 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
1046 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
1047 * @param Periphs This parameter can be a combination of the following values:
1048 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
1049 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1050 * @note (*) Not supported by all the devices
1051 * @retval None
1052 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1053 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1054 {
1055 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1056 }
1057
1058 /**
1059 * @brief Force APB1 peripherals reset.
1060 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1061 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
1062 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1063 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1064 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1065 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
1066 * APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset\n
1067 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1068 * @param Periphs This parameter can be a combination of the following values:
1069 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1070 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1071 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1072 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1073 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1074 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1075 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1076 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1077 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1078 * @note (*) Not supported by all the devices
1079 * @retval None
1080 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1081 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1082 {
1083 SET_BIT(RCC->APB1RSTR1, Periphs);
1084 }
1085
1086 /**
1087 * @brief Force APB1 peripherals reset.
1088 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1089 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
1090 * @param Periphs This parameter can be a combination of the following values:
1091 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1092 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
1093 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1094 * @note (*) Not supported by all the devices
1095 * @retval None
1096 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1097 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1098 {
1099 SET_BIT(RCC->APB1RSTR2, Periphs);
1100 }
1101
1102 /**
1103 * @brief Release APB1 peripherals reset.
1104 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1105 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
1106 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1107 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1108 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1109 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
1110 * APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
1111 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1112 * @param Periphs This parameter can be a combination of the following values:
1113 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1114 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1115 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1116 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1117 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1118 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1119 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1120 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1121 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1122 * @note (*) Not supported by all the devices
1123 * @retval None
1124 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1125 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1126 {
1127 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1128 }
1129
1130 /**
1131 * @brief Release APB1 peripherals reset.
1132 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1133 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
1134 * @param Periphs This parameter can be a combination of the following values:
1135 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1136 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
1137 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1138 * @note (*) Not supported by all the devices
1139 * @retval None
1140 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1141 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1142 {
1143 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1144 }
1145
1146 /**
1147 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
1148 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n
1149 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockSleep\n
1150 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockSleep\n
1151 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n
1152 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n
1153 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n
1154 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n
1155 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockSleep\n
1156 * APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockSleep\n
1157 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep
1158 * @param Periphs This parameter can be a combination of the following values:
1159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1160 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1161 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1162 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1163 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1164 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1165 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1166 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1167 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1168 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1169 * @note (*) Not supported by all the devices
1170 * @retval None
1171 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)1172 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
1173 {
1174 __IO uint32_t tmpreg;
1175 SET_BIT(RCC->APB1SMENR1, Periphs);
1176 /* Delay after an RCC peripheral clock enabling */
1177 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1178 (void)tmpreg;
1179 }
1180
1181 /**
1182 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
1183 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockSleep\n
1184 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockSleep
1185 * @param Periphs This parameter can be a combination of the following values:
1186 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
1187 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1188 * @note (*) Not supported by all the devices
1189 * @retval None
1190 */
LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)1191 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
1192 {
1193 __IO uint32_t tmpreg;
1194 SET_BIT(RCC->APB1SMENR2, Periphs);
1195 /* Delay after an RCC peripheral clock enabling */
1196 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1197 (void)tmpreg;
1198 }
1199
1200 /**
1201 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
1202 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n
1203 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockSleep\n
1204 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockSleep\n
1205 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n
1206 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n
1207 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n
1208 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n
1209 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockSleep\n
1210 * APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockSleep\n
1211 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep
1212 * @param Periphs This parameter can be a combination of the following values:
1213 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1214 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1215 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1216 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1217 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1218 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1219 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1220 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1221 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1222 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1223 * @note (*) Not supported by all the devices
1224 * @retval None
1225 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)1226 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
1227 {
1228 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1229 }
1230
1231 /**
1232 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
1233 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockSleep\n
1234 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockSleep
1235 * @param Periphs This parameter can be a combination of the following values:
1236 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 (*)
1237 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1238 * @note (*) Not supported by all the devices
1239 * @retval None
1240 */
LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)1241 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
1242 {
1243 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1244 }
1245
1246 /**
1247 * @}
1248 */
1249
1250 /** @defgroup BUS_LL_EF_APB2 APB2
1251 * @{
1252 */
1253
1254 /**
1255 * @brief Enable APB2 peripherals clock.
1256 * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n
1257 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1258 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1259 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1260 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1261 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1262 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
1263 * @param Periphs This parameter can be a combination of the following values:
1264 * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
1265 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1266 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1267 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1268 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
1269 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1270 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1271 * @note (*) Not supported by all the devices
1272 * @retval None
1273 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1274 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1275 {
1276 __IO uint32_t tmpreg;
1277 SET_BIT(RCC->APB2ENR, Periphs);
1278 /* Delay after an RCC peripheral clock enabling */
1279 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1280 (void)tmpreg;
1281 }
1282
1283 /**
1284 * @brief Check if APB2 peripheral clock is enabled or not
1285 * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n
1286 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1287 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1288 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1289 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1290 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1291 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
1292 * @param Periphs This parameter can be a combination of the following values:
1293 * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
1294 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1295 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1296 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1297 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
1298 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1299 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1300 * @note (*) Not supported by all the devices
1301 * @retval uint32_t
1302 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1303 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1304 {
1305 return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1306 }
1307
1308 /**
1309 * @brief Disable APB2 peripherals clock.
1310 * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n
1311 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1312 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1313 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1314 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1315 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1316 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
1317 * @param Periphs This parameter can be a combination of the following values:
1318 * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
1319 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1320 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1321 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1322 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
1323 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1324 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1325 * @note (*) Not supported by all the devices
1326 * @retval None
1327 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1328 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1329 {
1330 CLEAR_BIT(RCC->APB2ENR, Periphs);
1331 }
1332
1333 /**
1334 * @brief Force APB2 peripherals reset.
1335 * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1336 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1337 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1338 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1339 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1340 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1341 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
1342 * @param Periphs This parameter can be a combination of the following values:
1343 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1344 * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
1345 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1346 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1347 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1348 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
1349 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1350 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1351 * @note (*) Not supported by all the devices
1352 * @retval None
1353 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1354 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1355 {
1356 SET_BIT(RCC->APB2RSTR, Periphs);
1357 }
1358
1359 /**
1360 * @brief Release APB2 peripherals reset.
1361 * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1362 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1363 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1364 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1365 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1366 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1367 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset
1368 * @param Periphs This parameter can be a combination of the following values:
1369 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1370 * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
1371 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1372 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1373 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1374 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
1375 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1376 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1377 * @note (*) Not supported by all the devices
1378 * @retval None
1379 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1380 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1381 {
1382 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1383 }
1384
1385 /**
1386 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
1387 * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n
1388 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep\n
1389 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n
1390 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n
1391 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockSleep\n
1392 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockSleep\n
1393 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockSleep
1394 * @param Periphs This parameter can be a combination of the following values:
1395 * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
1396 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1397 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1398 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1399 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
1400 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1401 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1402 * @note (*) Not supported by all the devices
1403 * @retval None
1404 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)1405 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
1406 {
1407 __IO uint32_t tmpreg;
1408 SET_BIT(RCC->APB2SMENR, Periphs);
1409 /* Delay after an RCC peripheral clock enabling */
1410 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1411 (void)tmpreg;
1412 }
1413
1414 /**
1415 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
1416 * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n
1417 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep\n
1418 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n
1419 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n
1420 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockSleep\n
1421 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockSleep\n
1422 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockSleep
1423 * @param Periphs This parameter can be a combination of the following values:
1424 * @arg @ref LL_APB2_GRP1_PERIPH_ADC (*)
1425 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1426 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1427 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1428 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
1429 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1430 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1431 * @note (*) Not supported by all the devices
1432 * @retval None
1433 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)1434 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
1435 {
1436 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1437 }
1438
1439 /**
1440 * @}
1441 */
1442
1443 /** @defgroup BUS_LL_EF_APB3 APB3
1444 * @{
1445 */
1446
1447 /**
1448 * @brief Force APB3 peripherals reset.
1449 * @rmtoll APB3RSTR RFRST LL_APB3_GRP1_ForceReset
1450 * @param Periphs This parameter can be a combination of the following values:
1451 * @arg @ref LL_APB3_GRP1_PERIPH_RF
1452 * @retval None
1453 */
LL_APB3_GRP1_ForceReset(uint32_t Periphs)1454 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
1455 {
1456 SET_BIT(RCC->APB3RSTR, Periphs);
1457 }
1458
1459 /**
1460 * @brief Release APB3 peripherals reset.
1461 * @rmtoll APB3RSTR RFRST LL_APB3_GRP1_ReleaseReset
1462 * @param Periphs This parameter can be a combination of the following values:
1463 * @arg @ref LL_APB3_GRP1_PERIPH_RF
1464 * @retval None
1465 */
LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)1466 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
1467 {
1468 CLEAR_BIT(RCC->APB3RSTR, Periphs);
1469 }
1470
1471 /**
1472 * @}
1473 */
1474
1475 /** @defgroup BUS_LL_EF_C2_AHB1 C2 AHB1
1476 * @{
1477 */
1478 /**
1479 * @brief Enable C2AHB1 peripherals clock.
1480 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n
1481 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n
1482 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_EnableClock\n
1483 * C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_EnableClock\n
1484 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_EnableClock\n
1485 * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_EnableClock
1486 * @param Periphs This parameter can be a combination of the following values:
1487 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1488 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
1489 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1490 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1491 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1492 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1493 * @note (*) Not supported by all the devices
1494 * @retval None
1495 */
1496
LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)1497 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
1498 {
1499 __IO uint32_t tmpreg;
1500 SET_BIT(RCC->C2AHB1ENR, Periphs);
1501 /* Delay after an RCC peripheral clock enabling */
1502 tmpreg = READ_BIT(RCC->C2AHB1ENR, Periphs);
1503 (void)tmpreg;
1504 }
1505
1506 /**
1507 * @brief Check if C2AHB1 peripheral clock is enabled or not
1508 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1509 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1510 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1511 * C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1512 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_IsEnabledClock\n
1513 * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_IsEnabledClock
1514 * @param Periphs This parameter can be a combination of the following values:
1515 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1516 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
1517 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1518 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1519 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1520 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1521 * @note (*) Not supported by all the devices
1522 * @retval uint32_t
1523 */
1524
LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)1525 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
1526 {
1527 return ((READ_BIT(RCC->C2AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1528 }
1529
1530 /**
1531 * @brief Disable C2AHB1 peripherals clock.
1532 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n
1533 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n
1534 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_DisableClock\n
1535 * C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_DisableClock\n
1536 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_DisableClock\n
1537 * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_DisableClock
1538 * @param Periphs This parameter can be a combination of the following values:
1539 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1540 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
1541 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1542 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1543 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1544 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1545 * @note (*) Not supported by all the devices
1546 * @retval None
1547 */
1548
LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)1549 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
1550 {
1551 CLEAR_BIT(RCC->C2AHB1ENR, Periphs);
1552 }
1553
1554 /**
1555 * @brief Enable C2AHB1 peripherals clock during Low Power (Sleep) mode.
1556 * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1557 * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1558 * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1559 * C2AHB1ENR SRAM1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1560 * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1561 * C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_EnableClockSleep
1562 * @param Periphs This parameter can be a combination of the following values:
1563 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1564 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
1565 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1566 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1567 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1568 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1569 * @note (*) Not supported by all the devices
1570 * @retval None
1571 */
1572
LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)1573 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
1574 {
1575 __IO uint32_t tmpreg;
1576 SET_BIT(RCC->C2AHB1SMENR, Periphs);
1577 /* Delay after an RCC peripheral clock enabling */
1578 tmpreg = READ_BIT(RCC->C2AHB1SMENR, Periphs);
1579 (void)tmpreg;
1580 }
1581
1582 /**
1583 * @brief Disable C2AHB1 peripherals clock during Low Power (Sleep) mode.
1584 * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1585 * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1586 * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1587 * C2AHB1ENR SRAM1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1588 * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1589 * C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_DisableClockSleep
1590 * @param Periphs This parameter can be a combination of the following values:
1591 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1592 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2 (*)
1593 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1594 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1595 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1596 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1597 * @note (*) Not supported by all the devices
1598 * @retval None
1599 */
1600
LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)1601 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
1602 {
1603 CLEAR_BIT(RCC->C2AHB1SMENR, Periphs);
1604 }
1605
1606 /**
1607 * @}
1608 */
1609
1610 /** @defgroup BUS_LL_EF_C2_AHB2 C2 AHB2
1611 * @{
1612 */
1613
1614 /**
1615 * @brief Enable C2AHB2 peripherals clock.
1616 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_EnableClock\n
1617 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_EnableClock\n
1618 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_EnableClock\n
1619 * C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_EnableClock\n
1620 * C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_EnableClock\n
1621 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_EnableClock\n
1622 * C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_EnableClock\n
1623 * C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_EnableClock
1624 * @param Periphs This parameter can be a combination of the following values:
1625 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1626 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1627 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1628 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
1629 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1630 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1631 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
1632 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
1633 * @note (*) Not supported by all the devices
1634 * @retval None
1635 */
LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)1636 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
1637 {
1638 __IO uint32_t tmpreg;
1639 SET_BIT(RCC->C2AHB2ENR, Periphs);
1640 /* Delay after an RCC peripheral clock enabling */
1641 tmpreg = READ_BIT(RCC->C2AHB2ENR, Periphs);
1642 (void)tmpreg;
1643 }
1644
1645 /**
1646 * @brief Check if C2AHB2 peripheral clock is enabled or not
1647 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1648 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1649 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1650 * C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1651 * C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1652 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1653 * C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1654 * C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_IsEnabledClock
1655 * @param Periphs This parameter can be a combination of the following values:
1656 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1657 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1658 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1659 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
1660 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1661 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1662 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
1663 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
1664 * @note (*) Not supported by all the devices
1665 * @retval uint32_t
1666 */
LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)1667 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
1668 {
1669 return ((READ_BIT(RCC->C2AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1670 }
1671
1672 /**
1673 * @brief Disable C2AHB2 peripherals clock.
1674 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_DisableClock\n
1675 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_DisableClock\n
1676 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_DisableClock\n
1677 * C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_DisableClock\n
1678 * C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_DisableClock\n
1679 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_DisableClock\n
1680 * C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_DisableClock\n
1681 * C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_DisableClock
1682 * @param Periphs This parameter can be a combination of the following values:
1683 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1684 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1685 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1686 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
1687 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1688 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1689 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
1690 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
1691 * @note (*) Not supported by all the devices
1692 * @retval None
1693 */
LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)1694 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
1695 {
1696 CLEAR_BIT(RCC->C2AHB2ENR, Periphs);
1697 }
1698
1699 /**
1700 * @brief Enable C2AHB2 peripherals clock during Low Power (Sleep) mode.
1701 * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1702 * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1703 * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1704 * C2AHB2SMENR GPIODSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1705 * C2AHB2SMENR GPIOESMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1706 * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1707 * C2AHB2SMENR ADCSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1708 * C2AHB2SMENR AES1SMEN LL_C2_AHB2_GRP1_EnableClockSleep
1709 * @param Periphs This parameter can be a combination of the following values:
1710 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1711 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1712 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1713 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
1714 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1715 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1716 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
1717 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
1718 * @note (*) Not supported by all the devices
1719 * @retval None
1720 */
LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)1721 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
1722 {
1723 __IO uint32_t tmpreg;
1724 SET_BIT(RCC->C2AHB2SMENR, Periphs);
1725 /* Delay after an RCC peripheral clock enabling */
1726 tmpreg = READ_BIT(RCC->C2AHB2SMENR, Periphs);
1727 (void)tmpreg;
1728 }
1729
1730 /**
1731 * @brief Disable C2AHB2 peripherals clock during Low Power (Sleep) mode.
1732 * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1733 * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1734 * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1735 * C2AHB2SMENR GPIODSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1736 * C2AHB2SMENR GPIOESMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1737 * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1738 * C2AHB2SMENR ADCSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1739 * C2AHB2SMENR AES1SMEN LL_C2_AHB2_GRP1_DisableClockSleep
1740 * @param Periphs This parameter can be a combination of the following values:
1741 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1742 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1743 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1744 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD (*)
1745 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1746 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1747 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC (*)
1748 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1 (*)
1749 * @note (*) Not supported by all the devices
1750 * @retval None
1751 */
LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)1752 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
1753 {
1754 CLEAR_BIT(RCC->C2AHB2SMENR, Periphs);
1755 }
1756
1757 /**
1758 * @}
1759 */
1760
1761 /** @defgroup BUS_LL_EF_C2_AHB3 C2 AHB3
1762 * @{
1763 */
1764
1765 /**
1766 * @brief Enable C2AHB3 peripherals clock.
1767 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_EnableClock\n
1768 * C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_EnableClock\n
1769 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_EnableClock\n
1770 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_EnableClock\n
1771 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_EnableClock\n
1772 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock
1773 * @param Periphs This parameter can be a combination of the following values:
1774 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1775 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1776 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1777 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1778 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1779 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1780 * @retval None
1781 */
LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)1782 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
1783 {
1784 __IO uint32_t tmpreg;
1785 SET_BIT(RCC->C2AHB3ENR, Periphs);
1786 /* Delay after an RCC peripheral clock enabling */
1787 tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs);
1788 (void)tmpreg;
1789 }
1790
1791 /**
1792 * @brief Check if C2AHB3 peripheral clock is enabled or not
1793 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1794 * C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_IsEnabledClock\n
1795 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1796 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1797 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1798 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock
1799 * @param Periphs This parameter can be a combination of the following values:
1800 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1801 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1802 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1803 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1804 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1805 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1806 * @retval uint32_t
1807 */
LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)1808 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1809 {
1810 return ((READ_BIT(RCC->C2AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1811 }
1812
1813 /**
1814 * @brief Disable C2AHB3 peripherals clock.
1815 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_DisableClock\n
1816 * C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_DisableClock\n
1817 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_DisableClock\n
1818 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_DisableClock\n
1819 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_DisableClock\n
1820 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock
1821 * @param Periphs This parameter can be a combination of the following values:
1822 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1823 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1824 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1825 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1826 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1827 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1828 * @retval None
1829 */
LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)1830 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
1831 {
1832 CLEAR_BIT(RCC->C2AHB3ENR, Periphs);
1833 }
1834
1835 /**
1836 * @brief Enable C2AHB3 peripherals clock during Low Power (Sleep) mode.
1837 * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1838 * C2AHB3SMENR AES2SMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1839 * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1840 * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1841 * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_EnableClockSleep
1842 * @param Periphs This parameter can be a combination of the following values:
1843 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1844 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1845 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1846 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
1847 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1848 * @retval None
1849 */
LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)1850 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
1851 {
1852 __IO uint32_t tmpreg;
1853 SET_BIT(RCC->C2AHB3SMENR, Periphs);
1854 /* Delay after an RCC peripheral clock enabling */
1855 tmpreg = READ_BIT(RCC->C2AHB3SMENR, Periphs);
1856 (void)tmpreg;
1857 }
1858
1859 /**
1860 * @brief Disable C2AHB3 peripherals clock during Low Power (Sleep) mode.
1861 * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1862 * C2AHB3SMENR AES2SMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1863 * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1864 * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1865 * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_DisableClockSleep
1866 * @param Periphs This parameter can be a combination of the following values:
1867 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1868 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1869 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1870 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
1871 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1872 * @retval None
1873 */
LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)1874 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
1875 {
1876 CLEAR_BIT(RCC->C2AHB3SMENR, Periphs);
1877 }
1878
1879 /**
1880 * @}
1881 */
1882
1883 /** @defgroup BUS_LL_EF_C2_APB1 C2 APB1
1884 * @{
1885 */
1886
1887 /**
1888 * @brief Enable C2APB1 peripherals clock.
1889 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_EnableClock\n
1890 * C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_EnableClock\n
1891 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_EnableClock\n
1892 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_EnableClock\n
1893 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_EnableClock\n
1894 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_EnableClock\n
1895 * C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_EnableClock\n
1896 * C2APB1ENR1 USBEN LL_C2_APB1_GRP1_EnableClock\n
1897 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_EnableClock
1898 * @param Periphs This parameter can be a combination of the following values:
1899 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
1900 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
1901 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
1902 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
1903 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
1904 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
1905 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
1906 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
1907 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
1908 * @note (*) Not supported by all the devices
1909 * @retval None
1910 */
LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)1911 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
1912 {
1913 __IO uint32_t tmpreg;
1914 SET_BIT(RCC->C2APB1ENR1, Periphs);
1915 /* Delay after an RCC peripheral clock enabling */
1916 tmpreg = READ_BIT(RCC->C2APB1ENR1, Periphs);
1917 (void)tmpreg;
1918 }
1919
1920 /**
1921 * @brief Enable C2APB1 peripherals clock.
1922 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_EnableClock\n
1923 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_EnableClock
1924 * @param Periphs This parameter can be a combination of the following values:
1925 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
1926 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
1927 * @note (*) Not supported by all the devices
1928 * @retval None
1929 */
LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)1930 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
1931 {
1932 __IO uint32_t tmpreg;
1933 SET_BIT(RCC->C2APB1ENR2, Periphs);
1934 /* Delay after an RCC peripheral clock enabling */
1935 tmpreg = READ_BIT(RCC->C2APB1ENR2, Periphs);
1936 (void)tmpreg;
1937 }
1938
1939 /**
1940 * @brief Check if C2APB1 peripheral clock is enabled or not
1941 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n
1942 * C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_IsEnabledClock\n
1943 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_IsEnabledClock\n
1944 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n
1945 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n
1946 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n
1947 * C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_IsEnabledClock\n
1948 * C2APB1ENR1 USBEN LL_C2_APB1_GRP1_IsEnabledClock\n
1949 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock
1950 * @param Periphs This parameter can be a combination of the following values:
1951 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
1952 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
1953 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
1954 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
1955 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
1956 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
1957 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
1958 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
1959 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
1960 * @note (*) Not supported by all the devices
1961 * @retval uint32_t
1962 */
LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1963 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1964 {
1965 return ((READ_BIT(RCC->C2APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
1966 }
1967
1968 /**
1969 * @brief Check if C2APB1 peripheral clock is enabled or not
1970 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_IsEnabledClock\n
1971 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_IsEnabledClock
1972 * @param Periphs This parameter can be a combination of the following values:
1973 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
1974 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
1975 * @note (*) Not supported by all the devices
1976 * @retval uint32_t
1977 */
LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1978 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1979 {
1980 return ((READ_BIT(RCC->C2APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
1981 }
1982
1983 /**
1984 * @brief Disable C2APB1 peripherals clock.
1985 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_DisableClock\n
1986 * C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_DisableClock\n
1987 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_DisableClock\n
1988 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_DisableClock\n
1989 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_DisableClock\n
1990 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_DisableClock\n
1991 * C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_DisableClock\n
1992 * C2APB1ENR1 USBEN LL_C2_APB1_GRP1_DisableClock\n
1993 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_DisableClock
1994 * @param Periphs This parameter can be a combination of the following values:
1995 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
1996 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
1997 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
1998 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
1999 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2000 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
2001 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
2002 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
2003 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2004 * @note (*) Not supported by all the devices
2005 * @retval None
2006 */
LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)2007 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
2008 {
2009 CLEAR_BIT(RCC->C2APB1ENR1, Periphs);
2010 }
2011
2012 /**
2013 * @brief Disable C2APB1 peripherals clock.
2014 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_DisableClock\n
2015 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_DisableClock
2016 * @param Periphs This parameter can be a combination of the following values:
2017 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
2018 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2019 * @note (*) Not supported by all the devices
2020 * @retval None
2021 */
LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)2022 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
2023 {
2024 CLEAR_BIT(RCC->C2APB1ENR2, Periphs);
2025 }
2026
2027 /**
2028 * @brief Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
2029 * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2030 * C2APB1SMENR1 LCDSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2031 * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2032 * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2033 * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2034 * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2035 * C2APB1SMENR1 CRSSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2036 * C2APB1SMENR1 USBSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2037 * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_EnableClockSleep
2038 * @param Periphs This parameter can be a combination of the following values:
2039 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
2040 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
2041 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
2042 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
2043 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2044 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
2045 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
2046 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
2047 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2048 * @note (*) Not supported by all the devices
2049 * @retval None
2050 */
LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)2051 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
2052 {
2053 __IO uint32_t tmpreg;
2054 SET_BIT(RCC->C2APB1SMENR1, Periphs);
2055 /* Delay after an RCC peripheral clock enabling */
2056 tmpreg = READ_BIT(RCC->C2APB1SMENR1, Periphs);
2057 (void)tmpreg;
2058 }
2059
2060 /**
2061 * @brief Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
2062 * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_EnableClockSleep\n
2063 * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_EnableClockSleep
2064 * @param Periphs This parameter can be a combination of the following values:
2065 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
2066 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2067 * @note (*) Not supported by all the devices
2068 * @retval None
2069 */
LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)2070 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
2071 {
2072 __IO uint32_t tmpreg;
2073 SET_BIT(RCC->C2APB1SMENR2, Periphs);
2074 /* Delay after an RCC peripheral clock enabling */
2075 tmpreg = READ_BIT(RCC->C2APB1SMENR2, Periphs);
2076 (void)tmpreg;
2077 }
2078
2079 /**
2080 * @brief Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
2081 * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2082 * C2APB1SMENR1 LCDSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2083 * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2084 * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2085 * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2086 * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2087 * C2APB1SMENR1 CRSSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2088 * C2APB1SMENR1 USBSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2089 * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_DisableClockSleep
2090 * @param Periphs This parameter can be a combination of the following values:
2091 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
2092 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD (*)
2093 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
2094 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2 (*)
2095 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2096 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3 (*)
2097 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS (*)
2098 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB (*)
2099 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2100 * @note (*) Not supported by all the devices
2101 * @retval None
2102 */
LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)2103 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
2104 {
2105 CLEAR_BIT(RCC->C2APB1SMENR1, Periphs);
2106 }
2107
2108 /**
2109 * @brief Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
2110 * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_DisableClockSleep\n
2111 * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_DisableClockSleep
2112 * @param Periphs This parameter can be a combination of the following values:
2113 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1 (*)
2114 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2115 * @note (*) Not supported by all the devices
2116 * @retval None
2117 */
LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)2118 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
2119 {
2120 CLEAR_BIT(RCC->C2APB1SMENR2, Periphs);
2121 }
2122
2123 /**
2124 * @}
2125 */
2126
2127 /** @defgroup BUS_LL_EF_C2_APB2 C2 APB2
2128 * @{
2129 */
2130
2131 /**
2132 * @brief Enable C2APB2 peripherals clock.
2133 * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_EnableClock\n
2134 * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n
2135 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n
2136 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n
2137 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n
2138 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n
2139 * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock
2140 * @param Periphs This parameter can be a combination of the following values:
2141 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
2142 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2143 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2144 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2145 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
2146 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
2147 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
2148 * @note (*) Not supported by all the devices
2149 * @retval None
2150 */
LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)2151 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
2152 {
2153 __IO uint32_t tmpreg;
2154 SET_BIT(RCC->C2APB2ENR, Periphs);
2155 /* Delay after an RCC peripheral clock enabling */
2156 tmpreg = READ_BIT(RCC->C2APB2ENR, Periphs);
2157 (void)tmpreg;
2158 }
2159
2160 /**
2161 * @brief Check if C2APB2 peripheral clock is enabled or not
2162 * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_IsEnabledClock\n
2163 * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2164 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2165 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2166 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n
2167 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n
2168 * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock
2169 * @param Periphs This parameter can be a combination of the following values:
2170 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
2171 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2172 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2173 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2174 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
2175 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
2176 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
2177 * @note (*) Not supported by all the devices
2178 * @retval uint32_t
2179 */
LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2180 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2181 {
2182 return ((READ_BIT(RCC->C2APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
2183 }
2184
2185 /**
2186 * @brief Disable C2APB2 peripherals clock.
2187 * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_DisableClock\n
2188 * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n
2189 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n
2190 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n
2191 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n
2192 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n
2193 * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock
2194 * @param Periphs This parameter can be a combination of the following values:
2195 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
2196 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2197 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2198 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2199 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
2200 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
2201 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
2202 * @note (*) Not supported by all the devices
2203 * @retval None
2204 */
LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)2205 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
2206 {
2207 CLEAR_BIT(RCC->C2APB2ENR, Periphs);
2208 }
2209
2210 /**
2211 * @brief Enable C2APB2 peripherals clock during Low Power (Sleep) mode.
2212 * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2213 * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2214 * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2215 * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2216 * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2217 * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2218 * C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_EnableClockSleep
2219 * @param Periphs This parameter can be a combination of the following values:
2220 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
2221 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2222 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2223 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2224 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
2225 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
2226 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
2227 * @note (*) Not supported by all the devices
2228 * @retval None
2229 */
LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)2230 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2231 {
2232 __IO uint32_t tmpreg;
2233 SET_BIT(RCC->C2APB2SMENR, Periphs);
2234 /* Delay after an RCC peripheral clock enabling */
2235 tmpreg = READ_BIT(RCC->C2APB2SMENR, Periphs);
2236 (void)tmpreg;
2237 }
2238
2239 /**
2240 * @brief Disable C2APB2 peripherals clock during Low Power (Sleep) mode.
2241 * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2242 * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2243 * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2244 * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2245 * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2246 * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2247 * C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_DisableClockSleep
2248 * @param Periphs This parameter can be a combination of the following values:
2249 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC (*)
2250 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2251 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2252 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2253 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16 (*)
2254 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17 (*)
2255 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1 (*)
2256 * @note (*) Not supported by all the devices
2257 * @retval None
2258 */
LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)2259 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2260 {
2261 CLEAR_BIT(RCC->C2APB2SMENR, Periphs);
2262 }
2263
2264 /**
2265 * @}
2266 */
2267
2268 /** @defgroup BUS_LL_EF_C2_APB3 C2 APB3
2269 * @{
2270 */
2271
2272 /**
2273 * @brief Enable C2APB3 peripherals clock.
2274 * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_EnableClock\n
2275 * C2APB3ENR 802EN LL_C2_APB3_GRP1_EnableClock (*)
2276 * @param Periphs This parameter can be a combination of the following values:
2277 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2278 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
2279 * @note (*) Not supported by all the devices
2280 * @retval None
2281 */
LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)2282 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
2283 {
2284 __IO uint32_t tmpreg;
2285 SET_BIT(RCC->C2APB3ENR, Periphs);
2286 /* Delay after an RCC peripheral clock enabling */
2287 tmpreg = READ_BIT(RCC->C2APB3ENR, Periphs);
2288 (void)tmpreg;
2289 }
2290
2291 /**
2292 * @brief Check if C2APB3 peripheral clock is enabled or not
2293 * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_IsEnabledClock\n
2294 * C2APB3ENR 802EN LL_C2_APB3_GRP1_IsEnabledClock (*)
2295 * @param Periphs This parameter can be a combination of the following values:
2296 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2297 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
2298 * @note (*) Not supported by all the devices
2299 * @retval uint32_t
2300 */
LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)2301 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
2302 {
2303 return ((READ_BIT(RCC->C2APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
2304 }
2305
2306 /**
2307 * @brief Disable C2APB3 peripherals clock.
2308 * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_DisableClock\n
2309 * C2APB3ENR 802EN LL_C2_APB3_GRP1_DisableClock (*)
2310 * @param Periphs This parameter can be a combination of the following values:
2311 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2312 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
2313 * @note (*) Not supported by all the devices
2314 * @retval None
2315 */
LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)2316 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
2317 {
2318 CLEAR_BIT(RCC->C2APB3ENR, Periphs);
2319 }
2320
2321 /**
2322 * @brief Enable C2APB3 peripherals clock during Low Power (Sleep) mode.
2323 * @rmtoll C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_EnableClockSleep\n
2324 * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_EnableClockSleep (*)
2325 * @param Periphs This parameter can be a combination of the following values:
2326 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2327 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
2328 * @note (*) Not supported by all the devices
2329 * @retval None
2330 */
LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)2331 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
2332 {
2333 __IO uint32_t tmpreg;
2334 SET_BIT(RCC->C2APB3SMENR, Periphs);
2335 /* Delay after an RCC peripheral clock enabling */
2336 tmpreg = READ_BIT(RCC->C2APB3SMENR, Periphs);
2337 (void)tmpreg;
2338 }
2339
2340 /**
2341 * @brief Disable C2APB3 peripherals clock during Low Power (Sleep) mode.
2342 * @rmtoll C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_DisableClockSleep\n
2343 * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_DisableClockSleep (*)
2344 * @param Periphs This parameter can be a combination of the following values:
2345 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2346 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802 (*)
2347 * @note (*) Not supported by all the devices
2348 * @retval None
2349 */
LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)2350 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
2351 {
2352 CLEAR_BIT(RCC->C2APB3SMENR, Periphs);
2353 }
2354
2355 /**
2356 * @}
2357 */
2358
2359 /**
2360 * @}
2361 */
2362
2363 /**
2364 * @}
2365 */
2366
2367 #endif /* defined(RCC) */
2368
2369 /**
2370 * @}
2371 */
2372
2373 #ifdef __cplusplus
2374 }
2375 #endif
2376
2377 #endif /* STM32WBxx_LL_BUS_H */
2378
