1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2018 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef STM32G0xx_LL_BUS_H
37 #define STM32G0xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32g0xx.h"
45
46 /** @addtogroup STM32G0xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58
59 /* Private constants ---------------------------------------------------------*/
60
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
74 #if defined(DMA2)
75 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
76 #endif /* DMA2 */
77 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
78 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN
79 #if defined(CRC)
80 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
81 #endif /* CRC */
82 #if defined(AES)
83 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
84 #endif /* AES */
85 #if defined(RNG)
86 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN
87 #endif /* RNG */
88 /**
89 * @}
90 */
91
92
93 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
94 * @{
95 */
96 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
97 #if defined(TIM2)
98 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
99 #endif /* TIM2 */
100 #if defined(TIM3)
101 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
102 #endif /* TIM3 */
103 #if defined(TIM4)
104 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APBENR1_TIM4EN
105 #endif /* TIM4 */
106 #if defined(TIM6)
107 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APBENR1_TIM6EN
108 #endif /* TIM6 */
109 #if defined(TIM7)
110 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APBENR1_TIM7EN
111 #endif /* TIM7 */
112 #if defined(LPUART2)
113 #define LL_APB1_GRP1_PERIPH_LPUART2 RCC_APBENR1_LPUART2EN
114 #endif /* LPUART2 */
115 #if defined(USART5)
116 #define LL_APB1_GRP1_PERIPH_USART5 RCC_APBENR1_USART5EN
117 #endif /* USART5 */
118 #if defined(USART6)
119 #define LL_APB1_GRP1_PERIPH_USART6 RCC_APBENR1_USART6EN
120 #endif /* USART6 */
121 #define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN
122 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
123 #if defined(FDCAN1) || defined(FDCAN2)
124 #define LL_APB1_GRP1_PERIPH_FDCAN RCC_APBENR1_FDCANEN
125 #endif /* FDCAN1 */
126 #if defined(USB_DRD_FS)
127 #define LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN
128 #endif /* USB_DRD_FS */
129 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN
130 #if defined(SPI3)
131 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APBENR1_SPI3EN
132 #endif /* SPI3 */
133 #if defined(CRS)
134 #define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
135 #endif /* CRS */
136 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
137 #if defined(USART3)
138 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN
139 #endif /* USART3 */
140 #if defined(USART4)
141 #define LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN
142 #endif /* USART4 */
143 #if defined(LPUART1)
144 #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APBENR1_LPUART1EN
145 #endif /* LPUART1 */
146 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN
147 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN
148 #if defined(I2C3)
149 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APBENR1_I2C3EN
150 #endif /* I2C3 */
151 #if defined(CEC)
152 #define LL_APB1_GRP1_PERIPH_CEC RCC_APBENR1_CECEN
153 #endif /* CEC */
154 #if defined(UCPD1)
155 #define LL_APB1_GRP1_PERIPH_UCPD1 RCC_APBENR1_UCPD1EN
156 #endif /* UCPD1 */
157 #if defined(UCPD2)
158 #define LL_APB1_GRP1_PERIPH_UCPD2 RCC_APBENR1_UCPD2EN
159 #endif /* UCPD2 */
160 #define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN
161 #define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
162 #if defined(DAC1)
163 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APBENR1_DAC1EN
164 #endif /* DAC1 */
165 #if defined(LPTIM2)
166 #define LL_APB1_GRP1_PERIPH_LPTIM2 RCC_APBENR1_LPTIM2EN
167 #endif /* LPTIM2 */
168 #if defined(LPTIM1)
169 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIM1EN
170 #endif /* LPTIM1 */
171 /**
172 * @}
173 */
174
175 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
176 * @{
177 */
178 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
179 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
180 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APBENR2_TIM1EN
181 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APBENR2_SPI1EN
182 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APBENR2_USART1EN
183 #if defined(TIM14)
184 #define LL_APB2_GRP1_PERIPH_TIM14 RCC_APBENR2_TIM14EN
185 #endif /* TIM14 */
186 #if defined(TIM15)
187 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APBENR2_TIM15EN
188 #endif /* TIM15 */
189 #if defined(TIM16)
190 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APBENR2_TIM16EN
191 #endif /* TIM16 */
192 #if defined(TIM17)
193 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APBENR2_TIM17EN
194 #endif /* TIM17 */
195 #if defined(ADC)
196 #define LL_APB2_GRP1_PERIPH_ADC RCC_APBENR2_ADCEN
197 #endif /* ADC */
198 /**
199 * @}
200 */
201
202 /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
203 * @{
204 */
205 #define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
206 #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
207 #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
208 #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN
209 #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN
210 #if defined(GPIOE)
211 #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN
212 #endif /* GPIOE */
213 #if defined(GPIOF)
214 #define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN
215 #endif /* GPIOF */
216 /**
217 * @}
218 */
219
220 /**
221 * @}
222 */
223
224 /* Exported macro ------------------------------------------------------------*/
225 /* Exported functions --------------------------------------------------------*/
226 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
227 * @{
228 */
229
230 /** @defgroup BUS_LL_EF_AHB1 AHB1
231 * @{
232 */
233
234 /**
235 * @brief Enable AHB1 peripherals clock.
236 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
237 * AHBENR FLASHEN LL_AHB1_GRP1_EnableClock\n
238 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
239 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
240 * AHBENR RNGEN LL_AHB1_GRP1_EnableClock
241 * @param Periphs This parameter can be a combination of the following values:
242 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
243 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
244 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
245 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
246 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
247 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
248 * @retval None
249 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)250 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
251 {
252 __IO uint32_t tmpreg;
253 SET_BIT(RCC->AHBENR, Periphs);
254 /* Delay after an RCC peripheral clock enabling */
255 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
256 (void)tmpreg;
257 }
258
259 /**
260 * @brief Check if AHB1 peripheral clock is enabled or not
261 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
262 * AHBENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
263 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
264 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
265 * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock
266 * @param Periphs This parameter can be a combination of the following values:
267 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
268 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
269 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
270 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
271 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
272 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
273 * @retval State of Periphs (1 or 0).
274 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)275 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
276 {
277 return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL);
278 }
279
280 /**
281 * @brief Disable AHB1 peripherals clock.
282 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
283 * AHBENR FLASHEN LL_AHB1_GRP1_DisableClock\n
284 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
285 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
286 * AHBENR RNGEN LL_AHB1_GRP1_DisableClock
287 * @param Periphs This parameter can be a combination of the following values:
288 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
289 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
290 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
291 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
292 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
293 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
294 * @retval None
295 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)296 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
297 {
298 CLEAR_BIT(RCC->AHBENR, Periphs);
299 }
300
301 /**
302 * @brief Force AHB1 peripherals reset.
303 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
304 * AHBRSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
305 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
306 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
307 * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset
308 * @param Periphs This parameter can be a combination of the following values:
309 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
310 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
311 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
312 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
313 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
314 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
315 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
316 * @retval None
317 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)318 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
319 {
320 SET_BIT(RCC->AHBRSTR, Periphs);
321 }
322
323 /**
324 * @brief Release AHB1 peripherals reset.
325 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
326 * AHBRSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
327 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
328 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
329 * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset
330 * @param Periphs This parameter can be a combination of the following values:
331 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
332 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
333 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
334 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
335 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
336 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
337 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
338 * @retval None
339 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)340 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
341 {
342 CLEAR_BIT(RCC->AHBRSTR, Periphs);
343 }
344
345 /**
346 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
347 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
348 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
349 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
350 * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
351 * AHBSMENR AESSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
352 * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockStopSleep
353 * @param Periphs This parameter can be a combination of the following values:
354 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
355 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
356 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
357 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
358 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
359 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
360 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
361 * @retval None
362 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)363 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
364 {
365 __IO uint32_t tmpreg;
366 SET_BIT(RCC->AHBSMENR, Periphs);
367 /* Delay after an RCC peripheral clock enabling */
368 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
369 (void)tmpreg;
370 }
371
372 /**
373 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
374 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
375 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
376 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
377 * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
378 * AHBSMENR AESSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
379 * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockStopSleep
380 * @param Periphs This parameter can be a combination of the following values:
381 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
382 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
383 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
384 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
385 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
386 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
387 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
388 * @retval None
389 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)390 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
391 {
392 CLEAR_BIT(RCC->AHBSMENR, Periphs);
393 }
394
395 /**
396 * @}
397 */
398
399 /** @defgroup BUS_LL_EF_APB1 APB1
400 * @{
401 */
402
403 /**
404 * @brief Enable APB1 peripherals clock.
405 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
406 * APBENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
407 * APBENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
408 * APBENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
409 * APBENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
410 * APBENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
411 * APBENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
412 * APBENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
413 * APBENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
414 * APBENR1 USART2EN LL_APB1_GRP1_EnableClock\n
415 * APBENR1 USART3EN LL_APB1_GRP1_EnableClock\n
416 * APBENR1 USART4EN LL_APB1_GRP1_EnableClock\n
417 * APBENR1 USART5EN LL_APB1_GRP1_EnableClock\n
418 * APBENR1 USART6EN LL_APB1_GRP1_EnableClock\n
419 * APBENR1 LPUART1EN LL_APB1_GRP1_EnableClock\n
420 * APBENR1 LPUART2EN LL_APB1_GRP1_EnableClock\n
421 * APBENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
422 * APBENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
423 * APBENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
424 * APBENR1 CECEN LL_APB1_GRP1_EnableClock\n
425 * APBENR1 UCPD1EN LL_APB1_GRP1_EnableClock\n
426 * APBENR1 UCPD2EN LL_APB1_GRP1_EnableClock\n
427 * APBENR1 USBEN LL_APB1_GRP1_EnableClock\n
428 * APBENR1 FDCANEN LL_APB1_GRP1_EnableClock\n
429 * APBENR1 DBGEN LL_APB1_GRP1_EnableClock\n
430 * APBENR1 PWREN LL_APB1_GRP1_EnableClock\n
431 * APBENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
432 * APBENR1 LPTIM2EN LL_APB1_GRP1_EnableClock\n
433 * APBENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
434 * @param Periphs This parameter can be a combination of the following values:
435 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
436 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
437 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
438 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
439 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
440 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
441 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
442 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
443 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
444 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
445 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
446 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
447 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
448 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
449 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
450 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
451 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
452 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
453 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
454 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
455 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
456 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
457 * @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
458 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
459 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
460 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
461 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
462 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
463 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
464 * @note Peripheral marked with (1) are not available all devices
465 * @retval None
466 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)467 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
468 {
469 __IO uint32_t tmpreg;
470 SET_BIT(RCC->APBENR1, Periphs);
471 /* Delay after an RCC peripheral clock enabling */
472 tmpreg = READ_BIT(RCC->APBENR1, Periphs);
473 (void)tmpreg;
474 }
475
476 /**
477 * @brief Check if APB1 peripheral clock is enabled or not
478 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
479 * APBENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
480 * APBENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
481 * APBENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
482 * APBENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
483 * APBENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
484 * APBENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
485 * APBENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
486 * APBENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
487 * APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
488 * APBENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
489 * APBENR1 USART4EN LL_APB1_GRP1_IsEnabledClock\n
490 * APBENR1 USART5EN LL_APB1_GRP1_IsEnabledClock\n
491 * APBENR1 USART6EN LL_APB1_GRP1_IsEnabledClock\n
492 * APBENR1 LPUART1EN LL_APB1_GRP1_IsEnabledClock\n
493 * APBENR1 LPUART2EN LL_APB1_GRP1_IsEnabledClock\n
494 * APBENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
495 * APBENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
496 * APBENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
497 * APBENR1 CECEN LL_APB1_GRP1_IsEnabledClock\n
498 * APBENR1 UCPD1EN LL_APB1_GRP1_IsEnabledClock\n
499 * APBENR1 UCPD2EN LL_APB1_GRP1_IsEnabledClock\n
500 * APBENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
501 * APBENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock\n
502 * APBENR1 DBGEN LL_APB1_GRP1_IsEnabledClock\n
503 * APBENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
504 * APBENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
505 * APBENR1 LPTIM2EN LL_APB1_GRP1_IsEnabledClock\n
506 * APBENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
507 * @param Periphs This parameter can be a combination of the following values:
508 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
509 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
510 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
511 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
512 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
513 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
514 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
515 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
516 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
517 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
518 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
519 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
520 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
521 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
522 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
523 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
524 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
525 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
526 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
527 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
528 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
529 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
530 * @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
531 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
532 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
533 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
534 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
535 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
536 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
537 * @note Peripheral marked with (1) are not available all devices
538 * @retval State of Periphs (1 or 0).
539 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)540 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
541 {
542 return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
543 }
544
545 /**
546 * @brief Disable APB1 peripherals clock.
547 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
548 * APBENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
549 * APBENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
550 * APBENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
551 * APBENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
552 * APBENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
553 * APBENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
554 * APBENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
555 * APBENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
556 * APBENR1 USART2EN LL_APB1_GRP1_DisableClock\n
557 * APBENR1 USART3EN LL_APB1_GRP1_DisableClock\n
558 * APBENR1 USART4EN LL_APB1_GRP1_DisableClock\n
559 * APBENR1 USART5EN LL_APB1_GRP1_DisableClock\n
560 * APBENR1 USART6EN LL_APB1_GRP1_DisableClock\n
561 * APBENR1 LPUART1EN LL_APB1_GRP1_DisableClock\n
562 * APBENR1 LPUART2EN LL_APB1_GRP1_DisableClock\n
563 * APBENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
564 * APBENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
565 * APBENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
566 * APBENR1 CECEN LL_APB1_GRP1_DisableClock\n
567 * APBENR1 UCPD1EN LL_APB1_GRP1_DisableClock\n
568 * APBENR1 UCPD2EN LL_APB1_GRP1_DisableClock\n
569 * APBENR1 USBEN LL_APB1_GRP1_DisableClock\n
570 * APBENR1 FDCANEN LL_APB1_GRP1_DisableClock\n
571 * APBENR1 DBGEN LL_APB1_GRP1_DisableClock\n
572 * APBENR1 PWREN LL_APB1_GRP1_DisableClock\n
573 * APBENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
574 * APBENR1 LPTIM2EN LL_APB1_GRP1_DisableClock\n
575 * APBENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
576 * @param Periphs This parameter can be a combination of the following values:
577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
579 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
580 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
582 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
583 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
584 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
585 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
586 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
587 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
588 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
589 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
590 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
591 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
592 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
593 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
594 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
595 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
596 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
597 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
598 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
599 * @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
600 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
601 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
602 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
603 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
604 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
605 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
606 * @note Peripheral marked with (1) are not available all devices
607 * @retval None
608 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)609 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
610 {
611 CLEAR_BIT(RCC->APBENR1, Periphs);
612 }
613
614 /**
615 * @brief Force APB1 peripherals reset.
616 * @rmtoll APBRSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
617 * APBRSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
618 * APBRSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
619 * APBRSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
620 * APBRSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
621 * APBRSTR1 RTCRST LL_APB1_GRP1_ForceReset\n
622 * APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
623 * APBRSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
624 * APBRSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
625 * APBRSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
626 * APBRSTR1 USART4RST LL_APB1_GRP1_ForceReset\n
627 * APBRSTR1 USART5RST LL_APB1_GRP1_ForceReset\n
628 * APBRSTR1 USART6RST LL_APB1_GRP1_ForceReset\n
629 * APBRSTR1 LPUART1RST LL_APB1_GRP1_ForceReset\n
630 * APBRSTR1 LPUART2RST LL_APB1_GRP1_ForceReset\n
631 * APBRSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
632 * APBRSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
633 * APBRSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
634 * APBRSTR1 CECRST LL_APB1_GRP1_ForceReset\n
635 * APBRSTR1 UCPD1RST LL_APB1_GRP1_ForceReset\n
636 * APBRSTR1 UCPD2RST LL_APB1_GRP1_ForceReset\n
637 * APBRSTR1 USBRST LL_APB1_GRP1_ForceReset\n
638 * APBRSTR1 FDCANRST LL_APB1_GRP1_ForceReset\n
639 * APBRSTR1 DBGRST LL_APB1_GRP1_ForceReset\n
640 * APBRSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
641 * APBRSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
642 * APBRSTR1 LPTIM2RST LL_APB1_GRP1_ForceReset\n
643 * APBRSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
644 * @param Periphs This parameter can be a combination of the following values:
645 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
646 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
647 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
648 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
649 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
650 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
651 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
652 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
653 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
654 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
655 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
656 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
657 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
658 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
659 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
660 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
661 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
662 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
663 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
664 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
665 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
666 * @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
667 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
668 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
669 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
670 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
671 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
672 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
673 * @note Peripheral marked with (1) are not available all devices
674 * @retval None
675 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)676 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
677 {
678 SET_BIT(RCC->APBRSTR1, Periphs);
679 }
680
681 /**
682 * @brief Release APB1 peripherals reset.
683 * @rmtoll APBRSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
684 * APBRSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
685 * APBRSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
686 * APBRSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
687 * APBRSTR1 RTCRST LL_APB1_GRP1_ReleaseReset\n
688 * APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
689 * APBRSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
690 * APBRSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
691 * APBRSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
692 * APBRSTR1 USART4RST LL_APB1_GRP1_ReleaseReset\n
693 * APBRSTR1 USART5RST LL_APB1_GRP1_ReleaseReset\n
694 * APBRSTR1 USART6RST LL_APB1_GRP1_ReleaseReset\n
695 * APBRSTR1 LPUART1RST LL_APB1_GRP1_ReleaseReset\n
696 * APBRSTR1 LPUART2RST LL_APB1_GRP1_ReleaseReset\n
697 * APBRSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
698 * APBRSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
699 * APBRSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
700 * APBRSTR1 CECRST LL_APB1_GRP1_ReleaseReset\n
701 * APBRSTR1 UCPD1RST LL_APB1_GRP1_ReleaseReset\n
702 * APBRSTR1 UCPD2RST LL_APB1_GRP1_ReleaseReset\n
703 * APBRSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
704 * APBRSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset\n
705 * APBRSTR1 DBGRST LL_APB1_GRP1_ReleaseReset\n
706 * APBRSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
707 * APBRSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
708 * APBRSTR1 LPTIM2RST LL_APB1_GRP1_ReleaseReset\n
709 * APBRSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
710 * @param Periphs This parameter can be a combination of the following values:
711 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
712 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
713 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
714 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
715 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
716 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
717 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
718 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
719 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
720 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
721 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
722 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
723 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
724 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
725 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
726 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
727 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
728 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
729 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
730 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
731 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
732 * @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
733 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
734 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
735 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
736 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
737 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
738 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
739 * @note Peripheral marked with (1) are not available all devices
740 * @retval None
741 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)742 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
743 {
744 CLEAR_BIT(RCC->APBRSTR1, Periphs);
745 }
746
747 /**
748 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
749 * @rmtoll APBSMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
750 * APBSMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
751 * APBSMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
752 * APBSMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
753 * APBSMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
754 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
755 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
756 * APBSMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
757 * APBSMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
758 * APBSMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
759 * APBSMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
760 * APBSMENR1 USART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
761 * APBSMENR1 USART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
762 * APBSMENR1 USART6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
763 * APBSMENR1 LPUART1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
764 * APBSMENR1 LPUART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
765 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
766 * APBSMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
767 * APBSMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
768 * APBSMENR1 CECSMEN LL_APB1_GRP1_EnableClockStopSleep\n
769 * APBSMENR1 UCPD1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
770 * APBSMENR1 UCPD2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
771 * APBSMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
772 * APBSMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep\n
773 * APBSMENR1 DBGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
774 * APBSMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
775 * APBSMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
776 * APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
777 * APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
778 * @param Periphs This parameter can be a combination of the following values:
779 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
780 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
781 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
782 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
783 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
784 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
785 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
786 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
787 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
788 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
789 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
790 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
791 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
792 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
793 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
794 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
795 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
796 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
797 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
798 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
799 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
800 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
801 * @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
802 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
803 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
804 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
805 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
806 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
807 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
808 * @note Peripheral marked with (1) are not available all devices
809 * @retval None
810 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)811 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
812 {
813 __IO uint32_t tmpreg;
814 SET_BIT(RCC->APBSMENR1, Periphs);
815 /* Delay after an RCC peripheral clock enabling */
816 tmpreg = READ_BIT(RCC->APBSMENR1, Periphs);
817 (void)tmpreg;
818 }
819
820 /**
821 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
822 * @rmtoll APBSMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
823 * APBSMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
824 * APBSMENR1 TIM'SMEN LL_APB1_GRP1_DisableClockStopSleep\n
825 * APBSMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
826 * APBSMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
827 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
828 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
829 * APBSMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
830 * APBSMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
831 * APBSMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
832 * APBSMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
833 * APBSMENR1 USART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
834 * APBSMENR1 USART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
835 * APBSMENR1 USART6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
836 * APBSMENR1 LPUART1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
837 * APBSMENR1 LPUART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
838 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
839 * APBSMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
840 * APBSMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
841 * APBSMENR1 CECSMEN LL_APB1_GRP1_DisableClockStopSleep\n
842 * APBSMENR1 UCPD1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
843 * APBSMENR1 UCPD2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
844 * APBSMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
845 * APBSMENR1 FSCANSMEN LL_APB1_GRP1_DisableClockStopSleep\n
846 * APBSMENR1 DBGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
847 * APBSMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
848 * APBSMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
849 * APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
850 * APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
851 * @param Periphs This parameter can be a combination of the following values:
852 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
853 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
854 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
855 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
856 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
857 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
858 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
859 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
860 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
861 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
862 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
863 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
864 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
865 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
866 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
867 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
868 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
869 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
870 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
871 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
872 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
873 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
874 * @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
875 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
876 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
877 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
878 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
879 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
880 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
881 * @note Peripheral marked with (1) are not available all devices
882 * @retval None
883 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)884 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
885 {
886 CLEAR_BIT(RCC->APBSMENR1, Periphs);
887 }
888
889 /**
890 * @}
891 */
892
893 /** @defgroup BUS_LL_EF_APB2 APB2
894 * @{
895 */
896
897 /**
898 * @brief Enable APB2 peripherals clock.
899 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_EnableClock\n
900 * APBENR2 TIM1EN LL_APB2_GRP1_EnableClock\n
901 * APBENR2 SPI1EN LL_APB2_GRP1_EnableClock\n
902 * APBENR2 USART1EN LL_APB2_GRP1_EnableClock\n
903 * APBENR2 TIM14EN LL_APB2_GRP1_EnableClock\n
904 * APBENR2 TIM15EN LL_APB2_GRP1_EnableClock\n
905 * APBENR2 TIM16EN LL_APB2_GRP1_EnableClock\n
906 * APBENR2 TIM17EN LL_APB2_GRP1_EnableClock\n
907 * APBENR2 ADCEN LL_APB2_GRP1_EnableClock
908 * @param Periphs This parameter can be a combination of the following values:
909 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
910 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
911 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
912 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
913 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
914 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
915 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
916 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
917 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
918 * @note (*) peripheral not available on all devices
919 * @retval None
920 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)921 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
922 {
923 __IO uint32_t tmpreg;
924 SET_BIT(RCC->APBENR2, Periphs);
925 /* Delay after an RCC peripheral clock enabling */
926 tmpreg = READ_BIT(RCC->APBENR2, Periphs);
927 (void)tmpreg;
928 }
929
930 /**
931 * @brief Check if APB2 peripheral clock is enabled or not
932 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
933 * APBENR2 TIM1EN LL_APB2_GRP1_IsEnabledClock\n
934 * APBENR2 SPI1EN LL_APB2_GRP1_IsEnabledClock\n
935 * APBENR2 USART1EN LL_APB2_GRP1_IsEnabledClock\n
936 * APBENR2 TIM14EN LL_APB2_GRP1_IsEnabledClock\n
937 * APBENR2 TIM15EN LL_APB2_GRP1_IsEnabledClock\n
938 * APBENR2 TIM16EN LL_APB2_GRP1_IsEnabledClock\n
939 * APBENR2 TIM17EN LL_APB2_GRP1_IsEnabledClock\n
940 * APBENR2 ADCEN LL_APB2_GRP1_IsEnabledClock
941 * @param Periphs This parameter can be a combination of the following values:
942 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
943 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
944 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
945 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
946 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
947 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
948 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
949 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
950 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
951 * @note (*) peripheral not available on all devices
952 * @retval State of Periphs (1 or 0).
953 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)954 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
955 {
956 return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
957 }
958
959 /**
960 * @brief Disable APB2 peripherals clock.
961 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_DisableClock\n
962 * APBENR2 TIM1EN LL_APB2_GRP1_DisableClock\n
963 * APBENR2 SPI1EN LL_APB2_GRP1_DisableClock\n
964 * APBENR2 USART1EN LL_APB2_GRP1_DisableClock\n
965 * APBENR2 TIM14EN LL_APB2_GRP1_DisableClock\n
966 * APBENR2 TIM15EN LL_APB2_GRP1_DisableClock\n
967 * APBENR2 TIM16EN LL_APB2_GRP1_DisableClock\n
968 * APBENR2 TIM17EN LL_APB2_GRP1_DisableClock\n
969 * APBENR2 ADCEN LL_APB2_GRP1_DisableClock
970 * @param Periphs This parameter can be a combination of the following values:
971 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
972 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
973 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
974 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
975 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
976 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
977 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
978 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
979 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
980 * @note (*) peripheral not available on all devices
981 * @retval None
982 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)983 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
984 {
985 CLEAR_BIT(RCC->APBENR2, Periphs);
986 }
987
988 /**
989 * @brief Force APB2 peripherals reset.
990 * @rmtoll APBRSTR2 SYSCFGRST LL_APB2_GRP1_ForceReset\n
991 * APBRSTR2 TIM1RST LL_APB2_GRP1_ForceReset\n
992 * APBRSTR2 SPI1RST LL_APB2_GRP1_ForceReset\n
993 * APBRSTR2 USART1RST LL_APB2_GRP1_ForceReset\n
994 * APBRSTR2 TIM14RST LL_APB2_GRP1_ForceReset\n
995 * APBRSTR2 TIM15RST LL_APB2_GRP1_ForceReset\n
996 * APBRSTR2 TIM16RST LL_APB2_GRP1_ForceReset\n
997 * APBRSTR2 TIM17RST LL_APB2_GRP1_ForceReset\n
998 * APBRSTR2 ADCRST LL_APB2_GRP1_ForceReset
999 * @param Periphs This parameter can be a combination of the following values:
1000 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1001 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1002 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1003 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1004 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1005 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
1006 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
1007 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1008 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1009 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1010 * @note (*) peripheral not available on all devices
1011 * @retval None
1012 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1013 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1014 {
1015 SET_BIT(RCC->APBRSTR2, Periphs);
1016 }
1017
1018 /**
1019 * @brief Release APB2 peripherals reset.
1020 * @rmtoll APBRSTR2 SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1021 * APBRSTR2 TIM1RST LL_APB2_GRP1_ReleaseReset\n
1022 * APBRSTR2 SPI1RST LL_APB2_GRP1_ReleaseReset\n
1023 * APBRSTR2 USART1RST LL_APB2_GRP1_ReleaseReset\n
1024 * APBRSTR2 TIM14RST LL_APB2_GRP1_ReleaseReset\n
1025 * APBRSTR2 TIM15RST LL_APB2_GRP1_ReleaseReset\n
1026 * APBRSTR2 TIM16RST LL_APB2_GRP1_ReleaseReset\n
1027 * APBRSTR2 TIM17RST LL_APB2_GRP1_ReleaseReset\n
1028 * APBRSTR2 ADCRST LL_APB2_GRP1_ReleaseReset
1029 * @param Periphs This parameter can be a combination of the following values:
1030 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1031 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1032 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1033 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1034 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1035 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
1036 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
1037 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1038 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1039 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1040 * @note (*) peripheral not available on all devices
1041 * @retval None
1042 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1043 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1044 {
1045 CLEAR_BIT(RCC->APBRSTR2, Periphs);
1046 }
1047
1048 /**
1049 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1050 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1051 * APBSMENR2 TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1052 * APBSMENR2 SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1053 * APBSMENR2 USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1054 * APBSMENR2 TIM14SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1055 * APBSMENR2 TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1056 * APBSMENR2 TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1057 * APBSMENR2 TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1058 * APBSMENR2 ADCSMEN LL_APB2_GRP1_EnableClockStopSleep
1059 * @param Periphs This parameter can be a combination of the following values:
1060 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1061 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1062 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1063 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1064 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
1065 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
1066 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1067 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1068 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1069 * @note (*) peripheral not available on all devices
1070 * @retval None
1071 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1072 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1073 {
1074 __IO uint32_t tmpreg;
1075 SET_BIT(RCC->APBSMENR2, Periphs);
1076 /* Delay after an RCC peripheral clock enabling */
1077 tmpreg = READ_BIT(RCC->APBSMENR2, Periphs);
1078 (void)tmpreg;
1079 }
1080
1081 /**
1082 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1083 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1084 * APBSMENR2 TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1085 * APBSMENR2 SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1086 * APBSMENR2 USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1087 * APBSMENR2 TIM14SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1088 * APBSMENR2 TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1089 * APBSMENR2 TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1090 * APBSMENR2 TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1091 * APBSMENR2 ADCSMEN LL_APB2_GRP1_DisableClockStopSleep
1092 * @param Periphs This parameter can be a combination of the following values:
1093 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1094 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1095 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1096 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1097 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
1098 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
1099 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1100 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1101 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1102 * @note (*) peripheral not available on all devices
1103 * @retval None
1104 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1105 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1106 {
1107 CLEAR_BIT(RCC->APBSMENR2, Periphs);
1108 }
1109
1110 /**
1111 * @}
1112 */
1113
1114 /** @defgroup BUS_LL_EF_IOP IOP
1115 * @{
1116 */
1117
1118 /**
1119 * @brief Enable IOP peripherals clock.
1120 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n
1121 * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n
1122 * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n
1123 * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n
1124 * IOPENR GPIOEEN LL_IOP_GRP1_EnableClock\n
1125 * IOPENR GPIOFEN LL_IOP_GRP1_EnableClock
1126 * @param Periphs This parameter can be a combination of the following values:
1127 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1128 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1129 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1130 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1131 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
1132 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1133 * @retval None
1134 */
LL_IOP_GRP1_EnableClock(uint32_t Periphs)1135 __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
1136 {
1137 __IO uint32_t tmpreg;
1138 SET_BIT(RCC->IOPENR, Periphs);
1139 /* Delay after an RCC peripheral clock enabling */
1140 tmpreg = READ_BIT(RCC->IOPENR, Periphs);
1141 (void)tmpreg;
1142 }
1143
1144 /**
1145 * @brief Check if IOP peripheral clock is enabled or not
1146 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n
1147 * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n
1148 * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n
1149 * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n
1150 * IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock\n
1151 * IOPENR GPIOFEN LL_IOP_GRP1_IsEnabledClock
1152 * @param Periphs This parameter can be a combination of the following values:
1153 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1154 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1155 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1156 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1157 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
1158 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1159 * @retval State of Periphs (1 or 0).
1160 */
LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)1161 __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
1162 {
1163 return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
1164 }
1165
1166 /**
1167 * @brief Disable IOP peripherals clock.
1168 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n
1169 * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n
1170 * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n
1171 * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n
1172 * IOPENR GPIOEEN LL_IOP_GRP1_DisableClock\n
1173 * IOPENR GPIOFEN LL_IOP_GRP1_DisableClock
1174 * @param Periphs This parameter can be a combination of the following values:
1175 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1176 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1177 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1178 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1179 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
1180 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1181 * @retval None
1182 */
LL_IOP_GRP1_DisableClock(uint32_t Periphs)1183 __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
1184 {
1185 CLEAR_BIT(RCC->IOPENR, Periphs);
1186 }
1187
1188 /**
1189 * @brief Disable IOP peripherals clock.
1190 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ForceReset\n
1191 * IOPRSTR GPIOBRST LL_IOP_GRP1_ForceReset\n
1192 * IOPRSTR GPIOCRST LL_IOP_GRP1_ForceReset\n
1193 * IOPRSTR GPIODRST LL_IOP_GRP1_ForceReset\n
1194 * IOPRSTR GPIOERST LL_IOP_GRP1_ForceReset\n
1195 * IOPRSTR GPIOFRST LL_IOP_GRP1_ForceReset
1196 * @param Periphs This parameter can be a combination of the following values:
1197 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
1198 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1199 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1200 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1201 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1202 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
1203 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1204 * @retval None
1205 */
LL_IOP_GRP1_ForceReset(uint32_t Periphs)1206 __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
1207 {
1208 SET_BIT(RCC->IOPRSTR, Periphs);
1209 }
1210
1211 /**
1212 * @brief Release IOP peripherals reset.
1213 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ReleaseReset\n
1214 * IOPRSTR GPIOBRST LL_IOP_GRP1_ReleaseReset\n
1215 * IOPRSTR GPIOCRST LL_IOP_GRP1_ReleaseReset\n
1216 * IOPRSTR GPIODRST LL_IOP_GRP1_ReleaseReset\n
1217 * IOPRSTR GPIOERST LL_IOP_GRP1_ReleaseReset\n
1218 * IOPRSTR GPIOFRST LL_IOP_GRP1_ReleaseReset
1219 * @param Periphs This parameter can be a combination of the following values:
1220 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
1221 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1222 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1223 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1224 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1225 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
1226 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1227 * @retval None
1228 */
LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)1229 __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
1230 {
1231 CLEAR_BIT(RCC->IOPRSTR, Periphs);
1232 }
1233
1234 /**
1235 * @brief Enable IOP peripheral clocks in Sleep and Stop modes
1236 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_EnableClockStopSleep\n
1237 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1238 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1239 * IOPSMENR GPIODSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1240 * IOPSMENR GPIOESMEN LL_IOP_GRP1_EnableClockStopSleep\n
1241 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_EnableClockStopSleep
1242 * @param Periphs This parameter can be a combination of the following values:
1243 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1244 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1245 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1246 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1247 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
1248 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1249 * @retval None
1250 */
LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)1251 __STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)
1252 {
1253 __IO uint32_t tmpreg;
1254 SET_BIT(RCC->IOPSMENR, Periphs);
1255 /* Delay after an RCC peripheral clock enabling */
1256 tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
1257 (void)tmpreg;
1258 }
1259
1260 /**
1261 * @brief Disable IOP peripheral clocks in Sleep and Stop modes
1262 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_DisableClockStopSleep\n
1263 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1264 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1265 * IOPSMENR GPIODSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1266 * IOPSMENR GPIOESMEN LL_IOP_GRP1_DisableClockStopSleep\n
1267 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_DisableClockStopSleep
1268 * @param Periphs This parameter can be a combination of the following values:
1269 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1270 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1271 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1272 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1273 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
1274 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1275 * @retval None
1276 */
LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)1277 __STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)
1278 {
1279 CLEAR_BIT(RCC->IOPSMENR, Periphs);
1280 }
1281
1282 /**
1283 * @}
1284 */
1285
1286
1287 /**
1288 * @}
1289 */
1290
1291 /**
1292 * @}
1293 */
1294
1295 #endif /* RCC */
1296
1297 /**
1298 * @}
1299 */
1300
1301 #ifdef __cplusplus
1302 }
1303 #endif
1304
1305 #endif /* STM32G0xx_LL_BUS_H */
1306
1307
