1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 (+) Access to VREFBUF registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef STM32WBxx_LL_SYSTEM_H
35 #define STM32WBxx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32wbxx.h"
43
44 /** @addtogroup STM32WBxx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61 /**
62 * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
63 */
64 #define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x1FFF75F0UL)) /*!< Address of VREFBUF trimming value for VRS=0,
65 VREF_SC0 in STM32WB datasheet */
66 #define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x1FFF7530UL)) /*!< Address of VREFBUF trimming value for VRS=1,
67 VREF_SC1 in STM32WB datasheet */
68 /**
69 * @}
70 */
71
72 /* Private macros ------------------------------------------------------------*/
73
74 /* Exported types ------------------------------------------------------------*/
75 /* Exported constants --------------------------------------------------------*/
76 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
77 * @{
78 */
79
80 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
81 * @{
82 */
83 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
84 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
85 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
86 #if defined(QUADSPI)
87 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
88 #endif /* QUADSPI */
89 /**
90 * @}
91 */
92
93 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
94 * @{
95 */
96 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
97 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
98 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
99 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
100 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
101 #if defined(I2C3)
102 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
103 #endif /* I2C3 */
104 /**
105 * @}
106 */
107
108 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
109 * @{
110 */
111 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
112 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
113 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
114 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
115 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
116 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
117 /**
118 * @}
119 */
120
121 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
122 * @{
123 */
124 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
125 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
126 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
127 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
128 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
129 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
130 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
131 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
132 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
133 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
134 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
135 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
136 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
137 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
138 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
139 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
140 /**
141 * @}
142 */
143
144 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
145 * @{
146 */
147 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
148 with Break Input of TIM1/16/17 */
149 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
150 with TIM1/16/17 Break Input
151 and also the PVDE
152 and PLS bits of the Power Control Interface */
153 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
154 with Break Input of TIM1/16/17 */
155 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
156 with Break Input of TIM1/16/17 */
157 /**
158 * @}
159 */
160
161 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRITE PROTECTION
162 * @{
163 */
164 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR1_PAGE0 /*!< SRAM2A Write protection page 0 */
165 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR1_PAGE1 /*!< SRAM2A Write protection page 1 */
166 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR1_PAGE2 /*!< SRAM2A Write protection page 2 */
167 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR1_PAGE3 /*!< SRAM2A Write protection page 3 */
168 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR1_PAGE4 /*!< SRAM2A Write protection page 4 */
169 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR1_PAGE5 /*!< SRAM2A Write protection page 5 */
170 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR1_PAGE6 /*!< SRAM2A Write protection page 6 */
171 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR1_PAGE7 /*!< SRAM2A Write protection page 7 */
172 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR1_PAGE8 /*!< SRAM2A Write protection page 8 */
173 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR1_PAGE9 /*!< SRAM2A Write protection page 9 */
174 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR1_PAGE10 /*!< SRAM2A Write protection page 10 */
175 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR1_PAGE11 /*!< SRAM2A Write protection page 11 */
176 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR1_PAGE12 /*!< SRAM2A Write protection page 12 */
177 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR1_PAGE13 /*!< SRAM2A Write protection page 13 */
178 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR1_PAGE14 /*!< SRAM2A Write protection page 14 */
179 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR1_PAGE15 /*!< SRAM2A Write protection page 15 */
180 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR1_PAGE16 /*!< SRAM2A Write protection page 16 */
181 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR1_PAGE17 /*!< SRAM2A Write protection page 17 */
182 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR1_PAGE18 /*!< SRAM2A Write protection page 18 */
183 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR1_PAGE19 /*!< SRAM2A Write protection page 19 */
184 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR1_PAGE20 /*!< SRAM2A Write protection page 20 */
185 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR1_PAGE21 /*!< SRAM2A Write protection page 21 */
186 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR1_PAGE22 /*!< SRAM2A Write protection page 22 */
187 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR1_PAGE23 /*!< SRAM2A Write protection page 23 */
188 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR1_PAGE24 /*!< SRAM2A Write protection page 24 */
189 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR1_PAGE25 /*!< SRAM2A Write protection page 25 */
190 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR1_PAGE26 /*!< SRAM2A Write protection page 26 */
191 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR1_PAGE27 /*!< SRAM2A Write protection page 27 */
192 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR1_PAGE28 /*!< SRAM2A Write protection page 28 */
193 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR1_PAGE29 /*!< SRAM2A Write protection page 29 */
194 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR1_PAGE30 /*!< SRAM2A Write protection page 30 */
195 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR1_PAGE31 /*!< SRAM2A Write protection page 31 */
196
197 #define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2B Write protection page 32 */
198 #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2B Write protection page 33 */
199 #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2B Write protection page 34 */
200 #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2B Write protection page 35 */
201 #if defined(SYSCFG_SWPR2_PAGE36)
202 #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2B Write protection page 36 */
203 #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2B Write protection page 37 */
204 #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2B Write protection page 38 */
205 #define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2B Write protection page 39 */
206 #define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2B Write protection page 40 */
207 #define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2B Write protection page 41 */
208 #define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2B Write protection page 42 */
209 #define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2B Write protection page 43 */
210 #define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2B Write protection page 44 */
211 #define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2B Write protection page 45 */
212 #define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2B Write protection page 46 */
213 #define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2B Write protection page 47 */
214 #define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2B Write protection page 48 */
215 #define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2B Write protection page 49 */
216 #define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2B Write protection page 50 */
217 #define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2B Write protection page 51 */
218 #define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2B Write protection page 52 */
219 #define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2B Write protection page 53 */
220 #define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2B Write protection page 54 */
221 #define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2B Write protection page 55 */
222 #define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2B Write protection page 56 */
223 #define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2B Write protection page 57 */
224 #define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2B Write protection page 58 */
225 #define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2B Write protection page 59 */
226 #define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2B Write protection page 60 */
227 #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2B Write protection page 61 */
228 #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2B Write protection page 62 */
229 #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2B Write protection page 63 */
230 #endif /* SYSCFG_SWPR2_PAGE36 */
231 /**
232 * @}
233 */
234
235 /** @defgroup SYSTEM_LL_EC_IM SYSCFG CPU1 INTERRUPT MASK
236 * @{
237 */
238 #define LL_SYSCFG_GRP1_TIM1 SYSCFG_IMR1_TIM1IM /*!< Enabling of interrupt from Timer 1 to CPU1 */
239 #if defined(TIM16)
240 #define LL_SYSCFG_GRP1_TIM16 SYSCFG_IMR1_TIM16IM /*!< Enabling of interrupt from Timer 16 to CPU1 */
241 #endif /* TIM16 */
242 #if defined(TIM17)
243 #define LL_SYSCFG_GRP1_TIM17 SYSCFG_IMR1_TIM17IM /*!< Enabling of interrupt from Timer 17 to CPU1 */
244 #endif /* TIM17 */
245
246 #define LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */
247 #define LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */
248 #define LL_SYSCFG_GRP1_EXTI7 SYSCFG_IMR1_EXTI7IM /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1 */
249 #define LL_SYSCFG_GRP1_EXTI8 SYSCFG_IMR1_EXTI8IM /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1 */
250 #define LL_SYSCFG_GRP1_EXTI9 SYSCFG_IMR1_EXTI9IM /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1 */
251 #define LL_SYSCFG_GRP1_EXTI10 SYSCFG_IMR1_EXTI10IM /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */
252 #define LL_SYSCFG_GRP1_EXTI11 SYSCFG_IMR1_EXTI11IM /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */
253 #define LL_SYSCFG_GRP1_EXTI12 SYSCFG_IMR1_EXTI12IM /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */
254 #define LL_SYSCFG_GRP1_EXTI13 SYSCFG_IMR1_EXTI13IM /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */
255 #define LL_SYSCFG_GRP1_EXTI14 SYSCFG_IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */
256 #define LL_SYSCFG_GRP1_EXTI15 SYSCFG_IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */
257
258 #if defined(SYSCFG_IMR2_PVM1IM)
259 #define LL_SYSCFG_GRP2_PVM1 SYSCFG_IMR2_PVM1IM /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU1 */
260 #endif /* SYSCFG_IMR2_PVM1IM */
261 #define LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */
262 #define LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */
263 /**
264 * @}
265 */
266
267 /** @defgroup SYSTEM_LL_EC_C2_IM SYSCFG CPU2 INTERRUPT MASK
268 * @{
269 */
270 #define LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers
271 and LSE Clock Security System to CPU2 */
272 #define LL_C2_SYSCFG_GRP1_RTCWKUP SYSCFG_C2IMR1_RTCWKUPIM /*!< Enabling of interrupt from RTC Wakeup to CPU2 */
273 #define LL_C2_SYSCFG_GRP1_RTCALARM SYSCFG_C2IMR1_RTCALARMIM /*!< Enabling of interrupt from RTC Alarms to CPU2 */
274 #define LL_C2_SYSCFG_GRP1_RCC SYSCFG_C2IMR1_RCCIM /*!< Enabling of interrupt from RCC to CPU2 */
275 #define LL_C2_SYSCFG_GRP1_FLASH SYSCFG_C2IMR1_FLASHIM /*!< Enabling of interrupt from FLASH to CPU2 */
276 #define LL_C2_SYSCFG_GRP1_PKA SYSCFG_C2IMR1_PKAIM /*!< Enabling of interrupt from Public Key Accelerator to CPU2 */
277 #define LL_C2_SYSCFG_GRP1_RNG SYSCFG_C2IMR1_RNGIM /*!< Enabling of interrupt from Random Number Generator to CPU2 */
278 #if defined(AES1)
279 #define LL_C2_SYSCFG_GRP1_AES1 SYSCFG_C2IMR1_AES1IM /*!< Enabling of interrupt from Advanced Encryption Standard 1 to CPU2 */
280 #endif /* AES1 */
281 #if defined(COMP1)
282 #define LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM /*!< Enabling of interrupt from Comparator to CPU2 */
283 #endif /* COMP1 */
284 #define LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */
285
286 #define LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */
287 #define LL_C2_SYSCFG_GRP1_EXTI1 SYSCFG_C2IMR1_EXTI1IM /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2 */
288 #define LL_C2_SYSCFG_GRP1_EXTI2 SYSCFG_C2IMR1_EXTI2IM /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2 */
289 #define LL_C2_SYSCFG_GRP1_EXTI3 SYSCFG_C2IMR1_EXTI3IM /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2 */
290 #define LL_C2_SYSCFG_GRP1_EXTI4 SYSCFG_C2IMR1_EXTI4IM /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2 */
291 #define LL_C2_SYSCFG_GRP1_EXTI5 SYSCFG_C2IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2 */
292 #define LL_C2_SYSCFG_GRP1_EXTI6 SYSCFG_C2IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2 */
293 #define LL_C2_SYSCFG_GRP1_EXTI7 SYSCFG_C2IMR1_EXTI7IM /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2 */
294 #define LL_C2_SYSCFG_GRP1_EXTI8 SYSCFG_C2IMR1_EXTI8IM /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2 */
295 #define LL_C2_SYSCFG_GRP1_EXTI9 SYSCFG_C2IMR1_EXTI9IM /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2 */
296 #define LL_C2_SYSCFG_GRP1_EXTI10 SYSCFG_C2IMR1_EXTI10IM /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */
297 #define LL_C2_SYSCFG_GRP1_EXTI11 SYSCFG_C2IMR1_EXTI11IM /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */
298 #define LL_C2_SYSCFG_GRP1_EXTI12 SYSCFG_C2IMR1_EXTI12IM /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */
299 #define LL_C2_SYSCFG_GRP1_EXTI13 SYSCFG_C2IMR1_EXTI13IM /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */
300 #define LL_C2_SYSCFG_GRP1_EXTI14 SYSCFG_C2IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */
301 #define LL_C2_SYSCFG_GRP1_EXTI15 SYSCFG_C2IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */
302
303 #define LL_C2_SYSCFG_GRP2_DMA1CH1 SYSCFG_C2IMR2_DMA1CH1IM /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2 */
304 #define LL_C2_SYSCFG_GRP2_DMA1CH2 SYSCFG_C2IMR2_DMA1CH2IM /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2 */
305 #define LL_C2_SYSCFG_GRP2_DMA1CH3 SYSCFG_C2IMR2_DMA1CH3IM /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2 */
306 #define LL_C2_SYSCFG_GRP2_DMA1CH4 SYSCFG_C2IMR2_DMA1CH4IM /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2 */
307 #define LL_C2_SYSCFG_GRP2_DMA1CH5 SYSCFG_C2IMR2_DMA1CH5IM /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2 */
308 #define LL_C2_SYSCFG_GRP2_DMA1CH6 SYSCFG_C2IMR2_DMA1CH6IM /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */
309 #define LL_C2_SYSCFG_GRP2_DMA1CH7 SYSCFG_C2IMR2_DMA1CH7IM /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */
310
311 #if defined(DMA2)
312 #define LL_C2_SYSCFG_GRP2_DMA2CH1 SYSCFG_C2IMR2_DMA2CH1IM /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2 */
313 #define LL_C2_SYSCFG_GRP2_DMA2CH2 SYSCFG_C2IMR2_DMA2CH2IM /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2 */
314 #define LL_C2_SYSCFG_GRP2_DMA2CH3 SYSCFG_C2IMR2_DMA2CH3IM /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2 */
315 #define LL_C2_SYSCFG_GRP2_DMA2CH4 SYSCFG_C2IMR2_DMA2CH4IM /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2 */
316 #define LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */
317 #define LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */
318 #define LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */
319 #endif /* DMA2 */
320
321 #define LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM /*!< Enabling of interrupt from DMAMUX1 to CPU2 */
322 #if defined(SYSCFG_C2IMR2_PVM1IM)
323 #define LL_C2_SYSCFG_GRP2_PVM1 SYSCFG_C2IMR2_PVM1IM /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU2 */
324 #endif /* SYSCFG_C2IMR2_PVM1IM */
325 #define LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */
326 #define LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */
327 #define LL_C2_SYSCFG_GRP2_TSC SYSCFG_C2IMR2_TSCIM /*!< Enabling of interrupt from Touch Sensing Controller to CPU2 */
328 #if defined(LCD)
329 #define LL_C2_SYSCFG_GRP2_LCD SYSCFG_C2IMR2_LCDIM /*!< Enabling of interrupt from Liquid Crystal Display to CPU2 */
330 #endif /* LCD */
331 /**
332 * @}
333 */
334
335 /** @defgroup SYSTEM_LL_EC_SECURE_IP_ACCESS SYSCFG SECURE IP ACCESS
336 * @{
337 */
338 #if defined(AES1)
339 #define LL_SYSCFG_SECURE_ACCESS_AES1 SYSCFG_SIPCR_SAES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
340 #endif /* AES1 */
341 #define LL_SYSCFG_SECURE_ACCESS_AES2 SYSCFG_SIPCR_SAES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */
342 #define LL_SYSCFG_SECURE_ACCESS_PKA SYSCFG_SIPCR_SPKA /*!< Enabling the security access of Public Key Accelerator */
343 #define LL_SYSCFG_SECURE_ACCESS_RNG SYSCFG_SIPCR_SRNG /*!< Enabling the security access of Random Number Generator */
344 /**
345 * @}
346 */
347
348 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU CPU1 APB1 GRP1 STOP IP
349 * @{
350 */
351 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted */
352 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */
353 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted */
354 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */
355 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */
356 #if defined(I2C3)
357 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */
358 #endif /* I2C3 */
359 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */
360 /**
361 * @}
362 */
363
364 /** @defgroup SYSTEM_LL_EC_C2_APB1_GRP1_STOP_IP DBGMCU CPU2 APB1 GRP1 STOP IP
365 * @{
366 */
367 #define LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted */
368 #define LL_C2_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */
369 #define LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */
370 #define LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */
371 #if defined(I2C3)
372 #define LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */
373 #endif /* I2C3 */
374 #define LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */
375 /**
376 * @}
377 */
378
379 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU CPU1 APB1 GRP2 STOP IP
380 * @{
381 */
382 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */
383 /**
384 * @}
385 */
386
387 /** @defgroup SYSTEM_LL_EC_C2_APB1_GRP2_STOP_IP DBGMCU CPU2 APB1 GRP2 STOP IP
388 * @{
389 */
390 #define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */
391 /**
392 * @}
393 */
394
395 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU CPU1 APB2 GRP1 STOP IP
396 * @{
397 */
398 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
399 #if defined(TIM16)
400 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
401 #endif /* TIM16 */
402 #if defined(TIM17)
403 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
404 #endif /* TIM17 */
405 /**
406 * @}
407 */
408
409 /** @defgroup SYSTEM_LL_EC_C2_APB2_GRP1_STOP_IP DBGMCU CPU2 APB2 GRP1 STOP IP
410 * @{
411 */
412 #define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
413 #if defined(TIM16)
414 #define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
415 #endif /* TIM16 */
416 #if defined(TIM17)
417 #define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
418 #endif /* TIM17 */
419 /**
420 * @}
421 */
422
423 #if defined(VREFBUF)
424 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
425 * @{
426 */
427 #define LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREF_OUT1) */
428 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
429 /**
430 * @}
431 */
432 #endif /* VREFBUF */
433
434 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
435 * @{
436 */
437 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
438 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
439 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
440 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
441
442 /**
443 * @}
444 */
445
446 /**
447 * @}
448 */
449
450 /* Exported macro ------------------------------------------------------------*/
451
452 /* Exported functions --------------------------------------------------------*/
453 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
454 * @{
455 */
456
457 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
458 * @{
459 */
460
461 /**
462 * @brief Set memory mapping at address 0x00000000
463 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
464 * @param Memory This parameter can be one of the following values:
465 * @arg @ref LL_SYSCFG_REMAP_FLASH
466 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
467 * @arg @ref LL_SYSCFG_REMAP_SRAM
468 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
469 * @retval None
470 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)471 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
472 {
473 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
474 }
475
476 /**
477 * @brief Get memory mapping at address 0x00000000
478 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
479 * @retval Returned value can be one of the following values:
480 * @arg @ref LL_SYSCFG_REMAP_FLASH
481 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
482 * @arg @ref LL_SYSCFG_REMAP_SRAM
483 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
484 */
LL_SYSCFG_GetRemapMemory(void)485 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
486 {
487 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
488 }
489
490 /**
491 * @brief Enable I/O analog switch voltage booster.
492 * @note When voltage booster is enabled, I/O analog switches are supplied
493 * by a dedicated voltage booster, from VDD power domain. This is
494 * the recommended configuration with low VDDA voltage operation.
495 * @note The I/O analog switch voltage booster is relevant for peripherals
496 * using I/O in analog input: ADC and COMP.
497 * However, COMP inputs have a high impedance and
498 * voltage booster do not impact performance significantly.
499 * Therefore, the voltage booster is mainly intended for
500 * usage with ADC.
501 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
502 * @retval None
503 */
LL_SYSCFG_EnableAnalogBooster(void)504 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
505 {
506 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
507 }
508
509 /**
510 * @brief Disable I/O analog switch voltage booster.
511 * @note When voltage booster is enabled, I/O analog switches are supplied
512 * by a dedicated voltage booster, from VDD power domain. This is
513 * the recommended configuration with low VDDA voltage operation.
514 * @note The I/O analog switch voltage booster is relevant for peripherals
515 * using I/O in analog input: ADC and COMP.
516 * However, COMP inputs have a high impedance and
517 * voltage booster do not impact performance significantly.
518 * Therefore, the voltage booster is mainly intended for
519 * usage with ADC.
520 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
521 * @retval None
522 */
LL_SYSCFG_DisableAnalogBooster(void)523 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
524 {
525 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
526 }
527
528 #if defined(SYSCFG_CFGR1_ANASWVDD)
529 /**
530 * @brief Enable the Analog GPIO switch to control voltage selection
531 * when the supply voltage is supplied by VDDA
532 * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogGpioSwitch
533 * @note Activating the gpio switch enable IOs analog switches supplied by VDDA
534 * @retval None
535 */
LL_SYSCFG_EnableAnalogGpioSwitch(void)536 __STATIC_INLINE void LL_SYSCFG_EnableAnalogGpioSwitch(void)
537 {
538 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
539 }
540
541 /**
542 * @brief Disable the Analog GPIO switch to control voltage selection
543 * when the supply voltage is supplied by VDDA
544 * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogGpioSwitch
545 * @note Activating the gpio switch enable IOs analog switches supplied by VDDA
546 * @retval None
547 */
LL_SYSCFG_DisableAnalogGpioSwitch(void)548 __STATIC_INLINE void LL_SYSCFG_DisableAnalogGpioSwitch(void)
549 {
550 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
551 }
552 #endif /* SYSCFG_CFGR1_ANASWVDD */
553
554 /**
555 * @brief Enable the I2C fast mode plus driving capability.
556 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
557 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
558 * @param ConfigFastModePlus This parameter can be a combination of the following values:
559 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
560 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
561 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
562 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
563 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
564 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
565 * @retval None
566 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)567 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
568 {
569 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
570 }
571
572 /**
573 * @brief Disable the I2C fast mode plus driving capability.
574 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
575 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
576 * @param ConfigFastModePlus This parameter can be a combination of the following values:
577 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
578 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
579 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
580 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
581 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
582 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
583 * @retval None
584 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)585 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
586 {
587 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
588 }
589
590 /**
591 * @brief Enable Floating Point Unit Invalid operation Interrupt
592 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
593 * @retval None
594 */
LL_SYSCFG_EnableIT_FPU_IOC(void)595 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
596 {
597 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
598 }
599
600 /**
601 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
602 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
603 * @retval None
604 */
LL_SYSCFG_EnableIT_FPU_DZC(void)605 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
606 {
607 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
608 }
609
610 /**
611 * @brief Enable Floating Point Unit Underflow Interrupt
612 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
613 * @retval None
614 */
LL_SYSCFG_EnableIT_FPU_UFC(void)615 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
616 {
617 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
618 }
619
620 /**
621 * @brief Enable Floating Point Unit Overflow Interrupt
622 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
623 * @retval None
624 */
LL_SYSCFG_EnableIT_FPU_OFC(void)625 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
626 {
627 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
628 }
629
630 /**
631 * @brief Enable Floating Point Unit Input denormal Interrupt
632 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
633 * @retval None
634 */
LL_SYSCFG_EnableIT_FPU_IDC(void)635 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
636 {
637 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
638 }
639
640 /**
641 * @brief Enable Floating Point Unit Inexact Interrupt
642 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
643 * @retval None
644 */
LL_SYSCFG_EnableIT_FPU_IXC(void)645 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
646 {
647 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
648 }
649
650 /**
651 * @brief Disable Floating Point Unit Invalid operation Interrupt
652 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
653 * @retval None
654 */
LL_SYSCFG_DisableIT_FPU_IOC(void)655 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
656 {
657 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
658 }
659
660 /**
661 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
662 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
663 * @retval None
664 */
LL_SYSCFG_DisableIT_FPU_DZC(void)665 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
666 {
667 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
668 }
669
670 /**
671 * @brief Disable Floating Point Unit Underflow Interrupt
672 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
673 * @retval None
674 */
LL_SYSCFG_DisableIT_FPU_UFC(void)675 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
676 {
677 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
678 }
679
680 /**
681 * @brief Disable Floating Point Unit Overflow Interrupt
682 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
683 * @retval None
684 */
LL_SYSCFG_DisableIT_FPU_OFC(void)685 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
686 {
687 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
688 }
689
690 /**
691 * @brief Disable Floating Point Unit Input denormal Interrupt
692 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
693 * @retval None
694 */
LL_SYSCFG_DisableIT_FPU_IDC(void)695 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
696 {
697 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
698 }
699
700 /**
701 * @brief Disable Floating Point Unit Inexact Interrupt
702 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
703 * @retval None
704 */
LL_SYSCFG_DisableIT_FPU_IXC(void)705 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
706 {
707 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
708 }
709
710 /**
711 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
712 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
713 * @retval State of bit (1 or 0).
714 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)715 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
716 {
717 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)) ? 1UL : 0UL);
718 }
719
720 /**
721 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
722 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
723 * @retval State of bit (1 or 0).
724 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)725 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
726 {
727 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)) ? 1UL : 0UL);
728 }
729
730 /**
731 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
732 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
733 * @retval State of bit (1 or 0).
734 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)735 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
736 {
737 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)) ? 1UL : 0UL);
738 }
739
740 /**
741 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
742 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
743 * @retval State of bit (1 or 0).
744 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)745 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
746 {
747 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)) ? 1UL : 0UL);
748 }
749
750 /**
751 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
752 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
753 * @retval State of bit (1 or 0).
754 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)755 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
756 {
757 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)) ? 1UL : 0UL);
758 }
759
760 /**
761 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
762 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
763 * @retval State of bit (1 or 0).
764 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)765 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
766 {
767 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
768 }
769
770
771 /**
772 * @brief Configure source input for the EXTI external interrupt.
773 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
774 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
775 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
776 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
777 * @param Port This parameter can be one of the following values:
778 * @arg @ref LL_SYSCFG_EXTI_PORTA
779 * @arg @ref LL_SYSCFG_EXTI_PORTB
780 * @arg @ref LL_SYSCFG_EXTI_PORTC
781 * @arg @ref LL_SYSCFG_EXTI_PORTD
782 * @arg @ref LL_SYSCFG_EXTI_PORTE
783 * @arg @ref LL_SYSCFG_EXTI_PORTH
784 *
785 * @param Line This parameter can be one of the following values:
786 * @arg @ref LL_SYSCFG_EXTI_LINE0
787 * @arg @ref LL_SYSCFG_EXTI_LINE1
788 * @arg @ref LL_SYSCFG_EXTI_LINE2
789 * @arg @ref LL_SYSCFG_EXTI_LINE3
790 * @arg @ref LL_SYSCFG_EXTI_LINE4
791 * @arg @ref LL_SYSCFG_EXTI_LINE5
792 * @arg @ref LL_SYSCFG_EXTI_LINE6
793 * @arg @ref LL_SYSCFG_EXTI_LINE7
794 * @arg @ref LL_SYSCFG_EXTI_LINE8
795 * @arg @ref LL_SYSCFG_EXTI_LINE9
796 * @arg @ref LL_SYSCFG_EXTI_LINE10
797 * @arg @ref LL_SYSCFG_EXTI_LINE11
798 * @arg @ref LL_SYSCFG_EXTI_LINE12
799 * @arg @ref LL_SYSCFG_EXTI_LINE13
800 * @arg @ref LL_SYSCFG_EXTI_LINE14
801 * @arg @ref LL_SYSCFG_EXTI_LINE15
802 * @retval None
803 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)804 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
805 {
806 MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> 16U), (Port << ((POSITION_VAL((Line >> 16U))) & 0x0000000FUL)));
807 }
808
809 /**
810 * @brief Get the configured defined for specific EXTI Line
811 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
812 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
813 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
814 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
815 * @param Line This parameter can be one of the following values:
816 * @arg @ref LL_SYSCFG_EXTI_LINE0
817 * @arg @ref LL_SYSCFG_EXTI_LINE1
818 * @arg @ref LL_SYSCFG_EXTI_LINE2
819 * @arg @ref LL_SYSCFG_EXTI_LINE3
820 * @arg @ref LL_SYSCFG_EXTI_LINE4
821 * @arg @ref LL_SYSCFG_EXTI_LINE5
822 * @arg @ref LL_SYSCFG_EXTI_LINE6
823 * @arg @ref LL_SYSCFG_EXTI_LINE7
824 * @arg @ref LL_SYSCFG_EXTI_LINE8
825 * @arg @ref LL_SYSCFG_EXTI_LINE9
826 * @arg @ref LL_SYSCFG_EXTI_LINE10
827 * @arg @ref LL_SYSCFG_EXTI_LINE11
828 * @arg @ref LL_SYSCFG_EXTI_LINE12
829 * @arg @ref LL_SYSCFG_EXTI_LINE13
830 * @arg @ref LL_SYSCFG_EXTI_LINE14
831 * @arg @ref LL_SYSCFG_EXTI_LINE15
832 * @retval Returned value can be one of the following values:
833 * @arg @ref LL_SYSCFG_EXTI_PORTA
834 * @arg @ref LL_SYSCFG_EXTI_PORTB
835 * @arg @ref LL_SYSCFG_EXTI_PORTC
836 * @arg @ref LL_SYSCFG_EXTI_PORTD
837 * @arg @ref LL_SYSCFG_EXTI_PORTE
838 * @arg @ref LL_SYSCFG_EXTI_PORTH
839 */
LL_SYSCFG_GetEXTISource(uint32_t Line)840 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
841 {
842 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x0000000FUL));
843 }
844
845 /**
846 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
847 * automatically cleared at the end of the SRAM2 erase operation.)
848 * @note This bit is write-protected: setting this bit is possible only after the
849 * correct key sequence is written in the SYSCFG_SKR register.
850 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
851 * @retval None
852 */
LL_SYSCFG_EnableSRAM2Erase(void)853 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
854 {
855 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
856 }
857
858 /**
859 * @brief Check if SRAM2 erase operation is on going
860 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
861 * @retval State of bit (1 or 0).
862 */
LL_SYSCFG_IsSRAM2EraseOngoing(void)863 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
864 {
865 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY)) ? 1UL : 0UL);
866 }
867
868 /**
869 * @brief Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware
870 * and will only be reset by a Hardware reset, including a reset after Standby.)
871 * @note Firmware writing 0 has no effect.
872 * @rmtoll SYSCFG_SCSR C2RFD LL_SYSCFG_DisableSRAMFetch
873 * @retval None
874 */
LL_SYSCFG_DisableSRAMFetch(void)875 __STATIC_INLINE void LL_SYSCFG_DisableSRAMFetch(void)
876 {
877 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_C2RFD);
878 }
879
880 /**
881 * @brief Check if CPU2 SRAM fetch is enabled
882 * @rmtoll SYSCFG_SCSR C2RFD LL_SYSCFG_IsEnabledSRAMFetch
883 * @retval State of bit (1 or 0).
884 */
LL_SYSCFG_IsEnabledSRAMFetch(void)885 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMFetch(void)
886 {
887 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_C2RFD) != (SYSCFG_SCSR_C2RFD)) ? 1UL : 0UL);
888 }
889
890 /**
891 * @brief Set connections to TIM1/16/17 Break inputs
892 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
893 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
894 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
895 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
896 * @param Break This parameter can be a combination of the following values:
897 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
898 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
899 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
900 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
901 * @retval None
902 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)903 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
904 {
905 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
906 }
907
908 /**
909 * @brief Get connections to TIM1/16/17 Break inputs
910 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
911 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
912 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
913 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
914 * @retval Returned value can be can be a combination of the following values:
915 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
916 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
917 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
918 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
919 */
LL_SYSCFG_GetTIMBreakInputs(void)920 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
921 {
922 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
923 }
924
925 /**
926 * @brief Check if SRAM2 parity error detected
927 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
928 * @retval State of bit (1 or 0).
929 */
LL_SYSCFG_IsActiveFlag_SP(void)930 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
931 {
932 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
933 }
934
935 /**
936 * @brief Clear SRAM2 parity error flag
937 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
938 * @retval None
939 */
LL_SYSCFG_ClearFlag_SP(void)940 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
941 {
942 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
943 }
944
945 /**
946 * @brief Enable SRAM2 page write protection for Pages in range 0 to 31
947 * @note Write protection is cleared only by a system reset
948 * @rmtoll SYSCFG_SWPR1 PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
949 * @param SRAM2WRP This parameter can be a combination of the following values:
950 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
951 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
952 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
953 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
954 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
955 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
956 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
957 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
958 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
959 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
960 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
961 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
962 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
963 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
964 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
965 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
966 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16
967 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17
968 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18
969 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19
970 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20
971 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21
972 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22
973 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23
974 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24
975 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25
976 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26
977 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27
978 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28
979 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29
980 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30
981 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31
982 * @retval None
983 */
984 /* Legacy define */
985 #define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)986 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
987 {
988 SET_BIT(SYSCFG->SWPR1, SRAM2WRP);
989 }
990
991 /**
992 * @brief Enable SRAM2 page write protection for Pages in range 32 to 63
993 * @note Write protection is cleared only by a system reset
994 * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
995 * @param SRAM2WRP This parameter can be a combination of the following values:
996 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32
997 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33
998 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34
999 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35
1000 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36
1001 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37
1002 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38
1003 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39
1004 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40
1005 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41
1006 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42
1007 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43
1008 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44
1009 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45
1010 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46
1011 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47
1012 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48
1013 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49
1014 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50
1015 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51
1016 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52
1017 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53
1018 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54
1019 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55
1020 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56
1021 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57
1022 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58
1023 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59
1024 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60
1025 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61
1026 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62
1027 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63
1028 * @retval None
1029 */
LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)1030 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
1031 {
1032 SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
1033 }
1034
1035 /**
1036 * @brief SRAM2 page write protection lock prior to erase
1037 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
1038 * @retval None
1039 */
LL_SYSCFG_LockSRAM2WRP(void)1040 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
1041 {
1042 /* Writing a wrong key reactivates the write protection */
1043 WRITE_REG(SYSCFG->SKR, 0x00U);
1044 }
1045
1046 /**
1047 * @brief SRAM2 page write protection unlock prior to erase
1048 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
1049 * @retval None
1050 */
LL_SYSCFG_UnlockSRAM2WRP(void)1051 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
1052 {
1053 /* unlock the write protection of the SRAM2ER bit */
1054 WRITE_REG(SYSCFG->SKR, 0xCAU);
1055 WRITE_REG(SYSCFG->SKR, 0x53U);
1056 }
1057
1058 /**
1059 * @brief Enable CPU1 Interrupt Mask
1060 * @rmtoll SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_EnableIT\n
1061 * SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_EnableIT\n
1062 * SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_EnableIT\n
1063 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_EnableIT
1064 * @param Interrupt This parameter can be a combination of the following values:
1065 * @arg @ref LL_SYSCFG_GRP1_TIM1
1066 * @arg @ref LL_SYSCFG_GRP1_TIM16
1067 * @arg @ref LL_SYSCFG_GRP1_TIM17
1068 * @arg @ref LL_SYSCFG_GRP1_EXTI5
1069 * @arg @ref LL_SYSCFG_GRP1_EXTI6
1070 * @arg @ref LL_SYSCFG_GRP1_EXTI7
1071 * @arg @ref LL_SYSCFG_GRP1_EXTI8
1072 * @arg @ref LL_SYSCFG_GRP1_EXTI9
1073 * @arg @ref LL_SYSCFG_GRP1_EXTI10
1074 * @arg @ref LL_SYSCFG_GRP1_EXTI11
1075 * @arg @ref LL_SYSCFG_GRP1_EXTI12
1076 * @arg @ref LL_SYSCFG_GRP1_EXTI13
1077 * @arg @ref LL_SYSCFG_GRP1_EXTI14
1078 * @arg @ref LL_SYSCFG_GRP1_EXTI15
1079 * @retval None
1080 */
LL_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)1081 __STATIC_INLINE void LL_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)
1082 {
1083 CLEAR_BIT(SYSCFG->IMR1, Interrupt);
1084 }
1085
1086 /**
1087 * @brief Enable CPU1 Interrupt Mask
1088 * @rmtoll SYSCFG_IMR1 PVM1IM LL_SYSCFG_GRP2_EnableIT\n
1089 * SYSCFG_IMR1 PVM3IM LL_SYSCFG_GRP2_EnableIT\n
1090 * SYSCFG_IMR1 PVDIM LL_SYSCFG_GRP2_EnableIT
1091 * @param Interrupt This parameter can be a combination of the following values:
1092 * @arg @ref LL_SYSCFG_GRP2_PVM1
1093 * @arg @ref LL_SYSCFG_GRP2_PVM3
1094 * @arg @ref LL_SYSCFG_GRP2_PVD
1095 * @retval None
1096 */
LL_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)1097 __STATIC_INLINE void LL_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)
1098 {
1099 CLEAR_BIT(SYSCFG->IMR2, Interrupt);
1100 }
1101
1102 /**
1103 * @brief Disable CPU1 Interrupt Mask
1104 * @rmtoll SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_DisableIT\n
1105 * SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_DisableIT\n
1106 * SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_DisableIT\n
1107 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_DisableIT
1108 * @param Interrupt This parameter can be a combination of the following values:
1109 * @arg @ref LL_SYSCFG_GRP1_TIM1
1110 * @arg @ref LL_SYSCFG_GRP1_TIM16
1111 * @arg @ref LL_SYSCFG_GRP1_TIM17
1112 * @arg @ref LL_SYSCFG_GRP1_EXTI5
1113 * @arg @ref LL_SYSCFG_GRP1_EXTI6
1114 * @arg @ref LL_SYSCFG_GRP1_EXTI7
1115 * @arg @ref LL_SYSCFG_GRP1_EXTI8
1116 * @arg @ref LL_SYSCFG_GRP1_EXTI9
1117 * @arg @ref LL_SYSCFG_GRP1_EXTI10
1118 * @arg @ref LL_SYSCFG_GRP1_EXTI11
1119 * @arg @ref LL_SYSCFG_GRP1_EXTI12
1120 * @arg @ref LL_SYSCFG_GRP1_EXTI13
1121 * @arg @ref LL_SYSCFG_GRP1_EXTI14
1122 * @arg @ref LL_SYSCFG_GRP1_EXTI15
1123 * @retval None
1124 */
LL_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)1125 __STATIC_INLINE void LL_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)
1126 {
1127 SET_BIT(SYSCFG->IMR1, Interrupt);
1128 }
1129
1130 /**
1131 * @brief Disable CPU1 Interrupt Mask
1132 * @rmtoll SYSCFG_IMR2 PVM1IM LL_SYSCFG_GRP2_DisableIT\n
1133 * SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_DisableIT\n
1134 * SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_DisableIT
1135 * @param Interrupt This parameter can be a combination of the following values:
1136 * @arg @ref LL_SYSCFG_GRP2_PVM1
1137 * @arg @ref LL_SYSCFG_GRP2_PVM3
1138 * @arg @ref LL_SYSCFG_GRP2_PVD
1139 * @retval None
1140 */
LL_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)1141 __STATIC_INLINE void LL_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)
1142 {
1143 SET_BIT(SYSCFG->IMR2, Interrupt);
1144 }
1145
1146 /**
1147 * @brief Indicate if CPU1 Interrupt Mask is enabled
1148 * @rmtoll SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_IsEnabledIT\n
1149 * SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_IsEnabledIT\n
1150 * SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_IsEnabledIT\n
1151 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_IsEnabledIT
1152 * @param Interrupt This parameter can be one of the following values:
1153 * @arg @ref LL_SYSCFG_GRP1_TIM1
1154 * @arg @ref LL_SYSCFG_GRP1_TIM16
1155 * @arg @ref LL_SYSCFG_GRP1_TIM17
1156 * @arg @ref LL_SYSCFG_GRP1_EXTI5
1157 * @arg @ref LL_SYSCFG_GRP1_EXTI6
1158 * @arg @ref LL_SYSCFG_GRP1_EXTI7
1159 * @arg @ref LL_SYSCFG_GRP1_EXTI8
1160 * @arg @ref LL_SYSCFG_GRP1_EXTI9
1161 * @arg @ref LL_SYSCFG_GRP1_EXTI10
1162 * @arg @ref LL_SYSCFG_GRP1_EXTI11
1163 * @arg @ref LL_SYSCFG_GRP1_EXTI12
1164 * @arg @ref LL_SYSCFG_GRP1_EXTI13
1165 * @arg @ref LL_SYSCFG_GRP1_EXTI14
1166 * @arg @ref LL_SYSCFG_GRP1_EXTI15
1167 * @retval State of bit (1 or 0).
1168 */
LL_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)1169 __STATIC_INLINE uint32_t LL_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)
1170 {
1171 return ((READ_BIT(SYSCFG->IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1172 }
1173
1174 /**
1175 * @brief Indicate if CPU1 Interrupt Mask is enabled
1176 * @rmtoll SYSCFG_IMR2 PVM1IM LL_SYSCFG_GRP2_IsEnabledIT\n
1177 * SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_IsEnabledIT\n
1178 * SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_IsEnabledIT
1179 * @param Interrupt This parameter can be one of the following values:
1180 * @arg @ref LL_SYSCFG_GRP2_PVM1
1181 * @arg @ref LL_SYSCFG_GRP2_PVM3
1182 * @arg @ref LL_SYSCFG_GRP2_PVD
1183 * @retval State of bit (1 or 0).
1184 */
LL_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)1185 __STATIC_INLINE uint32_t LL_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)
1186 {
1187 return ((READ_BIT(SYSCFG->IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1188 }
1189
1190 /**
1191 * @brief Enable CPU2 Interrupt Mask
1192 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_EnableIT\n
1193 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_EnableIT\n
1194 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_EnableIT\n
1195 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_EnableIT\n
1196 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_EnableIT\n
1197 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_EnableIT\n
1198 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_EnableIT\n
1199 * SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_EnableIT\n
1200 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_EnableIT\n
1201 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_EnableIT\n
1202 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_EnableIT
1203 * @param Interrupt This parameter can be a combination of the following values:
1204 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
1205 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
1206 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
1207 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
1208 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
1209 * @arg @ref LL_C2_SYSCFG_GRP1_PKA
1210 * @arg @ref LL_C2_SYSCFG_GRP1_RNG
1211 * @arg @ref LL_C2_SYSCFG_GRP1_AES1
1212 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
1213 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
1214 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
1215 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
1216 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
1217 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
1218 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
1219 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
1220 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
1221 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
1222 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
1223 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
1224 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
1225 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
1226 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
1227 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
1228 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
1229 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
1230 * @retval None
1231 */
LL_C2_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)1232 __STATIC_INLINE void LL_C2_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)
1233 {
1234 CLEAR_BIT(SYSCFG->C2IMR1, Interrupt);
1235 }
1236
1237 /**
1238 * @brief Enable CPU2 Interrupt Mask
1239 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_EnableIT\n
1240 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_EnableIT\n
1241 * SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_EnableIT\n
1242 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_EnableIT\n
1243 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_EnableIT\n
1244 * SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_EnableIT\n
1245 * SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_EnableIT
1246 * @param Interrupt This parameter can be a combination of the following values:
1247 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
1248 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
1249 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
1250 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
1251 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
1252 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
1253 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
1254 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
1255 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
1256 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
1257 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
1258 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
1259 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
1260 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
1261 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
1262 * @arg @ref LL_C2_SYSCFG_GRP2_PVM1
1263 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
1264 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
1265 * @arg @ref LL_C2_SYSCFG_GRP2_TSC
1266 * @arg @ref LL_C2_SYSCFG_GRP2_LCD
1267 * @retval None
1268 */
LL_C2_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)1269 __STATIC_INLINE void LL_C2_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)
1270 {
1271 CLEAR_BIT(SYSCFG->C2IMR2, Interrupt);
1272 }
1273
1274 /**
1275 * @brief Disable CPU2 Interrupt Mask
1276 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_DisableIT\n
1277 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_DisableIT\n
1278 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_DisableIT\n
1279 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_DisableIT\n
1280 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_DisableIT\n
1281 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_DisableIT\n
1282 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_DisableIT\n
1283 * SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_DisableIT\n
1284 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_DisableIT\n
1285 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_DisableIT\n
1286 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_DisableIT
1287 * @param Interrupt This parameter can be a combination of the following values:
1288 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
1289 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
1290 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
1291 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
1292 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
1293 * @arg @ref LL_C2_SYSCFG_GRP1_PKA
1294 * @arg @ref LL_C2_SYSCFG_GRP1_RNG
1295 * @arg @ref LL_C2_SYSCFG_GRP1_AES1
1296 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
1297 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
1298 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
1299 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
1300 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
1301 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
1302 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
1303 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
1304 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
1305 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
1306 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
1307 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
1308 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
1309 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
1310 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
1311 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
1312 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
1313 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
1314 * @retval None
1315 */
LL_C2_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)1316 __STATIC_INLINE void LL_C2_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)
1317 {
1318 SET_BIT(SYSCFG->C2IMR1, Interrupt);
1319 }
1320
1321 /**
1322 * @brief Disable CPU2 Interrupt Mask
1323 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_DisableIT\n
1324 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_DisableIT\n
1325 * SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_DisableIT\n
1326 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_DisableIT\n
1327 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_DisableIT\n
1328 * SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_DisableIT\n
1329 * SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_DisableIT
1330 * @param Interrupt This parameter can be a combination of the following values:
1331 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
1332 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
1333 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
1334 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
1335 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
1336 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
1337 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
1338 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
1339 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
1340 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
1341 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
1342 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
1343 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
1344 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
1345 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
1346 * @arg @ref LL_C2_SYSCFG_GRP2_PVM1
1347 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
1348 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
1349 * @arg @ref LL_C2_SYSCFG_GRP2_TSC
1350 * @arg @ref LL_C2_SYSCFG_GRP2_LCD
1351 * @retval None
1352 */
LL_C2_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)1353 __STATIC_INLINE void LL_C2_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)
1354 {
1355 SET_BIT(SYSCFG->C2IMR2, Interrupt);
1356 }
1357
1358 /**
1359 * @brief Indicate if CPU2 Interrupt Mask is enabled
1360 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_EnableIT\n
1361 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1362 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1363 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1364 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1365 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1366 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1367 * SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1368 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1369 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1370 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_IsEnabledIT
1371 * @param Interrupt This parameter can be one of the following values:
1372 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
1373 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
1374 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
1375 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
1376 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
1377 * @arg @ref LL_C2_SYSCFG_GRP1_PKA
1378 * @arg @ref LL_C2_SYSCFG_GRP1_RNG
1379 * @arg @ref LL_C2_SYSCFG_GRP1_AES1
1380 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
1381 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
1382 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
1383 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
1384 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
1385 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
1386 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
1387 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
1388 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
1389 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
1390 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
1391 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
1392 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
1393 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
1394 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
1395 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
1396 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
1397 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
1398 * @retval State of bit (1 or 0).
1399 */
LL_C2_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)1400 __STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)
1401 {
1402 return ((READ_BIT(SYSCFG->C2IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1403 }
1404
1405 /**
1406 * @brief Indicate if CPU2 Interrupt Mask is enabled
1407 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1408 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1409 * SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1410 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1411 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1412 * SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1413 * SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_IsEnabledIT
1414 * @param Interrupt This parameter can be one of the following values:
1415 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
1416 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
1417 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
1418 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
1419 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
1420 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
1421 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
1422 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
1423 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
1424 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
1425 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
1426 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
1427 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
1428 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
1429 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
1430 * @arg @ref LL_C2_SYSCFG_GRP2_PVM1
1431 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
1432 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
1433 * @arg @ref LL_C2_SYSCFG_GRP2_TSC
1434 * @arg @ref LL_C2_SYSCFG_GRP2_LCD
1435 * @retval State of bit (1 or 0).
1436 */
LL_C2_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)1437 __STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)
1438 {
1439 return ((READ_BIT(SYSCFG->C2IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1440 }
1441
1442 /**
1443 * @brief Enable the access for security IP
1444 * @rmtoll SYSCFG_SIPCR SAES1 LL_SYSCFG_EnableSecurityAccess\n
1445 * SYSCFG_CFGR1 SAES2 LL_SYSCFG_EnableSecurityAccess\n
1446 * SYSCFG_CFGR1 SPKA LL_SYSCFG_EnableSecurityAccess\n
1447 * SYSCFG_CFGR1 SRNG LL_SYSCFG_EnableSecurityAccess
1448 * @param SecurityAccess This parameter can be a combination of the following values:
1449 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
1450 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
1451 * @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
1452 * @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
1453 * @retval None
1454 */
LL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess)1455 __STATIC_INLINE void LL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess)
1456 {
1457 SET_BIT(SYSCFG->SIPCR, SecurityAccess);
1458 }
1459
1460 /**
1461 * @brief Disable the access for security IP
1462 * @rmtoll SYSCFG_SIPCR SAES1 LL_SYSCFG_DisableSecurityAccess\n
1463 * SYSCFG_CFGR1 SAES2 LL_SYSCFG_DisableSecurityAccess\n
1464 * SYSCFG_CFGR1 SPKA LL_SYSCFG_DisableSecurityAccess\n
1465 * SYSCFG_CFGR1 SRNG LL_SYSCFG_DisableSecurityAccess
1466 * @param SecurityAccess This parameter can be a combination of the following values:
1467 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
1468 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
1469 * @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
1470 * @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
1471 * @retval None
1472 */
LL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess)1473 __STATIC_INLINE void LL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess)
1474 {
1475 CLEAR_BIT(SYSCFG->SIPCR, SecurityAccess);
1476 }
1477
1478 /**
1479 * @brief Indicate if access for security IP is enabled
1480 * @rmtoll SYSCFG_SIPCR SAES1 LL_SYSCFG_IsEnabledSecurityAccess\n
1481 * SYSCFG_CFGR1 SAES2 LL_SYSCFG_IsEnabledSecurityAccess\n
1482 * SYSCFG_CFGR1 SPKA LL_SYSCFG_IsEnabledSecurityAccess\n
1483 * SYSCFG_CFGR1 SRNG LL_SYSCFG_IsEnabledSecurityAccess
1484 * @param SecurityAccess This parameter can be one of the following values:
1485 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
1486 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
1487 * @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
1488 * @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
1489 * @retval State of bit (1 or 0).
1490 */
LL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess)1491 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess)
1492 {
1493 return ((READ_BIT(SYSCFG->SIPCR, SecurityAccess) == (SecurityAccess)) ? 1UL : 0UL);
1494 }
1495
1496 /**
1497 * @}
1498 */
1499
1500 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1501 * @note DBGMCU is only accessible by Cortex M4
1502 * To access on DBGMCU, Cortex M0+ need to request to the Cortex M4
1503 * the action.
1504 * @{
1505 */
1506
1507 /**
1508 * @brief Return the device identifier
1509 * @note For STM32WBxxxx devices, the device ID is 0x495
1510 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1511 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495)
1512 */
LL_DBGMCU_GetDeviceID(void)1513 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1514 {
1515 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1516 }
1517
1518 /**
1519 * @brief Return the device revision identifier
1520 * @note This field indicates the revision of the device.
1521 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1522 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1523 */
LL_DBGMCU_GetRevisionID(void)1524 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1525 {
1526 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1527 }
1528
1529 /**
1530 * @brief Enable the Debug Module during SLEEP mode
1531 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1532 * @retval None
1533 */
LL_DBGMCU_EnableDBGSleepMode(void)1534 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1535 {
1536 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1537 }
1538
1539 /**
1540 * @brief Disable the Debug Module during SLEEP mode
1541 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1542 * @retval None
1543 */
LL_DBGMCU_DisableDBGSleepMode(void)1544 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1545 {
1546 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1547 }
1548
1549 /**
1550 * @brief Enable the Debug Module during STOP mode
1551 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1552 * @retval None
1553 */
LL_DBGMCU_EnableDBGStopMode(void)1554 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1555 {
1556 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1557 }
1558
1559 /**
1560 * @brief Disable the Debug Module during STOP mode
1561 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1562 * @retval None
1563 */
LL_DBGMCU_DisableDBGStopMode(void)1564 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1565 {
1566 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1567 }
1568
1569 /**
1570 * @brief Enable the Debug Module during STANDBY mode
1571 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1572 * @retval None
1573 */
LL_DBGMCU_EnableDBGStandbyMode(void)1574 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1575 {
1576 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1577 }
1578
1579 /**
1580 * @brief Disable the Debug Module during STANDBY mode
1581 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1582 * @retval None
1583 */
LL_DBGMCU_DisableDBGStandbyMode(void)1584 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1585 {
1586 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1587 }
1588
1589 /**
1590 * @brief Enable the clock for Trace port
1591 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock\n
1592 */
LL_DBGMCU_EnableTraceClock(void)1593 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
1594 {
1595 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN);
1596 }
1597
1598 /**
1599 * @brief Disable the clock for Trace port
1600 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock\n
1601 * @retval None
1602 */
LL_DBGMCU_DisableTraceClock(void)1603 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
1604 {
1605 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN);
1606 }
1607
1608 /**
1609 * @brief Indicate if the clock for Trace port is enabled
1610 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock\n
1611 * @retval State of bit (1 or 0).
1612 */
LL_DBGMCU_IsEnabledTraceClock(void)1613 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
1614 {
1615 return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN) == (DBGMCU_CR_TRACE_IOEN)) ? 1UL : 0UL);
1616 }
1617
1618 /**
1619 * @brief Enable the external trigger output
1620 * @note When enable the external trigger is output (state of bit 1),
1621 * TRGIO pin is connected to TRGOUT.
1622 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_EnableTriggerOutput\n
1623 */
LL_DBGMCU_EnableTriggerOutput(void)1624 __STATIC_INLINE void LL_DBGMCU_EnableTriggerOutput(void)
1625 {
1626 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN);
1627 }
1628
1629 /**
1630 * @brief Disable the external trigger output
1631 * @note When disable external trigger is input (state of bit 0),
1632 * TRGIO pin is connected to TRGIN.
1633 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_DisableTriggerOutput\n
1634 * @retval None
1635 */
LL_DBGMCU_DisableTriggerOutput(void)1636 __STATIC_INLINE void LL_DBGMCU_DisableTriggerOutput(void)
1637 {
1638 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN);
1639 }
1640
1641 /**
1642 * @brief Indicate if the external trigger is output or input direction
1643 * @note When the external trigger is output (state of bit 1),
1644 * TRGIO pin is connected to TRGOUT.
1645 * When the external trigger is input (state of bit 0),
1646 * TRGIO pin is connected to TRGIN.
1647 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_EnableTriggerOutput\n
1648 * @retval State of bit (1 or 0).
1649 */
LL_DBGMCU_IsEnabledTriggerOutput(void)1650 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTriggerOutput(void)
1651 {
1652 return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN) == (DBGMCU_CR_TRGOEN)) ? 1UL : 0UL);
1653 }
1654
1655 /**
1656 * @brief Freeze CPU1 APB1 peripherals (group1 peripherals)
1657 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1658 * @param Periphs This parameter can be a combination of the following values:
1659 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1660 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1661 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1662 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1663 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1664 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1665 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1666 * @retval None
1667 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1668 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1669 {
1670 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1671 }
1672
1673 /**
1674 * @brief Freeze CPU2 APB1 peripherals (group1 peripherals)
1675 * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_FreezePeriph
1676 * @param Periphs This parameter can be a combination of the following values:
1677 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
1678 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
1679 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
1680 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
1681 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
1682 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
1683 * @retval None
1684 */
LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1685 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1686 {
1687 SET_BIT(DBGMCU->C2APB1FZR1, Periphs);
1688 }
1689
1690 /**
1691 * @brief Freeze CPU1 APB1 peripherals (group2 peripherals)
1692 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1693 * @param Periphs This parameter can be a combination of the following values:
1694 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1695 * @retval None
1696 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1697 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1698 {
1699 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1700 }
1701
1702 /**
1703 * @brief Freeze CPU2 APB1 peripherals (group2 peripherals)
1704 * @rmtoll DBGMCU_C2APB1FZR2 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP2_FreezePeriph
1705 * @param Periphs This parameter can be a combination of the following values:
1706 * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
1707 * @retval None
1708 */
LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1709 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1710 {
1711 SET_BIT(DBGMCU->C2APB1FZR2, Periphs);
1712 }
1713
1714 /**
1715 * @brief Unfreeze CPU1 APB1 peripherals (group1 peripherals)
1716 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1717 * @param Periphs This parameter can be a combination of the following values:
1718 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1719 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1720 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1721 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1722 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1723 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1724 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1725 * @retval None
1726 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1727 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1728 {
1729 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1730 }
1731
1732 /**
1733 * @brief Unfreeze CPU2 APB1 peripherals (group1 peripherals)
1734 * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph
1735 * @param Periphs This parameter can be a combination of the following values:
1736 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
1737 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
1738 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
1739 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
1740 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
1741 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
1742 * @retval None
1743 */
LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1744 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1745 {
1746 CLEAR_BIT(DBGMCU->C2APB1FZR1, Periphs);
1747 }
1748
1749 /**
1750 * @brief Unfreeze CPU1 APB1 peripherals (group2 peripherals)
1751 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1752 * @param Periphs This parameter can be a combination of the following values:
1753 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1754 * @retval None
1755 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1756 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1757 {
1758 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1759 }
1760
1761 /**
1762 * @brief Unfreeze CPU2 APB1 peripherals (group2 peripherals)
1763 * @rmtoll DBGMCU_C2APB1FZR2 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph
1764 * @param Periphs This parameter can be a combination of the following values:
1765 * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
1766 * @retval None
1767 */
LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1768 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1769 {
1770 CLEAR_BIT(DBGMCU->C2APB1FZR2, Periphs);
1771 }
1772
1773 /**
1774 * @brief Freeze CPU1 APB2 peripherals
1775 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1776 * @param Periphs This parameter can be a combination of the following values:
1777 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1778 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1779 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1780 * @retval None
1781 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1782 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1783 {
1784 SET_BIT(DBGMCU->APB2FZR, Periphs);
1785 }
1786
1787 /**
1788 * @brief Freeze CPU2 APB2 peripherals
1789 * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_FreezePeriph
1790 * @param Periphs This parameter can be a combination of the following values:
1791 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
1792 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
1793 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
1794 * @retval None
1795 */
LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1796 __STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1797 {
1798 SET_BIT(DBGMCU->C2APB2FZR, Periphs);
1799 }
1800
1801 /**
1802 * @brief Unfreeze CPU1 APB2 peripherals
1803 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1804 * @param Periphs This parameter can be a combination of the following values:
1805 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1806 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1807 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1808 * @retval None
1809 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1810 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1811 {
1812 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1813 }
1814
1815 /**
1816 * @brief Unfreeze CPU2 APB2 peripherals
1817 * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph
1818 * @param Periphs This parameter can be a combination of the following values:
1819 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
1820 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
1821 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
1822 * @retval None
1823 */
LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1824 __STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1825 {
1826 CLEAR_BIT(DBGMCU->C2APB2FZR, Periphs);
1827 }
1828
1829 /**
1830 * @}
1831 */
1832
1833 #if defined(VREFBUF)
1834 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1835 * @{
1836 */
1837
1838 /**
1839 * @brief Enable Internal voltage reference
1840 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1841 * @retval None
1842 */
LL_VREFBUF_Enable(void)1843 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1844 {
1845 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1846 }
1847
1848 /**
1849 * @brief Disable Internal voltage reference
1850 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1851 * @retval None
1852 */
LL_VREFBUF_Disable(void)1853 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1854 {
1855 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1856 }
1857
1858 /**
1859 * @brief Enable high impedance (VREF+pin is high impedance)
1860 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1861 * @retval None
1862 */
LL_VREFBUF_EnableHIZ(void)1863 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1864 {
1865 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1866 }
1867
1868 /**
1869 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1870 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1871 * @retval None
1872 */
LL_VREFBUF_DisableHIZ(void)1873 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1874 {
1875 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1876 }
1877
1878 /**
1879 * @brief Set the Voltage reference scale
1880 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1881 * @param Scale This parameter can be one of the following values:
1882 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1883 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1884 * @retval None
1885 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1886 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1887 {
1888 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1889 }
1890
1891 /**
1892 * @brief Get the Voltage reference scale
1893 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1894 * @retval Returned value can be one of the following values:
1895 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1896 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1897 */
LL_VREFBUF_GetVoltageScaling(void)1898 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1899 {
1900 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1901 }
1902
1903 /**
1904 * @brief Get the VREFBUF trimming value for VRS=0 (VREF_SC0)
1905 * @retval Between 0 and 0x3F
1906 */
LL_VREFBUF_SC0_GetCalibration(void)1907 __STATIC_INLINE uint32_t LL_VREFBUF_SC0_GetCalibration(void)
1908 {
1909 return (uint32_t)(*VREFBUF_SC0_CAL_ADDR);
1910 }
1911
1912 /**
1913 * @brief Get the VREFBUF trimming value for VRS=1 (VREF_SC1)
1914 * @retval Between 0 and 0x3F
1915 */
LL_VREFBUF_SC1_GetCalibration(void)1916 __STATIC_INLINE uint32_t LL_VREFBUF_SC1_GetCalibration(void)
1917 {
1918 return (uint32_t)(*VREFBUF_SC1_CAL_ADDR);
1919 }
1920
1921 /**
1922 * @brief Check if Voltage reference buffer is ready
1923 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1924 * @retval State of bit (1 or 0).
1925 */
LL_VREFBUF_IsVREFReady(void)1926 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1927 {
1928 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
1929 }
1930
1931 /**
1932 * @brief Get the trimming code for VREFBUF calibration
1933 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1934 * @retval Between 0 and 0x3F
1935 */
LL_VREFBUF_GetTrimming(void)1936 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1937 {
1938 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1939 }
1940
1941 /**
1942 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1943 * @note Each VrefBuf voltage scale is calibrated in production for each device,
1944 * data stored in flash memory.
1945 * Functions @ref LL_VREFBUF_SC0_GetCalibration and
1946 * @ref LL_VREFBUF_SC0_GetCalibration can be used to retrieve
1947 * these calibration data.
1948 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1949 * @param Value Between 0 and 0x3F
1950 * @retval None
1951 */
LL_VREFBUF_SetTrimming(uint32_t Value)1952 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1953 {
1954 WRITE_REG(VREFBUF->CCR, Value);
1955 }
1956
1957 /**
1958 * @}
1959 */
1960 #endif /* VREFBUF */
1961
1962 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1963 * @{
1964 */
1965
1966 /**
1967 * @brief Set FLASH Latency
1968 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1969 * @param Latency This parameter can be one of the following values:
1970 * @arg @ref LL_FLASH_LATENCY_0
1971 * @arg @ref LL_FLASH_LATENCY_1
1972 * @arg @ref LL_FLASH_LATENCY_2
1973 * @arg @ref LL_FLASH_LATENCY_3
1974 * @retval None
1975 */
LL_FLASH_SetLatency(uint32_t Latency)1976 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1977 {
1978 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1979 }
1980
1981 /**
1982 * @brief Get FLASH Latency
1983 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1984 * @retval Returned value can be one of the following values:
1985 * @arg @ref LL_FLASH_LATENCY_0
1986 * @arg @ref LL_FLASH_LATENCY_1
1987 * @arg @ref LL_FLASH_LATENCY_2
1988 * @arg @ref LL_FLASH_LATENCY_3
1989 */
LL_FLASH_GetLatency(void)1990 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1991 {
1992 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1993 }
1994
1995 /**
1996 * @brief Enable Prefetch
1997 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1998 * @retval None
1999 */
LL_FLASH_EnablePrefetch(void)2000 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
2001 {
2002 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
2003 }
2004
2005 /**
2006 * @brief Disable Prefetch
2007 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
2008 * @rmtoll FLASH_C2ACR PRFTEN LL_FLASH_DisablePrefetch
2009 * @retval None
2010 */
LL_FLASH_DisablePrefetch(void)2011 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
2012 {
2013 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
2014 }
2015
2016 /**
2017 * @brief Check if Prefetch buffer is enabled
2018 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
2019 * @rmtoll FLASH_C2ACR C2PRFTEN LL_FLASH_IsPrefetchEnabled
2020 * @retval State of bit (1 or 0).
2021 */
LL_FLASH_IsPrefetchEnabled(void)2022 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
2023 {
2024 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
2025 }
2026
2027 /**
2028 * @brief Enable Instruction cache
2029 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
2030 * @rmtoll FLASH_C2ACR ICEN LL_FLASH_EnableInstCache
2031 * @retval None
2032 */
LL_FLASH_EnableInstCache(void)2033 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
2034 {
2035 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
2036 }
2037
2038 /**
2039 * @brief Disable Instruction cache
2040 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
2041 * @rmtoll FLASH_C2ACR ICEN LL_FLASH_DisableInstCache
2042 * @retval None
2043 */
LL_FLASH_DisableInstCache(void)2044 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
2045 {
2046 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
2047 }
2048
2049 /**
2050 * @brief Enable Data cache
2051 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
2052 * @retval None
2053 */
LL_FLASH_EnableDataCache(void)2054 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
2055 {
2056 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
2057 }
2058
2059 /**
2060 * @brief Disable Data cache
2061 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
2062 * @retval None
2063 */
LL_FLASH_DisableDataCache(void)2064 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
2065 {
2066 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
2067 }
2068
2069 /**
2070 * @brief Enable Instruction cache reset
2071 * @note bit can be written only when the instruction cache is disabled
2072 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
2073 * @rmtoll FLASH_C2ACR ICRST LL_FLASH_EnableInstCacheReset
2074 * @retval None
2075 */
LL_FLASH_EnableInstCacheReset(void)2076 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
2077 {
2078 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
2079 }
2080
2081 /**
2082 * @brief Disable Instruction cache reset
2083 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
2084 * @rmtoll FLASH_C2ACR ICRST LL_FLASH_DisableInstCacheReset
2085 * @retval None
2086 */
LL_FLASH_DisableInstCacheReset(void)2087 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
2088 {
2089 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
2090 }
2091
2092 /**
2093 * @brief Enable Data cache reset
2094 * @note bit can be written only when the data cache is disabled
2095 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
2096 * @retval None
2097 */
LL_FLASH_EnableDataCacheReset(void)2098 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
2099 {
2100 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
2101 }
2102
2103 /**
2104 * @brief Disable Data cache reset
2105 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
2106 * @retval None
2107 */
LL_FLASH_DisableDataCacheReset(void)2108 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
2109 {
2110 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
2111 }
2112
2113 /**
2114 * @brief Suspend new program or erase operation request
2115 * @note Any new Flash program and erase operation on both CPU side will be suspended
2116 * until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are
2117 * cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash
2118 * CPU2 status register (FLASH_C2SR) register will be set when at least one PES
2119 * bit in FLASH_ACR or FLASH_C2ACR is set.
2120 * @rmtoll FLASH_ACR PES LL_FLASH_SuspendOperation
2121 * @rmtoll FLASH_C2ACR PES LL_FLASH_SuspendOperation
2122 * @retval None
2123 */
LL_FLASH_SuspendOperation(void)2124 __STATIC_INLINE void LL_FLASH_SuspendOperation(void)
2125 {
2126 SET_BIT(FLASH->ACR, FLASH_ACR_PES);
2127 }
2128
2129 /**
2130 * @brief Allow new program or erase operation request
2131 * @note Any new Flash program and erase operation on both CPU side will be allowed
2132 * until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is
2133 * set. The PESD bit in both the Flash status register (FLASH_SR) and Flash
2134 * CPU2 status register (FLASH_C2SR) register will be clear when both PES
2135 * bit in FLASH_ACR or FLASH_C2ACR is cleared.
2136 * @rmtoll FLASH_ACR PES LL_FLASH_AllowOperation
2137 * @rmtoll FLASH_C2ACR PES LL_FLASH_AllowOperation
2138 * @retval None
2139 */
LL_FLASH_AllowOperation(void)2140 __STATIC_INLINE void LL_FLASH_AllowOperation(void)
2141 {
2142 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PES);
2143 }
2144
2145 /**
2146 * @brief Check if new program or erase operation request from CPU2 is suspended
2147 * @rmtoll FLASH_ACR PES LL_FLASH_IsOperationSuspended
2148 * @rmtoll FLASH_C2ACR PES LL_FLASH_IsOperationSuspended
2149 * @retval State of bit (1 or 0).
2150 */
LL_FLASH_IsOperationSuspended(void)2151 __STATIC_INLINE uint32_t LL_FLASH_IsOperationSuspended(void)
2152 {
2153 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PES) == (FLASH_ACR_PES)) ? 1UL : 0UL);
2154 }
2155
2156 /**
2157 * @brief Check if new program or erase operation request from CPU1 or CPU2 is suspended
2158 * @rmtoll FLASH_SR PESD LL_FLASH_IsActiveFlag_OperationSuspended
2159 * @rmtoll FLASH_C2SR PESD LL_FLASH_IsActiveFlag_OperationSuspended
2160 * @retval State of bit (1 or 0).
2161 */
LL_FLASH_IsActiveFlag_OperationSuspended(void)2162 __STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OperationSuspended(void)
2163 {
2164 return ((READ_BIT(FLASH->SR, FLASH_SR_PESD) == (FLASH_SR_PESD)) ? 1UL : 0UL);
2165 }
2166
2167 /**
2168 * @brief Set EMPTY flag information as Flash User area empty
2169 * @rmtoll FLASH_ACR EMPTY LL_FLASH_SetEmptyFlag
2170 * @retval None
2171 */
LL_FLASH_SetEmptyFlag(void)2172 __STATIC_INLINE void LL_FLASH_SetEmptyFlag(void)
2173 {
2174 SET_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
2175 }
2176
2177 /**
2178 * @brief Clear EMPTY flag information as Flash User area programmed
2179 * @rmtoll FLASH_ACR EMPTY LL_FLASH_ClearEmptyFlag
2180 * @retval None
2181 */
LL_FLASH_ClearEmptyFlag(void)2182 __STATIC_INLINE void LL_FLASH_ClearEmptyFlag(void)
2183 {
2184 CLEAR_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
2185 }
2186
2187 /**
2188 * @brief Check if the EMPTY flag is set or reset
2189 * @rmtoll FLASH_ACR EMPTY LL_FLASH_IsEmptyFlag
2190 * @retval State of bit (1 or 0).
2191 */
LL_FLASH_IsEmptyFlag(void)2192 __STATIC_INLINE uint32_t LL_FLASH_IsEmptyFlag(void)
2193 {
2194 return ((READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY) == FLASH_ACR_EMPTY) ? 1UL : 0UL);
2195 }
2196
2197 /**
2198 * @brief Get IPCC buffer base address
2199 * @rmtoll FLASH_IPCCBR IPCCDBA LL_FLASH_GetIPCCBufferAddr
2200 * @retval IPCC data buffer base address offset
2201 */
LL_FLASH_GetIPCCBufferAddr(void)2202 __STATIC_INLINE uint32_t LL_FLASH_GetIPCCBufferAddr(void)
2203 {
2204 return (uint32_t)(READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA));
2205 }
2206
2207 /**
2208 * @brief Get CPU2 boot reset vector
2209 * @rmtoll FLASH_SRRVR SBRV LL_FLASH_GetC2BootResetVect
2210 * @retval CPU2 boot reset vector
2211 */
LL_FLASH_GetC2BootResetVect(void)2212 __STATIC_INLINE uint32_t LL_FLASH_GetC2BootResetVect(void)
2213 {
2214 return (uint32_t)(READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV));
2215 }
2216
2217 /**
2218 * @brief Return the Unique Device Number
2219 * @note The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
2220 * 802.15.4 64-bit Device Address EUI-64.
2221 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
2222 */
LL_FLASH_GetUDN(void)2223 __STATIC_INLINE uint32_t LL_FLASH_GetUDN(void)
2224 {
2225 return (uint32_t)(READ_REG(*((uint32_t *)UID64_BASE)));
2226 }
2227
2228 /**
2229 * @brief Return the Device ID
2230 * @note The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
2231 * 802.15.4 64-bit Device Address EUI-64.
2232 * For STM32WBxxxx devices, the device ID is 0x26
2233 * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x26 for STM32WB55x)
2234 */
LL_FLASH_GetDeviceID(void)2235 __STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void)
2236 {
2237 return (uint32_t)((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU);
2238 }
2239
2240 /**
2241 * @brief Return the ST Company ID
2242 * @note The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
2243 * 802.15.4 64-bit Device Address EUI-64.
2244 * For STM32WBxxxx devices, the ST Company ID is 0x0080E1
2245 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Company ID is 0x0080E1)
2246 */
LL_FLASH_GetSTCompanyID(void)2247 __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void)
2248 {
2249 return (uint32_t)(((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U) & 0x00FFFFFFU);
2250 }
2251 /**
2252 * @}
2253 */
2254
2255 /**
2256 * @}
2257 */
2258
2259 /**
2260 * @}
2261 */
2262
2263 /**
2264 * @}
2265 */
2266
2267 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
2268
2269 /**
2270 * @}
2271 */
2272
2273 #ifdef __cplusplus
2274 }
2275 #endif
2276
2277 #endif /* STM32WBxx_LL_SYSTEM_H */
2278
