1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef STM32L4xx_LL_BUS_H
37 #define STM32L4xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32l4xx.h"
45
46 /** @addtogroup STM32L4xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58
59 /* Private constants ---------------------------------------------------------*/
60
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
74 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
75 #if defined(DMAMUX1)
76 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
77 #endif /* DMAMUX1 */
78 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
79 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
80 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
81 #if defined(DMA2D)
82 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
83 #endif /* DMA2D */
84 #if defined(GFXMMU)
85 #define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN
86 #endif /* GFXMMU */
87 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
88 /**
89 * @}
90 */
91
92 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
93 * @{
94 */
95 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
96 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
97 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
98 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
99 #if defined(GPIOD)
100 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
101 #endif /*GPIOD*/
102 #if defined(GPIOE)
103 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
104 #endif /*GPIOE*/
105 #if defined(GPIOF)
106 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
107 #endif /* GPIOF */
108 #if defined(GPIOG)
109 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
110 #endif /* GPIOG */
111 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
112 #if defined(GPIOI)
113 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
114 #endif /* GPIOI */
115 #if defined(USB_OTG_FS)
116 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
117 #endif /* USB_OTG_FS */
118 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
119 #if defined(DCMI)
120 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
121 #endif /* DCMI */
122 #if defined(AES)
123 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
124 #endif /* AES */
125 #if defined(HASH)
126 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
127 #endif /* HASH */
128 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
129 #if defined(OCTOSPIM)
130 #define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN
131 #endif /* OCTOSPIM */
132 #if defined(PKA)
133 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN
134 #endif /* PKA */
135 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
136 #define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN
137 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
138 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
139 #if defined(SRAM3_BASE)
140 #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN
141 #endif /* SRAM3_BASE */
142 /**
143 * @}
144 */
145
146 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
147 * @{
148 */
149 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
150 #if defined(FMC_Bank1_R)
151 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
152 #endif /* FMC_Bank1_R */
153 #if defined(QUADSPI)
154 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
155 #endif /* QUADSPI */
156 #if defined(OCTOSPI1)
157 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
158 #endif /* OCTOSPI1 */
159 #if defined(OCTOSPI2)
160 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
161 #endif /* OCTOSPI2 */
162 /**
163 * @}
164 */
165
166 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
167 * @{
168 */
169 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
170 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
171 #if defined(TIM3)
172 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
173 #endif /* TIM3 */
174 #if defined(TIM4)
175 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
176 #endif /* TIM4 */
177 #if defined(TIM5)
178 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
179 #endif /* TIM5 */
180 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
181 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
182 #if defined(LCD)
183 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
184 #endif /* LCD */
185 #if defined(RCC_APB1ENR1_RTCAPBEN)
186 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
187 #endif /* RCC_APB1ENR1_RTCAPBEN */
188 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
189 #if defined(SPI2)
190 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
191 #endif /* SPI2 */
192 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
193 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
194 #if defined(USART3)
195 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
196 #endif /* USART3 */
197 #if defined(UART4)
198 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
199 #endif /* UART4 */
200 #if defined(UART5)
201 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
202 #endif /* UART5 */
203 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
204 #if defined(I2C2)
205 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
206 #endif /* I2C2 */
207 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
208 #if defined(CRS)
209 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
210 #endif /* CRS */
211 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
212 #if defined(CAN2)
213 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN
214 #endif /* CAN2 */
215 #if defined(USB)
216 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
217 #endif /* USB */
218 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
219 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
220 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
221 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
222 /**
223 * @}
224 */
225
226
227 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
228 * @{
229 */
230 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
231 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
232 #if defined(I2C4)
233 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
234 #endif /* I2C4 */
235 #if defined(SWPMI1)
236 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
237 #endif /* SWPMI1 */
238 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
239 /**
240 * @}
241 */
242
243 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
244 * @{
245 */
246 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
247 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
248 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
249 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
250 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
251 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
252 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
253 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
254 #if defined(TIM8)
255 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
256 #endif /* TIM8 */
257 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
258 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
259 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
260 #if defined(TIM17)
261 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
262 #endif /* TIM17 */
263 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
264 #if defined(SAI2)
265 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
266 #endif /* SAI2 */
267 #if defined(DFSDM1_Channel0)
268 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
269 #endif /* DFSDM1_Channel0 */
270 #if defined(LTDC)
271 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
272 #endif /* LTDC */
273 #if defined(DSI)
274 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
275 #endif /* DSI */
276 /**
277 * @}
278 */
279
280 /** Legacy definitions for compatibility purpose
281 @cond 0
282 */
283 #if defined(DFSDM1_Channel0)
284 #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
285 #endif /* DFSDM1_Channel0 */
286 /**
287 @endcond
288 */
289
290 /**
291 * @}
292 */
293
294 /* Exported macro ------------------------------------------------------------*/
295 /* Exported functions --------------------------------------------------------*/
296 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
297 * @{
298 */
299
300 /** @defgroup BUS_LL_EF_AHB1 AHB1
301 * @{
302 */
303
304 /**
305 * @brief Enable AHB1 peripherals clock.
306 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
307 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
308 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
309 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
310 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
311 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
312 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
313 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock
314 * @param Periphs This parameter can be a combination of the following values:
315 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
316 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
317 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
318 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
319 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
320 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
321 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
322 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
323 *
324 * (*) value not defined in all devices.
325 * @retval None
326 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)327 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
328 {
329 __IO uint32_t tmpreg;
330 SET_BIT(RCC->AHB1ENR, Periphs);
331 /* Delay after an RCC peripheral clock enabling */
332 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
333 (void)tmpreg;
334 }
335
336 /**
337 * @brief Check if AHB1 peripheral clock is enabled or not
338 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
339 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
340 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
341 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
342 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
343 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
344 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
345 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock
346 * @param Periphs This parameter can be a combination of the following values:
347 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
348 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
349 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
350 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
351 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
352 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
353 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
354 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
355 *
356 * (*) value not defined in all devices.
357 * @retval State of Periphs (1 or 0).
358 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)359 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
360 {
361 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
362 }
363
364 /**
365 * @brief Disable AHB1 peripherals clock.
366 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
367 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
368 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
369 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
370 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
371 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
372 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
373 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock
374 * @param Periphs This parameter can be a combination of the following values:
375 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
376 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
377 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
378 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
379 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
380 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
381 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
382 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
383 *
384 * (*) value not defined in all devices.
385 * @retval None
386 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)387 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
388 {
389 CLEAR_BIT(RCC->AHB1ENR, Periphs);
390 }
391
392 /**
393 * @brief Force AHB1 peripherals reset.
394 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
395 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
396 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
397 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
398 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
399 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n
400 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
401 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset
402 * @param Periphs This parameter can be a combination of the following values:
403 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
404 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
405 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
406 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
407 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
408 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
409 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
410 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
411 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
412 *
413 * (*) value not defined in all devices.
414 * @retval None
415 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)416 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
417 {
418 SET_BIT(RCC->AHB1RSTR, Periphs);
419 }
420
421 /**
422 * @brief Release AHB1 peripherals reset.
423 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
424 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
425 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
426 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
427 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
428 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
429 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
430 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset
431 * @param Periphs This parameter can be a combination of the following values:
432 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
433 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
434 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
435 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
436 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
437 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
438 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
439 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
440 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
441 *
442 * (*) value not defined in all devices.
443 * @retval None
444 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)445 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
446 {
447 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
448 }
449
450 /**
451 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
452 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
453 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
454 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
455 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
456 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
457 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
458 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
459 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
460 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep
461 * @param Periphs This parameter can be a combination of the following values:
462 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
463 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
464 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
465 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
466 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
467 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
468 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
469 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
470 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
471 *
472 * (*) value not defined in all devices.
473 * @retval None
474 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)475 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
476 {
477 __IO uint32_t tmpreg;
478 SET_BIT(RCC->AHB1SMENR, Periphs);
479 /* Delay after an RCC peripheral clock enabling */
480 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
481 (void)tmpreg;
482 }
483
484 /**
485 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
486 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
487 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
488 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
489 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
490 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
491 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
492 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
493 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
494 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep
495 * @param Periphs This parameter can be a combination of the following values:
496 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
497 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
498 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
499 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
500 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
501 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
502 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
503 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
504 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
505 *
506 * (*) value not defined in all devices.
507 * @retval None
508 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)509 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
510 {
511 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
512 }
513
514 /**
515 * @}
516 */
517
518 /** @defgroup BUS_LL_EF_AHB2 AHB2
519 * @{
520 */
521
522 /**
523 * @brief Enable AHB2 peripherals clock.
524 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
525 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
526 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
527 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
528 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
529 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
530 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
531 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
532 * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
533 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
534 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
535 * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
536 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
537 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
538 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
539 * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n
540 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock
541 * @param Periphs This parameter can be a combination of the following values:
542 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
543 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
544 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
545 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
546 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
547 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
548 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
549 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
550 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
551 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
552 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
553 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
554 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
555 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
556 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
557 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
558 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
559 *
560 * (*) value not defined in all devices.
561 * @retval None
562 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)563 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
564 {
565 __IO uint32_t tmpreg;
566 SET_BIT(RCC->AHB2ENR, Periphs);
567 /* Delay after an RCC peripheral clock enabling */
568 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
569 (void)tmpreg;
570 }
571
572 /**
573 * @brief Check if AHB2 peripheral clock is enabled or not
574 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
575 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
576 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
577 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
578 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
579 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
580 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
581 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
582 * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
583 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
584 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
585 * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
586 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
587 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
588 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
589 * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
590 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock
591 * @param Periphs This parameter can be a combination of the following values:
592 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
593 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
594 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
595 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
596 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
597 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
598 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
599 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
600 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
601 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
602 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
603 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
604 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
605 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
606 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
607 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
608 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
609 *
610 * (*) value not defined in all devices.
611 * @retval State of Periphs (1 or 0).
612 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)613 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
614 {
615 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
616 }
617
618 /**
619 * @brief Disable AHB2 peripherals clock.
620 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
621 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
622 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
623 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
624 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
625 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
626 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
627 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
628 * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
629 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
630 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
631 * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
632 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
633 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
634 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
635 * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n
636 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock
637 * @param Periphs This parameter can be a combination of the following values:
638 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
639 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
640 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
641 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
642 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
643 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
644 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
645 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
646 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
647 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
648 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
649 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
650 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
651 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
652 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
653 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
654 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
655 *
656 * (*) value not defined in all devices.
657 * @retval None
658 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)659 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
660 {
661 CLEAR_BIT(RCC->AHB2ENR, Periphs);
662 }
663
664 /**
665 * @brief Force AHB2 peripherals reset.
666 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
667 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
668 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
669 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
670 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
671 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
672 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
673 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
674 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n
675 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
676 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
677 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
678 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
679 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
680 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
681 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n
682 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset
683 * @param Periphs This parameter can be a combination of the following values:
684 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
685 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
686 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
687 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
688 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
689 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
690 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
691 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
692 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
693 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
694 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
695 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
696 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
697 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
698 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
699 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
700 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
701 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
702 *
703 * (*) value not defined in all devices.
704 * @retval None
705 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)706 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
707 {
708 SET_BIT(RCC->AHB2RSTR, Periphs);
709 }
710
711 /**
712 * @brief Release AHB2 peripherals reset.
713 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
714 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
715 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
716 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
717 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
718 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
719 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
720 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
721 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
722 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
723 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
724 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
725 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
726 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
727 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
728 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n
729 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset
730 * @param Periphs This parameter can be a combination of the following values:
731 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
732 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
733 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
734 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
735 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
736 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
737 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
738 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
739 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
740 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
741 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
742 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
743 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
744 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
745 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
746 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
747 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
748 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
749 *
750 * (*) value not defined in all devices.
751 * @retval None
752 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)753 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
754 {
755 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
756 }
757
758 /**
759 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
760 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
761 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
762 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
763 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
764 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
765 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
766 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
767 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
768 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
769 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
770 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
771 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
772 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
773 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
774 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
775 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
776 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
777 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
778 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep
779 * @param Periphs This parameter can be a combination of the following values:
780 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
781 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
782 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
783 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
784 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
785 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
786 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
787 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
788 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
789 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
790 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
791 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
792 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
793 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
794 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
795 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
796 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
797 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
798 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
799 *
800 * (*) value not defined in all devices.
801 * @retval None
802 */
LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)803 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
804 {
805 __IO uint32_t tmpreg;
806 SET_BIT(RCC->AHB2SMENR, Periphs);
807 /* Delay after an RCC peripheral clock enabling */
808 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
809 (void)tmpreg;
810 }
811
812 /**
813 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
814 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
815 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
816 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
817 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
818 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
819 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
820 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
821 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
822 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
823 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
824 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
825 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
826 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
827 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
828 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
829 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
830 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
831 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
832 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep
833 * @param Periphs This parameter can be a combination of the following values:
834 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
835 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
836 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
837 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
838 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
839 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
840 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
841 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
842 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
843 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
844 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
845 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
846 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
847 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
848 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
849 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
850 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
851 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
852 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
853 *
854 * (*) value not defined in all devices.
855 * @retval None
856 */
LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)857 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
858 {
859 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
860 }
861
862 /**
863 * @}
864 */
865
866 /** @defgroup BUS_LL_EF_AHB3 AHB3
867 * @{
868 */
869
870 /**
871 * @brief Enable AHB3 peripherals clock.
872 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
873 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n
874 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n
875 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock
876 * @param Periphs This parameter can be a combination of the following values:
877 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
878 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
879 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
880 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
881 *
882 * (*) value not defined in all devices.
883 * @retval None
884 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)885 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
886 {
887 __IO uint32_t tmpreg;
888 SET_BIT(RCC->AHB3ENR, Periphs);
889 /* Delay after an RCC peripheral clock enabling */
890 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
891 (void)tmpreg;
892 }
893
894 /**
895 * @brief Check if AHB3 peripheral clock is enabled or not
896 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
897 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n
898 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n
899 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock
900 * @param Periphs This parameter can be a combination of the following values:
901 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
902 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
903 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
904 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
905 *
906 * (*) value not defined in all devices.
907 * @retval State of Periphs (1 or 0).
908 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)909 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
910 {
911 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
912 }
913
914 /**
915 * @brief Disable AHB3 peripherals clock.
916 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
917 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n
918 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n
919 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock
920 * @param Periphs This parameter can be a combination of the following values:
921 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
922 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
923 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
924 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
925 *
926 * (*) value not defined in all devices.
927 * @retval None
928 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)929 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
930 {
931 CLEAR_BIT(RCC->AHB3ENR, Periphs);
932 }
933
934 /**
935 * @brief Force AHB3 peripherals reset.
936 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
937 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n
938 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n
939 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset
940 * @param Periphs This parameter can be a combination of the following values:
941 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
942 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
943 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
944 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
945 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
946 *
947 * (*) value not defined in all devices.
948 * @retval None
949 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)950 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
951 {
952 SET_BIT(RCC->AHB3RSTR, Periphs);
953 }
954
955 /**
956 * @brief Release AHB3 peripherals reset.
957 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
958 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
959 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n
960 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset
961 * @param Periphs This parameter can be a combination of the following values:
962 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
963 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
964 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
965 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
966 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
967 *
968 * (*) value not defined in all devices.
969 * @retval None
970 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)971 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
972 {
973 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
974 }
975
976 /**
977 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
978 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
979 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n
980 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
981 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep
982 * @param Periphs This parameter can be a combination of the following values:
983 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
984 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
985 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
986 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
987 *
988 * (*) value not defined in all devices.
989 * @retval None
990 */
LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)991 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
992 {
993 __IO uint32_t tmpreg;
994 SET_BIT(RCC->AHB3SMENR, Periphs);
995 /* Delay after an RCC peripheral clock enabling */
996 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
997 (void)tmpreg;
998 }
999
1000 /**
1001 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
1002 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1003 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1004 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1005 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1006 * @param Periphs This parameter can be a combination of the following values:
1007 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1008 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1009 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
1010 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
1011 *
1012 * (*) value not defined in all devices.
1013 * @retval None
1014 */
LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)1015 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
1016 {
1017 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
1018 }
1019
1020 /**
1021 * @}
1022 */
1023
1024 /** @defgroup BUS_LL_EF_APB1 APB1
1025 * @{
1026 */
1027
1028 /**
1029 * @brief Enable APB1 peripherals clock.
1030 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
1031 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
1032 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
1033 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
1034 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
1035 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
1036 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
1037 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
1038 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
1039 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
1040 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
1041 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
1042 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
1043 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
1044 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
1045 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
1046 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
1047 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
1048 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
1049 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
1050 * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n
1051 * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n
1052 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
1053 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
1054 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
1055 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
1056 * @param Periphs This parameter can be a combination of the following values:
1057 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1058 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1059 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1060 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1061 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1062 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1063 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1064 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1065 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1066 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1067 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1068 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1069 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1070 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1071 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1072 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1073 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1074 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1075 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1076 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1077 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1078 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1079 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1080 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1081 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1082 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1083 *
1084 * (*) value not defined in all devices.
1085 * @retval None
1086 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1087 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1088 {
1089 __IO uint32_t tmpreg;
1090 SET_BIT(RCC->APB1ENR1, Periphs);
1091 /* Delay after an RCC peripheral clock enabling */
1092 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
1093 (void)tmpreg;
1094 }
1095
1096 /**
1097 * @brief Enable APB1 peripherals clock.
1098 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
1099 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
1100 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
1101 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
1102 * @param Periphs This parameter can be a combination of the following values:
1103 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1104 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1105 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1106 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1107 *
1108 * (*) value not defined in all devices.
1109 * @retval None
1110 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)1111 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
1112 {
1113 __IO uint32_t tmpreg;
1114 SET_BIT(RCC->APB1ENR2, Periphs);
1115 /* Delay after an RCC peripheral clock enabling */
1116 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
1117 (void)tmpreg;
1118 }
1119
1120 /**
1121 * @brief Check if APB1 peripheral clock is enabled or not
1122 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1123 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1124 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1125 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1126 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1127 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1128 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
1129 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
1130 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1131 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1132 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1133 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
1134 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
1135 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
1136 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
1137 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1138 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1139 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1140 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
1141 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1142 * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n
1143 * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1144 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
1145 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
1146 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
1147 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
1148 * @param Periphs This parameter can be a combination of the following values:
1149 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1150 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1151 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1155 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1156 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1157 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1158 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1159 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1160 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1161 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1162 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1163 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1164 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1165 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1166 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1167 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1168 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1169 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1170 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1171 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1172 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1173 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1174 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1175 *
1176 * (*) value not defined in all devices.
1177 * @retval State of Periphs (1 or 0).
1178 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1179 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1180 {
1181 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
1182 }
1183
1184 /**
1185 * @brief Check if APB1 peripheral clock is enabled or not
1186 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
1187 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
1188 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
1189 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
1190 * @param Periphs This parameter can be a combination of the following values:
1191 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1192 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1193 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1194 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1195 *
1196 * (*) value not defined in all devices.
1197 * @retval State of Periphs (1 or 0).
1198 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1199 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1200 {
1201 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1202 }
1203
1204 /**
1205 * @brief Disable APB1 peripherals clock.
1206 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1207 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1208 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
1209 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
1210 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
1211 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
1212 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
1213 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
1214 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
1215 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1216 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
1217 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1218 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
1219 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
1220 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
1221 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1222 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1223 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1224 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
1225 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
1226 * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n
1227 * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n
1228 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
1229 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
1230 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
1231 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
1232 * @param Periphs This parameter can be a combination of the following values:
1233 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1234 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1235 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1236 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1237 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1238 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1239 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1240 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1241 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1242 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1243 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1244 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1245 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1246 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1247 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1248 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1249 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1250 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1251 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1252 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1253 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1254 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1255 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1256 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1257 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1258 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1259 *
1260 * (*) value not defined in all devices.
1261 * @retval None
1262 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1263 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1264 {
1265 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1266 }
1267
1268 /**
1269 * @brief Disable APB1 peripherals clock.
1270 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
1271 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
1272 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
1273 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
1274 * @param Periphs This parameter can be a combination of the following values:
1275 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1276 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1277 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1278 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1279 *
1280 * (*) value not defined in all devices.
1281 * @retval None
1282 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1283 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1284 {
1285 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1286 }
1287
1288 /**
1289 * @brief Force APB1 peripherals reset.
1290 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1291 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1292 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
1293 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
1294 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
1295 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
1296 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
1297 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1298 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
1299 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1300 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
1301 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
1302 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
1303 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1304 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
1305 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1306 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
1307 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
1308 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n
1309 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n
1310 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
1311 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
1312 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
1313 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1314 * @param Periphs This parameter can be a combination of the following values:
1315 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1316 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1317 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1318 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1319 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1320 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1321 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1322 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1323 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1324 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1325 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1326 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1327 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1328 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1329 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1330 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1331 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1332 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1333 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1334 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1335 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1336 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1337 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1338 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1339 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1340 *
1341 * (*) value not defined in all devices.
1342 * @retval None
1343 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1344 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1345 {
1346 SET_BIT(RCC->APB1RSTR1, Periphs);
1347 }
1348
1349 /**
1350 * @brief Force APB1 peripherals reset.
1351 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1352 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
1353 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
1354 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
1355 * @param Periphs This parameter can be a combination of the following values:
1356 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1357 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1358 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1359 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1360 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1361 *
1362 * (*) value not defined in all devices.
1363 * @retval None
1364 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1365 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1366 {
1367 SET_BIT(RCC->APB1RSTR2, Periphs);
1368 }
1369
1370 /**
1371 * @brief Release APB1 peripherals reset.
1372 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1373 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1374 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
1375 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
1376 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
1377 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
1378 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
1379 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1380 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
1381 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1382 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
1383 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
1384 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
1385 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1386 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
1387 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1388 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
1389 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
1390 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n
1391 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n
1392 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
1393 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
1394 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
1395 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1396 * @param Periphs This parameter can be a combination of the following values:
1397 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1398 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1399 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1402 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1403 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1404 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1405 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1406 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1407 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1408 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1409 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1410 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1411 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1412 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1413 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1414 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1415 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1416 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1417 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1418 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1419 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1420 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1421 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1422 *
1423 * (*) value not defined in all devices.
1424 * @retval None
1425 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1426 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1427 {
1428 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1429 }
1430
1431 /**
1432 * @brief Release APB1 peripherals reset.
1433 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1434 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
1435 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
1436 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
1437 * @param Periphs This parameter can be a combination of the following values:
1438 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1439 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1440 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1441 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1442 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1443 *
1444 * (*) value not defined in all devices.
1445 * @retval None
1446 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1447 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1448 {
1449 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1450 }
1451
1452 /**
1453 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1454 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1455 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1456 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1457 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1458 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1459 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1460 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1461 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1462 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1463 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1464 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1465 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1466 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1467 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1468 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1469 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1470 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1471 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1472 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1473 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1474 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1475 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1476 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1477 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1478 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1479 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
1480 * @param Periphs This parameter can be a combination of the following values:
1481 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1482 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1483 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1484 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1485 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1486 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1487 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1488 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1489 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1490 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1491 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1492 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1493 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1494 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1495 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1496 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1497 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1498 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1499 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1500 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1501 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1502 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1503 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1504 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1505 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1506 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1507 *
1508 * (*) value not defined in all devices.
1509 * @retval None
1510 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)1511 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
1512 {
1513 __IO uint32_t tmpreg;
1514 SET_BIT(RCC->APB1SMENR1, Periphs);
1515 /* Delay after an RCC peripheral clock enabling */
1516 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1517 (void)tmpreg;
1518 }
1519
1520 /**
1521 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1522 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1523 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1524 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1525 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
1526 * @param Periphs This parameter can be a combination of the following values:
1527 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1528 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1529 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1530 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1531 *
1532 * (*) value not defined in all devices.
1533 * @retval None
1534 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)1535 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1536 {
1537 __IO uint32_t tmpreg;
1538 SET_BIT(RCC->APB1SMENR2, Periphs);
1539 /* Delay after an RCC peripheral clock enabling */
1540 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1541 (void)tmpreg;
1542 }
1543
1544 /**
1545 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1546 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1547 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1548 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1549 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1550 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1551 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1552 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1553 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1554 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1555 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1556 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1557 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1558 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1559 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1560 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1561 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1562 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1563 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1564 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1565 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1566 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1567 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1568 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1569 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1570 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1571 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
1572 * @param Periphs This parameter can be a combination of the following values:
1573 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1574 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1579 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1580 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1581 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1582 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1583 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1584 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1585 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1586 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1587 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1588 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1589 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1590 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1591 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1592 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1593 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1594 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1595 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1596 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1597 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1598 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1599 *
1600 * (*) value not defined in all devices.
1601 * @retval None
1602 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)1603 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
1604 {
1605 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1606 }
1607
1608 /**
1609 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1610 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1611 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1612 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1613 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
1614 * @param Periphs This parameter can be a combination of the following values:
1615 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1616 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1617 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1618 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1619 *
1620 * (*) value not defined in all devices.
1621 * @retval None
1622 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)1623 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1624 {
1625 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1626 }
1627
1628 /**
1629 * @}
1630 */
1631
1632 /** @defgroup BUS_LL_EF_APB2 APB2
1633 * @{
1634 */
1635
1636 /**
1637 * @brief Enable APB2 peripherals clock.
1638 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1639 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
1640 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
1641 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1642 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1643 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1644 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1645 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
1646 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1647 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1648 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1649 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1650 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1651 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1652 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock
1653 * @param Periphs This parameter can be a combination of the following values:
1654 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1655 * @arg @ref LL_APB2_GRP1_PERIPH_FW
1656 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1657 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1658 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1659 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1660 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1661 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1662 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1663 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1664 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1665 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1666 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1667 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1668 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1669 *
1670 * (*) value not defined in all devices.
1671 * @retval None
1672 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1673 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1674 {
1675 __IO uint32_t tmpreg;
1676 SET_BIT(RCC->APB2ENR, Periphs);
1677 /* Delay after an RCC peripheral clock enabling */
1678 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1679 (void)tmpreg;
1680 }
1681
1682 /**
1683 * @brief Check if APB2 peripheral clock is enabled or not
1684 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1685 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
1686 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
1687 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1688 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1689 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1690 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1691 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
1692 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1693 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1694 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1695 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1696 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1697 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1698 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock
1699 * @param Periphs This parameter can be a combination of the following values:
1700 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1701 * @arg @ref LL_APB2_GRP1_PERIPH_FW
1702 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1703 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1704 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1705 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1706 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1707 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1708 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1709 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1710 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1711 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1712 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1713 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1714 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1715 *
1716 * (*) value not defined in all devices.
1717 * @retval State of Periphs (1 or 0).
1718 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1719 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1720 {
1721 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1722 }
1723
1724 /**
1725 * @brief Disable APB2 peripherals clock.
1726 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1727 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
1728 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1729 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1730 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1731 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1732 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
1733 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1734 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1735 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1736 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1737 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1738 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1739 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock
1740 * @param Periphs This parameter can be a combination of the following values:
1741 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1742 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1744 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1745 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1746 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1747 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1748 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1749 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1750 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1751 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1752 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1753 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1754 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1755 *
1756 * (*) value not defined in all devices.
1757 * @retval None
1758 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1759 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1760 {
1761 CLEAR_BIT(RCC->APB2ENR, Periphs);
1762 }
1763
1764 /**
1765 * @brief Force APB2 peripherals reset.
1766 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1767 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
1768 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1769 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1770 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1771 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1772 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
1773 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1774 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1775 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1776 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1777 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1778 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1779 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset
1780 * @param Periphs This parameter can be a combination of the following values:
1781 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1782 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1783 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1784 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1785 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1786 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1787 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1788 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1789 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1790 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1791 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1792 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1793 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1794 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1795 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1796 *
1797 * (*) value not defined in all devices.
1798 * @retval None
1799 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1800 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1801 {
1802 SET_BIT(RCC->APB2RSTR, Periphs);
1803 }
1804
1805 /**
1806 * @brief Release APB2 peripherals reset.
1807 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1808 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
1809 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1810 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1811 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1812 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1813 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
1814 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1815 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1816 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1817 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1818 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1819 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1820 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset
1821 * @param Periphs This parameter can be a combination of the following values:
1822 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1823 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1824 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1825 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1826 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1827 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1828 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1829 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1830 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1831 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1832 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1833 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1834 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1835 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1836 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1837 *
1838 * (*) value not defined in all devices.
1839 * @retval None
1840 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1841 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1842 {
1843 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1844 }
1845
1846 /**
1847 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1848 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1849 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1850 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1851 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1852 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1853 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1854 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1855 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1856 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1857 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1858 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1859 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1860 * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1861 * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep
1862 * @param Periphs This parameter can be a combination of the following values:
1863 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1864 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1865 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1866 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1867 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1868 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1869 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1870 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1871 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1872 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1873 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1874 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1875 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1876 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1877 *
1878 * (*) value not defined in all devices.
1879 * @retval None
1880 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1881 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1882 {
1883 __IO uint32_t tmpreg;
1884 SET_BIT(RCC->APB2SMENR, Periphs);
1885 /* Delay after an RCC peripheral clock enabling */
1886 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1887 (void)tmpreg;
1888 }
1889
1890 /**
1891 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1892 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1893 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1894 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1895 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1896 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1897 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1898 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1899 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1900 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1901 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1902 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1903 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1904 * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1905 * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep
1906 * @param Periphs This parameter can be a combination of the following values:
1907 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1908 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1909 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1910 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1911 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1912 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1913 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1914 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1915 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1916 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1917 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1918 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1919 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1920 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1921 *
1922 * (*) value not defined in all devices.
1923 * @retval None
1924 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1925 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1926 {
1927 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1928 }
1929
1930 /**
1931 * @}
1932 */
1933
1934
1935 /**
1936 * @}
1937 */
1938
1939 /**
1940 * @}
1941 */
1942
1943 #endif /* defined(RCC) */
1944
1945 /**
1946 * @}
1947 */
1948
1949 #ifdef __cplusplus
1950 }
1951 #endif
1952
1953 #endif /* STM32L4xx_LL_BUS_H */
1954
1955
