1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_bus.h
4 * @author MCD Application Team
5 * @version $VERSION$
6 * @date $DATE$
7 * @brief Header file of BUS LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * Copyright (c) 2019 STMicroelectronics.
12 * All rights reserved.
13 *
14 * This software is licensed under terms that can be found in the LICENSE file
15 * in the root directory of this software component.
16 * If no LICENSE file comes with this software, it is provided AS-IS.
17 *
18 ******************************************************************************
19 @verbatim
20 ##### RCC Limitations #####
21 ==============================================================================
22 [..]
23 A delay between an RCC peripheral clock enable and the effective peripheral
24 enabling should be taken into account in order to manage the peripheral read/write
25 from/to registers.
26 (+) This delay depends on the peripheral mapping.
27 (++) AHB & APB peripherals, 1 dummy read is necessary
28
29 [..]
30 Workarounds:
31 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
32 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
33
34 @endverbatim
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef STM32MP1xx_LL_BUS_H
40 #define STM32MP1xx_LL_BUS_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32mp1xx.h"
48
49 /** @addtogroup STM32MP1xx_LL_Driver
50 * @{
51 */
52
53 #if defined(RCC)
54
55 /** @defgroup BUS_LL BUS
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63
64 /* Private macros ------------------------------------------------------------*/
65
66 /* Exported types ------------------------------------------------------------*/
67
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
70 * @{
71 */
72
73 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
74 * @{
75 */
76 #define LL_AHB2_GRP1_PERIPH_ALL 0x00010127U
77 #define LL_AHB2_GRP1_PERIPH_DMA1 RCC_MC_AHB2ENSETR_DMA1EN
78 #define LL_AHB2_GRP1_PERIPH_DMA2 RCC_MC_AHB2ENSETR_DMA2EN
79 #define LL_AHB2_GRP1_PERIPH_DMAMUX RCC_MC_AHB2ENSETR_DMAMUXEN
80 #define LL_AHB2_GRP1_PERIPH_ADC12 RCC_MC_AHB2ENSETR_ADC12EN
81 #define LL_AHB2_GRP1_PERIPH_USBO RCC_MC_AHB2ENSETR_USBOEN
82 #define LL_AHB2_GRP1_PERIPH_SDMMC3 RCC_MC_AHB2ENSETR_SDMMC3EN
83 /**
84 * @}
85 */
86
87 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
88 * @{
89 */
90 #define LL_AHB3_GRP1_PERIPH_DCMI RCC_MC_AHB3ENSETR_DCMIEN
91 #if defined(CRYP2)
92 #define LL_AHB3_GRP1_PERIPH_CRYP2 RCC_MC_AHB3ENSETR_CRYP2EN
93 #define LL_AHB3_GRP1_PERIPH_ALL 0x000018F1U
94 #else /*!CRYP2*/
95 #define LL_AHB3_GRP1_PERIPH_ALL 0x000018E1U
96 #endif /* CRYP2 */
97 #define LL_AHB3_GRP1_PERIPH_HASH2 RCC_MC_AHB3ENSETR_HASH2EN
98 #define LL_AHB3_GRP1_PERIPH_RNG2 RCC_MC_AHB3ENSETR_RNG2EN
99 #define LL_AHB3_GRP1_PERIPH_CRC2 RCC_MC_AHB3ENSETR_CRC2EN
100 #define LL_AHB3_GRP1_PERIPH_HSEM RCC_MC_AHB3ENSETR_HSEMEN
101 #define LL_AHB3_GRP1_PERIPH_IPCC RCC_MC_AHB3ENSETR_IPCCEN
102 /**
103 * @}
104 */
105
106 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
107 * @{
108 */
109 #define LL_AHB4_GRP1_PERIPH_ALL 0x000007FFU
110 #define LL_AHB4_GRP1_PERIPH_GPIOA RCC_MC_AHB4ENSETR_GPIOAEN
111 #define LL_AHB4_GRP1_PERIPH_GPIOB RCC_MC_AHB4ENSETR_GPIOBEN
112 #define LL_AHB4_GRP1_PERIPH_GPIOC RCC_MC_AHB4ENSETR_GPIOCEN
113 #define LL_AHB4_GRP1_PERIPH_GPIOD RCC_MC_AHB4ENSETR_GPIODEN
114 #define LL_AHB4_GRP1_PERIPH_GPIOE RCC_MC_AHB4ENSETR_GPIOEEN
115 #define LL_AHB4_GRP1_PERIPH_GPIOF RCC_MC_AHB4ENSETR_GPIOFEN
116 #define LL_AHB4_GRP1_PERIPH_GPIOG RCC_MC_AHB4ENSETR_GPIOGEN
117 #define LL_AHB4_GRP1_PERIPH_GPIOH RCC_MC_AHB4ENSETR_GPIOHEN
118 #define LL_AHB4_GRP1_PERIPH_GPIOI RCC_MC_AHB4ENSETR_GPIOIEN
119 #define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_MC_AHB4ENSETR_GPIOJEN
120 #define LL_AHB4_GRP1_PERIPH_GPIOK RCC_MC_AHB4ENSETR_GPIOKEN
121 /**
122 * @}
123 */
124
125 /** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH AHB5 GRP1 PERIPH
126 * @{
127 */
128 /**
129 * @note LL_AHB5_GRP1_PERIPH_ALL only contains reset values (not enable)
130 */
131 #define LL_AHB5_GRP1_PERIPH_GPIOZ RCC_MC_AHB5ENSETR_GPIOZEN
132 #if defined(CRYP1)
133 #define LL_AHB5_GRP1_PERIPH_ALL 0x00010071U
134 #define LL_AHB5_GRP1_PERIPH_CRYP1 RCC_MC_AHB5ENSETR_CRYP1EN
135 #else /* !CRYP1 */
136 #define LL_AHB5_GRP1_PERIPH_ALL 0x00010061U
137 #endif /* CRYP1 */
138 #define LL_AHB5_GRP1_PERIPH_HASH1 RCC_MC_AHB5ENSETR_HASH1EN
139 #define LL_AHB5_GRP1_PERIPH_RNG1 RCC_MC_AHB5ENSETR_RNG1EN
140 #define LL_AHB5_GRP1_PERIPH_BKPSRAM RCC_MC_AHB5ENSETR_BKPSRAMEN
141 /**
142 * @}
143 */
144
145 /** @defgroup BUS_LL_EC_AHB6_GRP1_PERIPH AHB6 GRP1 PERIPH
146 * @{
147 */
148 #define LL_AHB6_GRP1_PERIPH_MDMA RCC_MC_AHB6ENSETR_MDMAEN
149 #define LL_AHB6_GRP1_PERIPH_GPU RCC_MC_AHB6ENSETR_GPUEN
150 #define LL_AHB6_GRP1_PERIPH_ETH1CK RCC_MC_AHB6ENSETR_ETHCKEN
151 #define LL_AHB6_GRP1_PERIPH_ETH1TX RCC_MC_AHB6ENSETR_ETHTXEN
152 #define LL_AHB6_GRP1_PERIPH_ETH1RX RCC_MC_AHB6ENSETR_ETHRXEN
153 #define LL_AHB6_GRP1_PERIPH_ETH1MAC RCC_MC_AHB6ENSETR_ETHMACEN
154 #define LL_AHB6_GRP1_PERIPH_ETH1STP RCC_MC_AHB6LPENSETR_ETHSTPEN
155 #define LL_AHB6_GRP1_PERIPH_FMC RCC_MC_AHB6ENSETR_FMCEN
156 #define LL_AHB6_GRP1_PERIPH_QSPI RCC_MC_AHB6ENSETR_QSPIEN
157 #define LL_AHB6_GRP1_PERIPH_SDMMC1 RCC_MC_AHB6ENSETR_SDMMC1EN
158 #define LL_AHB6_GRP1_PERIPH_SDMMC2 RCC_MC_AHB6ENSETR_SDMMC2EN
159 #define LL_AHB6_GRP1_PERIPH_CRC1 RCC_MC_AHB6ENSETR_CRC1EN
160 #define LL_AHB6_GRP1_PERIPH_USBH RCC_MC_AHB6ENSETR_USBHEN
161 /**
162 * @}
163 */
164
165 /** @defgroup BUS_LL_EC_AXI_GRP1_PERIPH AXI GRP1 PERIPH
166 * @{
167 */
168 #define LL_AXI_GRP1_PERIPH_ALL 0x00000001U
169 #define LL_AXI_GRP1_PERIPH_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN
170 /**
171 * @}
172 */
173
174 /** @defgroup BUS_LL_EC_MLAHB_GRP1_PERIPH MLAHB GRP1 PERIPH
175 * @{
176 */
177 #define LL_MLAHB_GRP1_PERIPH_ALL 0x00000010U
178 #define LL_MLAHB_GRP1_PERIPH_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN
179 /**
180 * @}
181 */
182
183 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
184 * @{
185 */
186 #define LL_APB1_GRP1_PERIPH_ALL 0xADEFDBFFU
187 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_MC_APB1ENSETR_TIM2EN
188 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_MC_APB1ENSETR_TIM3EN
189 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_MC_APB1ENSETR_TIM4EN
190 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_MC_APB1ENSETR_TIM5EN
191 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_MC_APB1ENSETR_TIM6EN
192 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_MC_APB1ENSETR_TIM7EN
193 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_MC_APB1ENSETR_TIM12EN
194 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_MC_APB1ENSETR_TIM13EN
195 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_MC_APB1ENSETR_TIM14EN
196 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_MC_APB1ENSETR_LPTIM1EN
197 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_MC_APB1ENSETR_SPI2EN
198 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_MC_APB1ENSETR_SPI3EN
199 #define LL_APB1_GRP1_PERIPH_USART2 RCC_MC_APB1ENSETR_USART2EN
200 #define LL_APB1_GRP1_PERIPH_USART3 RCC_MC_APB1ENSETR_USART3EN
201 #define LL_APB1_GRP1_PERIPH_UART4 RCC_MC_APB1ENSETR_UART4EN
202 #define LL_APB1_GRP1_PERIPH_UART5 RCC_MC_APB1ENSETR_UART5EN
203 #define LL_APB1_GRP1_PERIPH_UART7 RCC_MC_APB1ENSETR_UART7EN
204 #define LL_APB1_GRP1_PERIPH_UART8 RCC_MC_APB1ENSETR_UART8EN
205 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_MC_APB1ENSETR_I2C1EN
206 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_MC_APB1ENSETR_I2C2EN
207 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_MC_APB1ENSETR_I2C3EN
208 #define LL_APB1_GRP1_PERIPH_I2C5 RCC_MC_APB1ENSETR_I2C5EN
209 #define LL_APB1_GRP1_PERIPH_SPDIF RCC_MC_APB1ENSETR_SPDIFEN
210 #define LL_APB1_GRP1_PERIPH_CEC RCC_MC_APB1ENSETR_CECEN
211 #define LL_APB1_GRP1_PERIPH_WWDG1 RCC_MC_APB1ENSETR_WWDG1EN
212 #define LL_APB1_GRP1_PERIPH_DAC12 RCC_MC_APB1ENSETR_DAC12EN
213 #define LL_APB1_GRP1_PERIPH_MDIOS RCC_MC_APB1ENSETR_MDIOSEN
214 /**
215 * @}
216 */
217
218 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
219 * @{
220 */
221 /**
222 * @note LL_APB2_GRP1_PERIPH_ALL only contains reset values (not enable)
223 */
224 #define LL_APB2_GRP1_PERIPH_ALL 0x117271FU
225 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_MC_APB2ENSETR_TIM1EN
226 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_MC_APB2ENSETR_TIM8EN
227 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_MC_APB2ENSETR_TIM15EN
228 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_MC_APB2ENSETR_TIM16EN
229 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_MC_APB2ENSETR_TIM17EN
230 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_MC_APB2ENSETR_SPI1EN
231 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_MC_APB2ENSETR_SPI4EN
232 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_MC_APB2ENSETR_SPI5EN
233 #define LL_APB2_GRP1_PERIPH_USART6 RCC_MC_APB2ENSETR_USART6EN
234 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_MC_APB2ENSETR_SAI1EN
235 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_MC_APB2ENSETR_SAI2EN
236 #define LL_APB2_GRP1_PERIPH_SAI3 RCC_MC_APB2ENSETR_SAI3EN
237 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_MC_APB2ENSETR_DFSDMEN
238 #define LL_APB2_GRP1_PERIPH_ADFSDM1 RCC_MC_APB2ENSETR_ADFSDMEN
239 #define LL_APB2_GRP1_PERIPH_FDCAN RCC_MC_APB2ENSETR_FDCANEN
240 /**
241 * @}
242 */
243
244 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
245 * @{
246 */
247 /**
248 * @note LL_APB3_GRP1_PERIPH_ALL only contains reset values (not enable)
249 */
250 #define LL_APB3_GRP1_PERIPH_ALL 0x0003290FU
251 #define LL_APB3_GRP1_PERIPH_LPTIM2 RCC_MC_APB3ENSETR_LPTIM2EN
252 #define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_MC_APB3ENSETR_LPTIM3EN
253 #define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_MC_APB3ENSETR_LPTIM4EN
254 #define LL_APB3_GRP1_PERIPH_LPTIM5 RCC_MC_APB3ENSETR_LPTIM5EN
255 #define LL_APB3_GRP1_PERIPH_SAI4 RCC_MC_APB3ENSETR_SAI4EN
256 #define LL_APB3_GRP1_PERIPH_SYSCFG RCC_MC_APB3ENSETR_SYSCFGEN
257 #define LL_APB3_GRP1_PERIPH_VREF RCC_MC_APB3ENSETR_VREFEN
258 #define LL_APB3_GRP1_PERIPH_TMPSENS RCC_MC_APB3ENSETR_DTSEN
259 #define LL_APB3_GRP1_PERIPH_HDP RCC_MC_APB3ENSETR_HDPEN
260 /**
261 * @}
262 */
263
264 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH
265 * @{
266 */
267 /**
268 * @note LL_APB4_GRP1_PERIPH_ALL only contains reset values (not enable)
269 */
270 #define LL_APB4_GRP1_PERIPH_ALL 0x00010111U
271 #define LL_APB4_GRP1_PERIPH_LTDC RCC_MC_APB4ENSETR_LTDCEN
272 #define LL_APB4_GRP1_PERIPH_DSI RCC_MC_APB4ENSETR_DSIEN
273 #define LL_APB4_GRP1_PERIPH_DDRPERFM RCC_MC_APB4ENSETR_DDRPERFMEN
274 #define LL_APB4_GRP1_PERIPH_USBPHY RCC_MC_APB4ENSETR_USBPHYEN
275 #define LL_APB4_GRP1_PERIPH_STGENRO RCC_MC_APB4ENSETR_STGENROEN
276 #define LL_APB4_GRP1_PERIPH_STGENROSTP RCC_MC_APB4LPENSETR_STGENROSTPEN
277 /**
278 * @}
279 */
280
281 /** @defgroup BUS_LL_EC_APB5_GRP1_PERIPH APB5 GRP1 PERIPH
282 * @{
283 */
284 /**
285 * @note LL_APB5_GRP1_PERIPH_ALL only contains reset values (not enable)
286 */
287 #define LL_APB5_GRP1_PERIPH_ALL 0x0010001DU
288 #define LL_APB5_GRP1_PERIPH_SPI6 RCC_MC_APB5ENSETR_SPI6EN
289 #define LL_APB5_GRP1_PERIPH_I2C4 RCC_MC_APB5ENSETR_I2C4EN
290 #define LL_APB5_GRP1_PERIPH_I2C6 RCC_MC_APB5ENSETR_I2C6EN
291 #define LL_APB5_GRP1_PERIPH_USART1 RCC_MC_APB5ENSETR_USART1EN
292 #define LL_APB5_GRP1_PERIPH_RTCAPB RCC_MC_APB5ENSETR_RTCAPBEN
293 #define LL_APB5_GRP1_PERIPH_TZC1 RCC_MC_APB5ENSETR_TZC1EN
294 #define LL_APB5_GRP1_PERIPH_TZC2 RCC_MC_APB5ENSETR_TZC2EN
295 #define LL_APB5_GRP1_PERIPH_TZPC RCC_MC_APB5ENSETR_TZPCEN
296 #define LL_APB5_GRP1_PERIPH_BSEC RCC_MC_APB5ENSETR_BSECEN
297 #define LL_APB5_GRP1_PERIPH_STGEN RCC_MC_APB5ENSETR_STGENEN
298 #define LL_APB5_GRP1_PERIPH_STGENSTP RCC_MC_APB5LPENSETR_STGENSTPEN
299 /**
300 * @}
301 */
302
303 /**
304 * @}
305 */
306
307 /* Exported macro ------------------------------------------------------------*/
308 /* Exported functions --------------------------------------------------------*/
309 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
310 * @{
311 */
312
313 /** @defgroup BUS_LL_EF_AHB2 AHB2
314 * @{
315 */
316
317 /**
318 * @brief Enable AHB2 peripherals clock.
319 * @rmtoll MC_AHB2ENSETR DMA1 LL_AHB2_GRP1_EnableClock\n
320 * MC_AHB2ENSETR DMA2 LL_AHB2_GRP1_EnableClock\n
321 * MC_AHB2ENSETR DMAMUX LL_AHB2_GRP1_EnableClock\n
322 * MC_AHB2ENSETR ADC12 LL_AHB2_GRP1_EnableClock\n
323 * MC_AHB2ENSETR USBO LL_AHB2_GRP1_EnableClock\n
324 * MC_AHB2ENSETR SDMMC3 LL_AHB2_GRP1_EnableClock
325 * @param Periphs This parameter can be a combination of the following values:
326 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA1
327 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA2
328 * @arg @ref LL_AHB2_GRP1_PERIPH_DMAMUX
329 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
330 * @arg @ref LL_AHB2_GRP1_PERIPH_USBO
331 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC3
332 * @retval None
333 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)334 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
335 {
336 __IO uint32_t tmpreg;
337 WRITE_REG(RCC->MC_AHB2ENSETR, Periphs);
338 /* Delay after an RCC peripheral clock enabling */
339 tmpreg = READ_BIT(RCC->MC_AHB2ENSETR, Periphs);
340 (void)tmpreg;
341 }
342
343 /**
344 * @brief Check if AHB2 peripheral clock is enabled or not
345 * @rmtoll MC_AHB2ENSETR DMA1 LL_AHB2_GRP1_IsEnabledClock\n
346 * MC_AHB2ENSETR DMA2 LL_AHB2_GRP1_IsEnabledClock\n
347 * MC_AHB2ENSETR DMAMUX LL_AHB2_GRP1_IsEnabledClock\n
348 * MC_AHB2ENSETR ADC12 LL_AHB2_GRP1_IsEnabledClock\n
349 * MC_AHB2ENSETR USBO LL_AHB2_GRP1_IsEnabledClock\n
350 * MC_AHB2ENSETR SDMMC3 LL_AHB2_GRP1_IsEnabledClock
351 * @param Periphs This parameter can be a combination of the following values:
352 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA1
353 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA2
354 * @arg @ref LL_AHB2_GRP1_PERIPH_DMAMUX
355 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
356 * @arg @ref LL_AHB2_GRP1_PERIPH_USBO
357 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC3
358 * @retval State of Periphs (1 or 0).
359 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)360 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
361 {
362 return (READ_BIT(RCC->MC_AHB2ENSETR, Periphs) == Periphs);
363 }
364
365 /**
366 * @brief Disable AHB2 peripherals clock.
367 * @rmtoll MC_AHB2ENCLRR DMA1 LL_AHB2_GRP1_DisableClock\n
368 * MC_AHB2ENCLRR DMA2 LL_AHB2_GRP1_DisableClock\n
369 * MC_AHB2ENCLRR DMAMUX LL_AHB2_GRP1_DisableClock\n
370 * MC_AHB2ENCLRR ADC12 LL_AHB2_GRP1_DisableClock\n
371 * MC_AHB2ENCLRR USBO LL_AHB2_GRP1_DisableClock\n
372 * MC_AHB2ENCLRR SDMMC3 LL_AHB2_GRP1_DisableClock
373 * @param Periphs This parameter can be a combination of the following values:
374 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA1
375 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA2
376 * @arg @ref LL_AHB2_GRP1_PERIPH_DMAMUX
377 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
378 * @arg @ref LL_AHB2_GRP1_PERIPH_USBO
379 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC3
380 * @retval None
381 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)382 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
383 {
384 WRITE_REG(RCC->MC_AHB2ENCLRR, Periphs);
385 }
386
387 /**
388 * @brief Force AHB2 peripherals reset.
389 * @rmtoll AHB2RSTSETR DMA1 LL_AHB2_GRP1_ForceReset\n
390 * AHB2RSTSETR DMA2 LL_AHB2_GRP1_ForceReset\n
391 * AHB2RSTSETR DMAMUX LL_AHB2_GRP1_ForceReset\n
392 * AHB2RSTSETR ADC12 LL_AHB2_GRP1_ForceReset\n
393 * AHB2RSTSETR USBO LL_AHB2_GRP1_ForceReset\n
394 * AHB2RSTSETR SDMMC3 LL_AHB2_GRP1_ForceReset
395 * @param Periphs This parameter can be a combination of the following values:
396 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
397 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA1
398 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA2
399 * @arg @ref LL_AHB2_GRP1_PERIPH_DMAMUX
400 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
401 * @arg @ref LL_AHB2_GRP1_PERIPH_USBO
402 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC3
403 * @retval None
404 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)405 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
406 {
407 WRITE_REG(RCC->AHB2RSTSETR, Periphs);
408 }
409
410 /**
411 * @brief Release AHB2 peripherals reset.
412 * @rmtoll AHB2RSTCLRR DMA1 LL_AHB2_GRP1_ReleaseReset\n
413 * AHB2RSTCLRR DMA2 LL_AHB2_GRP1_ReleaseReset\n
414 * AHB2RSTCLRR DMAMUX LL_AHB2_GRP1_ReleaseReset\n
415 * AHB2RSTCLRR ADC12 LL_AHB2_GRP1_ReleaseReset\n
416 * AHB2RSTCLRR USBO LL_AHB2_GRP1_ReleaseReset\n
417 * AHB2RSTCLRR SDMMC3 LL_AHB2_GRP1_ReleaseReset
418 * @param Periphs This parameter can be a combination of the following values:
419 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
420 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA1
421 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA2
422 * @arg @ref LL_AHB2_GRP1_PERIPH_DMAMUX
423 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
424 * @arg @ref LL_AHB2_GRP1_PERIPH_USBO
425 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC3
426 * @retval None
427 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)428 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
429 {
430 WRITE_REG(RCC->AHB2RSTCLRR, Periphs);
431 }
432
433 /**
434 * @brief Enable AHB2 peripheral clocks in Sleep mode
435 * @rmtoll MC_AHB2LPENSETR DMA1 LL_AHB2_GRP1_EnableClockSleep\n
436 * MC_AHB2LPENSETR DMA2 LL_AHB2_GRP1_EnableClockSleep\n
437 * MC_AHB2LPENSETR DMAMUX LL_AHB2_GRP1_EnableClockSleep\n
438 * MC_AHB2LPENSETR ADC12 LL_AHB2_GRP1_EnableClockSleep\n
439 * MC_AHB2LPENSETR USBO LL_AHB2_GRP1_EnableClockSleep\n
440 * MC_AHB2LPENCLRR SDMMC3 LL_AHB2_GRP1_EnableClockSleep
441 * @param Periphs This parameter can be a combination of the following values:
442 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA1
443 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA2
444 * @arg @ref LL_AHB2_GRP1_PERIPH_DMAMUX
445 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
446 * @arg @ref LL_AHB2_GRP1_PERIPH_USBO
447 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC3
448 * @retval None
449 */
LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)450 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
451 {
452 __IO uint32_t tmpreg;
453 WRITE_REG(RCC->MC_AHB2LPENSETR, Periphs);
454 /* Delay after an RCC peripheral clock enabling */
455 tmpreg = READ_BIT(RCC->MC_AHB2LPENSETR, Periphs);
456 (void)tmpreg;
457 }
458
459 /**
460 * @brief Disable AHB2 peripheral clocks in Sleep mode
461 * @rmtoll MC_AHB2LPENCLRR DMA1 LL_AHB2_GRP1_DisableClockSleep\n
462 * MC_AHB2LPENCLRR DMA2 LL_AHB2_GRP1_DisableClockSleep\n
463 * MC_AHB2LPENCLRR DMAMUX LL_AHB2_GRP1_DisableClockSleep\n
464 * MC_AHB2LPENCLRR ADC12 LL_AHB2_GRP1_DisableClockSleep\n
465 * MC_AHB2LPENCLRR USBO LL_AHB2_GRP1_DisableClockSleep\n
466 * MC_AHB2LPENCLRR SDMMC3 LL_AHB2_GRP1_DisableClockSleep
467 * @param Periphs This parameter can be a combination of the following values:
468 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA1
469 * @arg @ref LL_AHB2_GRP1_PERIPH_DMA2
470 * @arg @ref LL_AHB2_GRP1_PERIPH_DMAMUX
471 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
472 * @arg @ref LL_AHB2_GRP1_PERIPH_USBO
473 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC3
474 * @retval None
475 */
LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)476 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
477 {
478 WRITE_REG(RCC->MC_AHB2LPENCLRR, Periphs);
479 }
480
481 /**
482 * @}
483 */
484
485 /** @defgroup BUS_LL_EF_AHB3 AHB3
486 * @{
487 */
488
489 /**
490 * @brief Enable AHB3 peripherals clock.
491 * @rmtoll MC_AHB3ENSETR DCMI LL_AHB3_GRP1_EnableClock\n
492 * MC_AHB3ENSETR CRYP2 LL_AHB3_GRP1_EnableClock\n
493 * MC_AHB3ENSETR HASH2 LL_AHB3_GRP1_EnableClock\n
494 * MC_AHB3ENSETR RNG2 LL_AHB3_GRP1_EnableClock\n
495 * MC_AHB3ENSETR CRC2 LL_AHB3_GRP1_EnableClock\n
496 * MC_AHB3ENSETR HSEM LL_AHB3_GRP1_EnableClock\n
497 * MC_AHB3ENSETR IPCC LL_AHB3_GRP1_EnableClock
498 * @param Periphs This parameter can be a combination of the following values:
499 * @arg @ref LL_AHB3_GRP1_PERIPH_DCMI
500 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP2 (*)
501 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH2
502 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG2
503 * @arg @ref LL_AHB3_GRP1_PERIPH_CRC2
504 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
505 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
506 *
507 * (*) value not defined in all devices.
508 * @retval None
509 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)510 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
511 {
512 __IO uint32_t tmpreg;
513 WRITE_REG(RCC->MC_AHB3ENSETR, Periphs);
514 /* Delay after an RCC peripheral clock enabling */
515 tmpreg = READ_BIT(RCC->MC_AHB3ENSETR, Periphs);
516 (void)tmpreg;
517 }
518
519 /**
520 * @brief Check if AHB3 peripheral clock is enabled or not
521 * @rmtoll MC_AHB3ENSETR DCMI LL_AHB3_GRP1_IsEnabledClock\n
522 * MC_AHB3ENSETR CRYP2 LL_AHB3_GRP1_IsEnabledClock\n
523 * MC_AHB3ENSETR HASH2 LL_AHB3_GRP1_IsEnabledClock\n
524 * MC_AHB3ENSETR RNG2 LL_AHB3_GRP1_IsEnabledClock\n
525 * MC_AHB3ENSETR CRC2 LL_AHB3_GRP1_IsEnabledClock\n
526 * MC_AHB3ENSETR HSEM LL_AHB3_GRP1_IsEnabledClock\n
527 * MC_AHB3ENSETR IPCC LL_AHB3_GRP1_IsEnabledClock
528 * @param Periphs This parameter can be a combination of the following values:
529 * @arg @ref LL_AHB3_GRP1_PERIPH_DCMI
530 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP2 (*)
531 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH2
532 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG2
533 * @arg @ref LL_AHB3_GRP1_PERIPH_CRC2
534 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
535 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
536 *
537 * (*) value not defined in all devices.
538 * @retval State of Periphs (1 or 0).
539 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)540 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
541 {
542 return (READ_BIT(RCC->MC_AHB3ENSETR, Periphs) == Periphs);
543 }
544
545 /**
546 * @brief Disable AHB3 peripherals clock.
547 * @rmtoll MC_AHB3ENCLRR DCMI LL_AHB3_GRP1_DisableClock\n
548 * MC_AHB3ENCLRR CRYP2 LL_AHB3_GRP1_DisableClock\n
549 * MC_AHB3ENCLRR HASH2 LL_AHB3_GRP1_DisableClock\n
550 * MC_AHB3ENCLRR RNG2 LL_AHB3_GRP1_DisableClock\n
551 * MC_AHB3ENCLRR CRC2 LL_AHB3_GRP1_DisableClock\n
552 * MC_AHB3ENCLRR HSEM LL_AHB3_GRP1_DisableClock\n
553 * MC_AHB3ENCLRR IPCC LL_AHB3_GRP1_DisableClock
554 * @param Periphs This parameter can be a combination of the following values:
555 * @arg @ref LL_AHB3_GRP1_PERIPH_DCMI
556 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP2 (*)
557 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH2
558 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG2
559 * @arg @ref LL_AHB3_GRP1_PERIPH_CRC2
560 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
561 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
562 *
563 * (*) value not defined in all devices.
564 * @retval None
565 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)566 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
567 {
568 WRITE_REG(RCC->MC_AHB3ENCLRR, Periphs);
569 }
570
571 /**
572 * @brief Force AHB3 peripherals reset.
573 * @rmtoll AHB3RSTSETR DCMI LL_AHB3_GRP1_ForceReset\n
574 * AHB3RSTSETR CRYP2 LL_AHB3_GRP1_ForceReset\n
575 * AHB3RSTSETR HASH2 LL_AHB3_GRP1_ForceReset\n
576 * AHB3RSTSETR RNG2 LL_AHB3_GRP1_ForceReset\n
577 * AHB3RSTSETR CRC2 LL_AHB3_GRP1_ForceReset\n
578 * AHB3RSTSETR HSEM LL_AHB3_GRP1_ForceReset\n
579 * AHB3RSTSETR IPCC LL_AHB3_GRP1_ForceReset
580 * @param Periphs This parameter can be a combination of the following values:
581 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
582 * @arg @ref LL_AHB3_GRP1_PERIPH_DCMI
583 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP2 (*)
584 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH2
585 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG2
586 * @arg @ref LL_AHB3_GRP1_PERIPH_CRC2
587 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
588 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
589 *
590 * (*) value not defined in all devices.
591 * @retval None
592 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)593 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
594 {
595 WRITE_REG(RCC->AHB3RSTSETR, Periphs);
596 }
597
598 /**
599 * @brief Release AHB3 peripherals reset.
600 * @rmtoll AHB3RSTCLRR DCMI LL_AHB3_GRP1_ReleaseReset\n
601 * AHB3RSTCLRR CRYP2 LL_AHB3_GRP1_ReleaseReset\n
602 * AHB3RSTCLRR HASH2 LL_AHB3_GRP1_ReleaseReset\n
603 * AHB3RSTCLRR RNG2 LL_AHB3_GRP1_ReleaseReset\n
604 * AHB3RSTCLRR CRC2 LL_AHB3_GRP1_ReleaseReset\n
605 * AHB3RSTCLRR HSEM LL_AHB3_GRP1_ReleaseReset\n
606 * AHB3RSTCLRR IPCC LL_AHB3_GRP1_ReleaseReset
607 * @param Periphs This parameter can be a combination of the following values:
608 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
609 * @arg @ref LL_AHB3_GRP1_PERIPH_DCMI
610 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP2 (*)
611 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH2
612 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG2
613 * @arg @ref LL_AHB3_GRP1_PERIPH_CRC2
614 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
615 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
616 *
617 * (*) value not defined in all devices.
618 * @retval None
619 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)620 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
621 {
622 WRITE_REG(RCC->AHB3RSTCLRR, Periphs);
623 }
624
625 /**
626 * @brief Enable AHB3 peripheral clocks in Sleep mode
627 * @rmtoll MC_AHB3LPENSETR DCMI LL_AHB3_GRP1_EnableClockSleep\n
628 * MC_AHB3LPENSETR CRYP2 LL_AHB3_GRP1_EnableClockSleep\n
629 * MC_AHB3LPENSETR HASH2 LL_AHB3_GRP1_EnableClockSleep\n
630 * MC_AHB3LPENSETR RNG2 LL_AHB3_GRP1_EnableClockSleep\n
631 * MC_AHB3LPENSETR CRC2 LL_AHB3_GRP1_EnableClockSleep\n
632 * MC_AHB3LPENSETR HSEM LL_AHB3_GRP1_EnableClockSleep\n
633 * MC_AHB3LPENSETR IPCC LL_AHB3_GRP1_EnableClockSleep
634 * @param Periphs This parameter can be a combination of the following values:
635 * @arg @ref LL_AHB3_GRP1_PERIPH_DCMI
636 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP2 (*)
637 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH2
638 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG2
639 * @arg @ref LL_AHB3_GRP1_PERIPH_CRC2
640 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
641 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
642 *
643 * (*) value not defined in all devices.
644 * @retval None
645 */
LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)646 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
647 {
648 __IO uint32_t tmpreg;
649 WRITE_REG(RCC->MC_AHB3LPENSETR, Periphs);
650 /* Delay after an RCC peripheral clock enabling */
651 tmpreg = READ_BIT(RCC->MC_AHB3LPENSETR, Periphs);
652 (void)tmpreg;
653 }
654
655 /**
656 * @brief Disable AHB3 peripheral clocks in Sleep mode
657 * @rmtoll MC_AHB3LPENCLRR DCMI LL_AHB3_GRP1_DisableClockSleep\n
658 * MC_AHB3LPENCLRR CRYP2 LL_AHB3_GRP1_DisableClockSleep\n
659 * MC_AHB3LPENCLRR HASH2 LL_AHB3_GRP1_DisableClockSleep\n
660 * MC_AHB3LPENCLRR RNG2 LL_AHB3_GRP1_DisableClockSleep\n
661 * MC_AHB3LPENCLRR CRC2 LL_AHB3_GRP1_DisableClockSleep\n
662 * MC_AHB3LPENCLRR HSEM LL_AHB3_GRP1_DisableClockSleep\n
663 * MC_AHB3LPENCLRR IPCC LL_AHB3_GRP1_DisableClockSleep
664 *
665 * @param Periphs This parameter can be a combination of the following values:
666 * @arg @ref LL_AHB3_GRP1_PERIPH_DCMI
667 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP2 (*)
668 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH2
669 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG2
670 * @arg @ref LL_AHB3_GRP1_PERIPH_CRC2
671 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
672 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
673 *
674 * (*) value not defined in all devices.
675 * @retval None
676 */
LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)677 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
678 {
679 WRITE_REG(RCC->MC_AHB3LPENCLRR, Periphs);
680 }
681
682 /**
683 * @}
684 */
685
686 /** @defgroup BUS_LL_EF_AHB4 AHB4
687 * @{
688 */
689
690 /**
691 * @brief Enable AHB4 peripherals clock.
692 * @rmtoll MC_AHB4ENSETR GPIOA LL_AHB4_GRP1_EnableClock\n
693 * MC_AHB4ENSETR GPIOB LL_AHB4_GRP1_EnableClock\n
694 * MC_AHB4ENSETR GPIOC LL_AHB4_GRP1_EnableClock\n
695 * MC_AHB4ENSETR GPIOD LL_AHB4_GRP1_EnableClock\n
696 * MC_AHB4ENSETR GPIOE LL_AHB4_GRP1_EnableClock\n
697 * MC_AHB4ENSETR GPIOF LL_AHB4_GRP1_EnableClock\n
698 * MC_AHB4ENSETR GPIOG LL_AHB4_GRP1_EnableClock\n
699 * MC_AHB4ENSETR GPIOH LL_AHB4_GRP1_EnableClock\n
700 * MC_AHB4ENSETR GPIOI LL_AHB4_GRP1_EnableClock\n
701 * MC_AHB4ENSETR GPIOJ LL_AHB4_GRP1_EnableClock\n
702 * MC_AHB4ENSETR GPIOK LL_AHB4_GRP1_EnableClock
703 * @param Periphs This parameter can be a combination of the following values:
704 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
705 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
706 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
707 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
708 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
709 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
710 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
711 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
712 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
713 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
714 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
715 * @retval None
716 */
LL_AHB4_GRP1_EnableClock(uint32_t Periphs)717 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
718 {
719 __IO uint32_t tmpreg;
720 WRITE_REG(RCC->MC_AHB4ENSETR, Periphs);
721 /* Delay after an RCC peripheral clock enabling */
722 tmpreg = READ_BIT(RCC->MC_AHB4ENSETR, Periphs);
723 (void)tmpreg;
724 }
725
726 /**
727 * @brief Check if AHB4 peripheral clock is enabled or not
728 * @rmtoll MC_AHB4ENSETR GPIOA LL_AHB4_GRP1_IsEnabledClock\n
729 * MC_AHB4ENSETR GPIOB LL_AHB4_GRP1_IsEnabledClock\n
730 * MC_AHB4ENSETR GPIOC LL_AHB4_GRP1_IsEnabledClock\n
731 * MC_AHB4ENSETR GPIOD LL_AHB4_GRP1_IsEnabledClock\n
732 * MC_AHB4ENSETR GPIOE LL_AHB4_GRP1_IsEnabledClock\n
733 * MC_AHB4ENSETR GPIOF LL_AHB4_GRP1_IsEnabledClock\n
734 * MC_AHB4ENSETR GPIOG LL_AHB4_GRP1_IsEnabledClock\n
735 * MC_AHB4ENSETR GPIOH LL_AHB4_GRP1_IsEnabledClock\n
736 * MC_AHB4ENSETR GPIOI LL_AHB4_GRP1_IsEnabledClock\n
737 * MC_AHB4ENSETR GPIOJ LL_AHB4_GRP1_IsEnabledClock\n
738 * MC_AHB4ENSETR GPIOK LL_AHB4_GRP1_IsEnabledClock
739 * @param Periphs This parameter can be a combination of the following values:
740 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
741 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
742 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
743 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
744 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
745 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
746 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
747 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
748 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
749 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
750 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
751 * @retval State of Periphs (1 or 0).
752 */
LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)753 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
754 {
755 return (READ_BIT(RCC->MC_AHB4ENSETR, Periphs) == Periphs);
756 }
757
758 /**
759 * @brief Disable AHB4 peripherals clock.
760 * @rmtoll MC_AHB4ENCLRR GPIOA LL_AHB4_GRP1_DisableClock\n
761 * MC_AHB4ENCLRR GPIOB LL_AHB4_GRP1_DisableClock\n
762 * MC_AHB4ENCLRR GPIOC LL_AHB4_GRP1_DisableClock\n
763 * MC_AHB4ENCLRR GPIOD LL_AHB4_GRP1_DisableClock\n
764 * MC_AHB4ENCLRR GPIOE LL_AHB4_GRP1_DisableClock\n
765 * MC_AHB4ENCLRR GPIOF LL_AHB4_GRP1_DisableClock\n
766 * MC_AHB4ENCLRR GPIOG LL_AHB4_GRP1_DisableClock\n
767 * MC_AHB4ENCLRR GPIOH LL_AHB4_GRP1_DisableClock\n
768 * MC_AHB4ENCLRR GPIOI LL_AHB4_GRP1_DisableClock\n
769 * MC_AHB4ENCLRR GPIOJ LL_AHB4_GRP1_DisableClock\n
770 * MC_AHB4ENCLRR GPIOK LL_AHB4_GRP1_DisableClock
771 * @param Periphs This parameter can be a combination of the following values:
772 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
773 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
774 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
775 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
776 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
777 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
778 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
779 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
780 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
781 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
782 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
783 *
784 * (*) value not defined in all devices.
785 * @retval None
786 */
LL_AHB4_GRP1_DisableClock(uint32_t Periphs)787 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
788 {
789 WRITE_REG(RCC->MC_AHB4ENCLRR, Periphs);
790 }
791
792 /**
793 * @brief Force AHB4 peripherals reset.
794 * @rmtoll AHB4RSTSETR GPIOA LL_AHB4_GRP1_ForceReset\n
795 * AHB4RSTSETR GPIOB LL_AHB4_GRP1_ForceReset\n
796 * AHB4RSTSETR GPIOC LL_AHB4_GRP1_ForceReset\n
797 * AHB4RSTSETR GPIOD LL_AHB4_GRP1_ForceReset\n
798 * AHB4RSTSETR GPIOE LL_AHB4_GRP1_ForceReset\n
799 * AHB4RSTSETR GPIOF LL_AHB4_GRP1_ForceReset\n
800 * AHB4RSTSETR GPIOG LL_AHB4_GRP1_ForceReset\n
801 * AHB4RSTSETR GPIOH LL_AHB4_GRP1_ForceReset\n
802 * AHB4RSTSETR GPIOI LL_AHB4_GRP1_ForceReset\n
803 * AHB4RSTSETR GPIOJ LL_AHB4_GRP1_ForceReset\n
804 * AHB4RSTSETR GPIOK LL_AHB4_GRP1_ForceReset
805 * @param Periphs This parameter can be a combination of the following values:
806 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
807 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
808 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
809 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
810 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
811 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
812 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
813 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
814 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
815 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
816 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
817 * @retval None
818 */
LL_AHB4_GRP1_ForceReset(uint32_t Periphs)819 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
820 {
821 WRITE_REG(RCC->AHB4RSTSETR, Periphs);
822 }
823
824 /**
825 * @brief Release AHB4 peripherals reset.
826 * @rmtoll AHB4RSTCLRR GPIOA LL_AHB4_GRP1_ReleaseReset\n
827 * AHB4RSTCLRR GPIOB LL_AHB4_GRP1_ReleaseReset\n
828 * AHB4RSTCLRR GPIOC LL_AHB4_GRP1_ReleaseReset\n
829 * AHB4RSTCLRR GPIOD LL_AHB4_GRP1_ReleaseReset\n
830 * AHB4RSTCLRR GPIOE LL_AHB4_GRP1_ReleaseReset\n
831 * AHB4RSTCLRR GPIOF LL_AHB4_GRP1_ReleaseReset\n
832 * AHB4RSTCLRR GPIOG LL_AHB4_GRP1_ReleaseReset\n
833 * AHB4RSTCLRR GPIOH LL_AHB4_GRP1_ReleaseReset\n
834 * AHB4RSTCLRR GPIOI LL_AHB4_GRP1_ReleaseReset\n
835 * AHB4RSTCLRR GPIOJ LL_AHB4_GRP1_ReleaseReset\n
836 * AHB4RSTCLRR GPIOK LL_AHB4_GRP1_ReleaseReset
837 * @param Periphs This parameter can be a combination of the following values:
838 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
839 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
840 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
841 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
842 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
843 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
844 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
845 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
846 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
847 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
848 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
849 * @retval None
850 */
LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)851 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
852 {
853 WRITE_REG(RCC->AHB4RSTCLRR, Periphs);
854 }
855
856 /**
857 * @brief Enable AHB4 peripheral clocks in Sleep mode
858 * @rmtoll MC_AHB4LPENSETR GPIOA LL_AHB4_GRP1_EnableClockSleep\n
859 * MC_AHB4LPENSETR GPIOB LL_AHB4_GRP1_EnableClockSleep\n
860 * MC_AHB4LPENSETR GPIOC LL_AHB4_GRP1_EnableClockSleep\n
861 * MC_AHB4LPENSETR GPIOD LL_AHB4_GRP1_EnableClockSleep\n
862 * MC_AHB4LPENSETR GPIOE LL_AHB4_GRP1_EnableClockSleep\n
863 * MC_AHB4LPENSETR GPIOF LL_AHB4_GRP1_EnableClockSleep\n
864 * MC_AHB4LPENSETR GPIOG LL_AHB4_GRP1_EnableClockSleep\n
865 * MC_AHB4LPENSETR GPIOH LL_AHB4_GRP1_EnableClockSleep\n
866 * MC_AHB4LPENSETR GPIOI LL_AHB4_GRP1_EnableClockSleep\n
867 * MC_AHB4LPENSETR GPIOJ LL_AHB4_GRP1_EnableClockSleep\n
868 * MC_AHB4LPENSETR GPIOK LL_AHB4_GRP1_EnableClockSleep
869 * @param Periphs This parameter can be a combination of the following values:
870 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
871 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
872 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
873 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
874 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
875 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
876 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
877 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
878 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
879 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
880 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
881 *
882 * (*) value not defined in all devices.
883 * @retval None
884 */
LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)885 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
886 {
887 __IO uint32_t tmpreg;
888 WRITE_REG(RCC->MC_AHB4LPENSETR, Periphs);
889 /* Delay after an RCC peripheral clock enabling */
890 tmpreg = READ_BIT(RCC->MC_AHB4LPENSETR, Periphs);
891 (void)tmpreg;
892 }
893
894 /**
895 * @brief Disable AHB4 peripheral clocks in Sleep modes
896 * @rmtoll MC_AHB4LPENCLRR GPIOA LL_AHB4_GRP1_DisableClockSleep\n
897 * MC_AHB4LPENCLRR GPIOB LL_AHB4_GRP1_DisableClockSleep\n
898 * MC_AHB4LPENCLRR GPIOC LL_AHB4_GRP1_DisableClockSleep\n
899 * MC_AHB4LPENCLRR GPIOD LL_AHB4_GRP1_DisableClockSleep\n
900 * MC_AHB4LPENCLRR GPIOE LL_AHB4_GRP1_DisableClockSleep\n
901 * MC_AHB4LPENCLRR GPIOF LL_AHB4_GRP1_DisableClockSleep\n
902 * MC_AHB4LPENCLRR GPIOG LL_AHB4_GRP1_DisableClockSleep\n
903 * MC_AHB4LPENCLRR GPIOH LL_AHB4_GRP1_DisableClockSleep\n
904 * MC_AHB4LPENCLRR GPIOI LL_AHB4_GRP1_DisableClockSleep\n
905 * MC_AHB4LPENCLRR GPIOJ LL_AHB4_GRP1_DisableClockSleep\n
906 * MC_AHB4LPENCLRR GPIOK LL_AHB4_GRP1_DisableClockSleep
907 * @param Periphs This parameter can be a combination of the following values:
908 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
909 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
910 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
911 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
912 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
913 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
914 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
915 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
916 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
917 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
918 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
919 * @retval None
920 */
LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)921 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
922 {
923 WRITE_REG(RCC->MC_AHB4LPENCLRR, Periphs);
924 }
925
926 /**
927 * @}
928 */
929
930 /** @defgroup BUS_LL_EF_AHB5 AHB5
931 * @{
932 */
933
934 /**
935 * @brief Enable AHB5 peripherals clock.
936 * @rmtoll MC_AHB5ENSETR GPIOZ LL_AHB5_GRP1_EnableClock\n
937 * MC_AHB5ENSETR CRYP1 LL_AHB5_GRP1_EnableClock\n
938 * MC_AHB5ENSETR HASH1 LL_AHB5_GRP1_EnableClock\n
939 * MC_AHB5ENSETR RNG1 LL_AHB5_GRP1_EnableClock\n
940 * MC_AHB5ENSETR BKPSRAM LL_AHB5_GRP1_EnableClock
941 * @param Periphs This parameter can be a combination of the following values:
942 * @arg @ref LL_AHB5_GRP1_PERIPH_GPIOZ
943 * @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
944 * @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
945 * @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
946 * @arg @ref LL_AHB5_GRP1_PERIPH_BKPSRAM
947 *
948 * (*) value not defined in all devices.
949 * @retval None
950 */
LL_AHB5_GRP1_EnableClock(uint32_t Periphs)951 __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs)
952 {
953 __IO uint32_t tmpreg;
954 WRITE_REG(RCC->MC_AHB5ENSETR, Periphs);
955 /* Delay after an RCC peripheral clock enabling */
956 tmpreg = READ_BIT(RCC->MC_AHB5ENSETR, Periphs);
957 (void)tmpreg;
958 }
959
960 /**
961 * @brief Check if AHB5 peripheral clock is enabled or not
962 * @rmtoll MC_AHB5ENSETR GPIOZ LL_AHB5_GRP1_IsEnabledClock\n
963 * MC_AHB5ENSETR CRYP1 LL_AHB5_GRP1_IsEnabledClock\n
964 * MC_AHB5ENSETR HASH1 LL_AHB5_GRP1_IsEnabledClock\n
965 * MC_AHB5ENSETR RNG1 LL_AHB5_GRP1_IsEnabledClock\n
966 * MC_AHB5ENSETR BKPSRAM LL_AHB5_GRP1_IsEnabledClock
967 * @param Periphs This parameter can be a combination of the following values:
968 * @arg @ref LL_AHB5_GRP1_PERIPH_GPIOZ
969 * @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
970 * @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
971 * @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
972 * @arg @ref LL_AHB5_GRP1_PERIPH_BKPSRAM
973 *
974 * (*) value not defined in all devices.
975 * @retval State of Periphs (1 or 0).
976 */
LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)977 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)
978 {
979 return (READ_BIT(RCC->MC_AHB5ENSETR, Periphs) == Periphs);
980 }
981
982 /**
983 * @brief Disable AHB5 peripherals clock.
984 * @rmtoll MC_AHB5ENCLRR GPIOZ LL_AHB5_GRP1_DisableClock\n
985 * MC_AHB5ENCLRR CRYP1 LL_AHB5_GRP1_DisableClock\n
986 * MC_AHB5ENCLRR HASH1 LL_AHB5_GRP1_DisableClock\n
987 * MC_AHB5ENCLRR RNG1 LL_AHB5_GRP1_DisableClock\n
988 * MC_AHB5ENCLRR BKPSRAM LL_AHB5_GRP1_DisableClock
989 * @param Periphs This parameter can be a combination of the following values:
990 * @arg @ref LL_AHB5_GRP1_PERIPH_GPIOZ
991 * @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
992 * @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
993 * @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
994 * @arg @ref LL_AHB5_GRP1_PERIPH_BKPSRAM
995 *
996 * (*) value not defined in all devices.
997 * @retval None
998 */
LL_AHB5_GRP1_DisableClock(uint32_t Periphs)999 __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs)
1000 {
1001 WRITE_REG(RCC->MC_AHB5ENCLRR, Periphs);
1002 }
1003
1004 /**
1005 * @brief Force AHB5 peripherals reset.
1006 * @rmtoll AHB5RSTSETR GPIOZ LL_AHB5_GRP1_ForceReset\n
1007 * AHB5RSTSETR CRYP1 LL_AHB5_GRP1_ForceReset\n
1008 * AHB5RSTSETR HASH1 LL_AHB5_GRP1_ForceReset\n
1009 * AHB5RSTSETR RNG1 LL_AHB5_GRP1_ForceReset\n
1010 * AHB5RSTSETR AXIMC LL_AHB5_GRP1_ForceReset
1011 * @param Periphs This parameter can be a combination of the following values:
1012 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
1013 * @arg @ref LL_AHB5_GRP1_PERIPH_GPIOZ
1014 * @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
1015 * @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
1016 * @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
1017 *
1018 * (*) value not defined in all devices.
1019 * @retval None
1020 */
LL_AHB5_GRP1_ForceReset(uint32_t Periphs)1021 __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs)
1022 {
1023 WRITE_REG(RCC->AHB5RSTSETR, Periphs);
1024 }
1025
1026 /**
1027 * @brief Release AHB5 peripherals reset.
1028 * @rmtoll AHB5RSTCLRR GPIOZ LL_AHB5_GRP1_ReleaseReset\n
1029 * AHB5RSTCLRR CRYP1 LL_AHB5_GRP1_ReleaseReset\n
1030 * AHB5RSTCLRR HASH1 LL_AHB5_GRP1_ReleaseReset\n
1031 * AHB5RSTCLRR RNG1 LL_AHB5_GRP1_ReleaseReset\n
1032 * AHB5RSTCLRR AXIMC LL_AHB5_GRP1_ReleaseReset
1033 * @param Periphs This parameter can be a combination of the following values:
1034 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
1035 * @arg @ref LL_AHB5_GRP1_PERIPH_GPIOZ
1036 * @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
1037 * @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
1038 * @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
1039 *
1040 * (*) value not defined in all devices.
1041 * @retval None
1042 */
LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)1043 __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)
1044 {
1045 WRITE_REG(RCC->AHB5RSTCLRR, Periphs);
1046 }
1047
1048 /**
1049 * @brief Enable AHB5 peripheral clocks in Sleep mode
1050 * @rmtoll MC_AHB5LPENSETR GPIOZ LL_AHB5_GRP1_EnableClockSleep\n
1051 * MC_AHB5LPENSETR CRYP1 LL_AHB5_GRP1_EnableClockSleep\n
1052 * MC_AHB5LPENSETR HASH1 LL_AHB5_GRP1_EnableClockSleep\n
1053 * MC_AHB5LPENSETR RNG1 LL_AHB5_GRP1_EnableClockSleep\n
1054 * MC_AHB5LPENSETR BKPSRAM LL_AHB5_GRP1_EnableClockSleep
1055 * @param Periphs This parameter can be a combination of the following values:
1056 * @arg @ref LL_AHB5_GRP1_PERIPH_GPIOZ
1057 * @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
1058 * @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
1059 * @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
1060 * @arg @ref LL_AHB5_GRP1_PERIPH_BKPSRAM
1061 *
1062 * (*) value not defined in all devices.
1063 * @retval None
1064 */
LL_AHB5_GRP1_EnableClockSleep(uint32_t Periphs)1065 __STATIC_INLINE void LL_AHB5_GRP1_EnableClockSleep(uint32_t Periphs)
1066 {
1067 __IO uint32_t tmpreg;
1068 WRITE_REG(RCC->MC_AHB5LPENSETR, Periphs);
1069 /* Delay after an RCC peripheral clock enabling */
1070 tmpreg = READ_BIT(RCC->MC_AHB5LPENSETR, Periphs);
1071 (void)tmpreg;
1072 }
1073
1074 /**
1075 * @brief Disable AHB5 peripheral clocks in Sleep mode
1076 * @rmtoll MC_AHB5LPENCLRR GPIOZ LL_AHB5_GRP1_DisableClockSleep\n
1077 * MC_AHB5LPENCLRR CRYP1 LL_AHB5_GRP1_DisableClockSleep\n
1078 * MC_AHB5LPENCLRR HASH1 LL_AHB5_GRP1_DisableClockSleep\n
1079 * MC_AHB5LPENCLRR RNG1 LL_AHB5_GRP1_DisableClockSleep\n
1080 * MC_AHB5LPENCLRR BKPSRAM LL_AHB5_GRP1_DisableClockSleep
1081 * @param Periphs This parameter can be a combination of the following values:
1082 * @arg @ref LL_AHB5_GRP1_PERIPH_GPIOZ
1083 * @arg @ref LL_AHB5_GRP1_PERIPH_CRYP1 (*)
1084 * @arg @ref LL_AHB5_GRP1_PERIPH_HASH1
1085 * @arg @ref LL_AHB5_GRP1_PERIPH_RNG1
1086 * @arg @ref LL_AHB5_GRP1_PERIPH_BKPSRAM
1087 *
1088 * (*) value not defined in all devices.
1089 * @retval None
1090 */
LL_AHB5_GRP1_DisableClockSleep(uint32_t Periphs)1091 __STATIC_INLINE void LL_AHB5_GRP1_DisableClockSleep(uint32_t Periphs)
1092 {
1093 WRITE_REG(RCC->MC_AHB5LPENCLRR, Periphs);
1094 }
1095
1096 /**
1097 * @}
1098 */
1099
1100 /** @defgroup BUS_LL_EF_AHB6 AHB6
1101 * @{
1102 */
1103
1104 /**
1105 * @brief Enable AHB6 peripherals clock.
1106 * @rmtoll MC_AHB6ENSETR MDMA LL_AHB6_GRP1_EnableClock\n
1107 * MC_AHB6ENSETR GPU LL_AHB6_GRP1_EnableClock\n
1108 * MC_AHB6ENSETR ETH1CK LL_AHB6_GRP1_EnableClock\n
1109 * MC_AHB6ENSETR ETH1TX LL_AHB6_GRP1_EnableClock\n
1110 * MC_AHB6ENSETR ETH1RX LL_AHB6_GRP1_EnableClock\n
1111 * MC_AHB6ENSETR ETH1MAC LL_AHB6_GRP1_EnableClock\n
1112 * MC_AHB6ENSETR FMC LL_AHB6_GRP1_EnableClock\n
1113 * MC_AHB6ENSETR QSPI LL_AHB6_GRP1_EnableClock\n
1114 * MC_AHB6ENSETR SDMMC1 LL_AHB6_GRP1_EnableClock\n
1115 * MC_AHB6ENSETR SDMMC2 LL_AHB6_GRP1_EnableClock\n
1116 * MC_AHB6ENSETR CRC1 LL_AHB6_GRP1_EnableClock\n
1117 * MC_AHB6ENSETR USBH LL_AHB6_GRP1_EnableClock
1118 * @param Periphs This parameter can be a combination of the following values:
1119 * @arg @ref LL_AHB6_GRP1_PERIPH_MDMA
1120 * @arg @ref LL_AHB6_GRP1_PERIPH_GPU
1121 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1CK
1122 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1TX
1123 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1RX
1124 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1MAC
1125 * @arg @ref LL_AHB6_GRP1_PERIPH_FMC
1126 * @arg @ref LL_AHB6_GRP1_PERIPH_QSPI
1127 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC1
1128 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC2
1129 * @arg @ref LL_AHB6_GRP1_PERIPH_CRC1
1130 * @arg @ref LL_AHB6_GRP1_PERIPH_USBH
1131 * @retval None
1132 */
LL_AHB6_GRP1_EnableClock(uint32_t Periphs)1133 __STATIC_INLINE void LL_AHB6_GRP1_EnableClock(uint32_t Periphs)
1134 {
1135 __IO uint32_t tmpreg;
1136 WRITE_REG(RCC->MC_AHB6ENSETR, Periphs);
1137 /* Delay after an RCC peripheral clock enabling */
1138 tmpreg = READ_BIT(RCC->MC_AHB6ENSETR, Periphs);
1139 (void)tmpreg;
1140 }
1141
1142 /**
1143 * @brief Check if AHB6 peripheral clock is enabled or not
1144 * @rmtoll MC_AHB6ENSETR MDMA LL_AHB6_GRP1_IsEnabledClock\n
1145 * MC_AHB6ENSETR GPU LL_AHB6_GRP1_IsEnabledClock\n
1146 * MC_AHB6ENSETR ETH1CK LL_AHB6_GRP1_IsEnabledClock\n
1147 * MC_AHB6ENSETR ETH1TX LL_AHB6_GRP1_IsEnabledClock\n
1148 * MC_AHB6ENSETR ETH1RX LL_AHB6_GRP1_IsEnabledClock\n
1149 * MC_AHB6ENSETR ETH1MAC LL_AHB6_GRP1_IsEnabledClock\n
1150 * MC_AHB6ENSETR FMC LL_AHB6_GRP1_IsEnabledClock\n
1151 * MC_AHB6ENSETR QSPI LL_AHB6_GRP1_IsEnabledClock\n
1152 * MC_AHB6ENSETR SDMMC1 LL_AHB6_GRP1_IsEnabledClock\n
1153 * MC_AHB6ENSETR SDMMC2 LL_AHB6_GRP1_IsEnabledClock\n
1154 * MC_AHB6ENSETR CRC1 LL_AHB6_GRP1_IsEnabledClock\n
1155 * MC_AHB6ENSETR USBH LL_AHB6_GRP1_IsEnabledClock
1156 * @param Periphs This parameter can be a combination of the following values:
1157 * @arg @ref LL_AHB6_GRP1_PERIPH_MDMA
1158 * @arg @ref LL_AHB6_GRP1_PERIPH_GPU
1159 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1CK
1160 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1TX
1161 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1RX
1162 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1MAC
1163 * @arg @ref LL_AHB6_GRP1_PERIPH_FMC
1164 * @arg @ref LL_AHB6_GRP1_PERIPH_QSPI
1165 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC1
1166 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC2
1167 * @arg @ref LL_AHB6_GRP1_PERIPH_CRC1
1168 * @arg @ref LL_AHB6_GRP1_PERIPH_USBH
1169 * @retval State of Periphs (1 or 0).
1170 */
LL_AHB6_GRP1_IsEnabledClock(uint32_t Periphs)1171 __STATIC_INLINE uint32_t LL_AHB6_GRP1_IsEnabledClock(uint32_t Periphs)
1172 {
1173 return (READ_BIT(RCC->MC_AHB6ENSETR, Periphs) == Periphs);
1174 }
1175
1176 /**
1177 * @brief Disable AHB6 peripherals clock.
1178 * @rmtoll MC_AHB6ENCLRR MDMA LL_AHB6_GRP1_DisableClock\n
1179 * MC_AHB6ENCLRR GPU LL_AHB6_GRP1_DisableClock\n
1180 * MC_AHB6ENCLRR ETH1CK LL_AHB6_GRP1_DisableClock\n
1181 * MC_AHB6ENCLRR ETH1TX LL_AHB6_GRP1_DisableClock\n
1182 * MC_AHB6ENCLRR ETH1RX LL_AHB6_GRP1_DisableClock\n
1183 * MC_AHB6ENCLRR ETH1MAC LL_AHB6_GRP1_DisableClock\n
1184 * MC_AHB6ENCLRR FMC LL_AHB6_GRP1_DisableClock\n
1185 * MC_AHB6ENCLRR QSPI LL_AHB6_GRP1_DisableClock\n
1186 * MC_AHB6ENCLRR SDMMC1 LL_AHB6_GRP1_DisableClock\n
1187 * MC_AHB6ENCLRR SDMMC2 LL_AHB6_GRP1_DisableClock\n
1188 * MC_AHB6ENCLRR CRC1 LL_AHB6_GRP1_DisableClock\n
1189 * MC_AHB6ENCLRR USBH LL_AHB6_GRP1_DisableClock
1190 * @param Periphs This parameter can be a combination of the following values:
1191 * @arg @ref LL_AHB6_GRP1_PERIPH_MDMA
1192 * @arg @ref LL_AHB6_GRP1_PERIPH_GPU
1193 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1CK
1194 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1TX
1195 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1RX
1196 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1MAC
1197 * @arg @ref LL_AHB6_GRP1_PERIPH_FMC
1198 * @arg @ref LL_AHB6_GRP1_PERIPH_QSPI
1199 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC1
1200 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC2
1201 * @arg @ref LL_AHB6_GRP1_PERIPH_CRC1
1202 * @arg @ref LL_AHB6_GRP1_PERIPH_USBH
1203 * @retval None
1204 */
LL_AHB6_GRP1_DisableClock(uint32_t Periphs)1205 __STATIC_INLINE void LL_AHB6_GRP1_DisableClock(uint32_t Periphs)
1206 {
1207 WRITE_REG(RCC->MC_AHB6ENCLRR, Periphs);
1208 }
1209
1210 /**
1211 * @brief Force AHB6 peripherals reset.
1212 * @rmtoll AHB6RSTSETR GPU LL_AHB6_GRP1_ForceReset\n
1213 * AHB6RSTSETR ETH1MAC LL_AHB6_GRP1_ForceReset\n
1214 * AHB6RSTSETR FMC LL_AHB6_GRP1_ForceReset\n
1215 * AHB6RSTSETR QSPI LL_AHB6_GRP1_ForceReset\n
1216 * AHB6RSTSETR SDMMC1 LL_AHB6_GRP1_ForceReset\n
1217 * AHB6RSTSETR SDMMC2 LL_AHB6_GRP1_ForceReset\n
1218 * AHB6RSTSETR CRC1 LL_AHB6_GRP1_ForceReset\n
1219 * AHB6RSTSETR USBH LL_AHB6_GRP1_ForceReset
1220 * @param Periphs This parameter can be a combination of the following values:
1221 * @arg @ref LL_AHB6_GRP1_PERIPH_GPU
1222 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1MAC
1223 * @arg @ref LL_AHB6_GRP1_PERIPH_FMC
1224 * @arg @ref LL_AHB6_GRP1_PERIPH_QSPI
1225 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC1
1226 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC2
1227 * @arg @ref LL_AHB6_GRP1_PERIPH_CRC1
1228 * @arg @ref LL_AHB6_GRP1_PERIPH_USBH
1229 * @retval None
1230 */
LL_AHB6_GRP1_ForceReset(uint32_t Periphs)1231 __STATIC_INLINE void LL_AHB6_GRP1_ForceReset(uint32_t Periphs)
1232 {
1233 WRITE_REG(RCC->AHB6RSTSETR, Periphs);
1234 }
1235
1236 /**
1237 * @brief Release AHB6 peripherals reset.
1238 * @rmtoll AHB6RSTCLRR ETH1MAC LL_AHB6_GRP1_ReleaseReset\n
1239 * AHB6RSTCLRR FMC LL_AHB6_GRP1_ReleaseReset\n
1240 * AHB6RSTCLRR QSPI LL_AHB6_GRP1_ReleaseReset\n
1241 * AHB6RSTCLRR SDMMC1 LL_AHB6_GRP1_ReleaseReset\n
1242 * AHB6RSTCLRR SDMMC2 LL_AHB6_GRP1_ReleaseReset\n
1243 * AHB6RSTCLRR CRC1 LL_AHB6_GRP1_ReleaseReset\n
1244 * AHB6RSTCLRR USBH LL_AHB6_GRP1_ReleaseReset
1245 * @param Periphs This parameter can be a combination of the following values:
1246 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1MAC
1247 * @arg @ref LL_AHB6_GRP1_PERIPH_FMC
1248 * @arg @ref LL_AHB6_GRP1_PERIPH_QSPI
1249 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC1
1250 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC2
1251 * @arg @ref LL_AHB6_GRP1_PERIPH_CRC1
1252 * @arg @ref LL_AHB6_GRP1_PERIPH_USBH
1253 * @retval None
1254 */
LL_AHB6_GRP1_ReleaseReset(uint32_t Periphs)1255 __STATIC_INLINE void LL_AHB6_GRP1_ReleaseReset(uint32_t Periphs)
1256 {
1257 WRITE_REG(RCC->AHB6RSTCLRR, Periphs);
1258 }
1259
1260 /**
1261 * @brief Enable AHB6 peripheral clocks in Sleep mode
1262 * @rmtoll MC_AHB6LPENSETR MDMA LL_AHB6_GRP1_EnableClockSleep\n
1263 * MC_AHB6LPENSETR GPU LL_AHB6_GRP1_EnableClockSleep\n
1264 * MC_AHB6LPENSETR ETH1CK LL_AHB6_GRP1_EnableClockSleep\n
1265 * MC_AHB6LPENSETR ETH1TX LL_AHB6_GRP1_EnableClockSleep\n
1266 * MC_AHB6LPENSETR ETH1RX LL_AHB6_GRP1_EnableClockSleep\n
1267 * MC_AHB6LPENSETR ETH1MAC LL_AHB6_GRP1_EnableClockSleep\n
1268 * MC_AHB6LPENSETR FMC LL_AHB6_GRP1_EnableClockSleep\n
1269 * MC_AHB6LPENSETR QSPI LL_AHB6_GRP1_EnableClockSleep\n
1270 * MC_AHB6LPENSETR SDMMC1 LL_AHB6_GRP1_EnableClockSleep\n
1271 * MC_AHB6LPENSETR SDMMC2 LL_AHB6_GRP1_EnableClockSleep\n
1272 * MC_AHB6LPENSETR CRC1 LL_AHB6_GRP1_EnableClockSleep\n
1273 * MC_AHB6LPENSETR USBH LL_AHB6_GRP1_EnableClockSleep
1274 * @param Periphs This parameter can be a combination of the following values:
1275 * @arg @ref LL_AHB6_GRP1_PERIPH_MDMA
1276 * @arg @ref LL_AHB6_GRP1_PERIPH_GPU
1277 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1CK
1278 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1TX
1279 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1RX
1280 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1MAC
1281 * @arg @ref LL_AHB6_GRP1_PERIPH_FMC
1282 * @arg @ref LL_AHB6_GRP1_PERIPH_QSPI
1283 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC1
1284 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC2
1285 * @arg @ref LL_AHB6_GRP1_PERIPH_CRC1
1286 * @arg @ref LL_AHB6_GRP1_PERIPH_USBH
1287 * @retval None
1288 */
LL_AHB6_GRP1_EnableClockSleep(uint32_t Periphs)1289 __STATIC_INLINE void LL_AHB6_GRP1_EnableClockSleep(uint32_t Periphs)
1290 {
1291 __IO uint32_t tmpreg;
1292 WRITE_REG(RCC->MC_AHB6LPENSETR, Periphs);
1293 /* Delay after an RCC peripheral clock enabling */
1294 tmpreg = READ_BIT(RCC->MC_AHB6LPENSETR, Periphs);
1295 (void)tmpreg;
1296 }
1297
1298 /**
1299 * @brief Disable AHB6 peripheral clocks in Sleep modes
1300 * @rmtoll MC_AHB6LPENCLRR MDMA LL_AHB6_GRP1_DisableClockSleep\n
1301 * MC_AHB6LPENCLRR GPU LL_AHB6_GRP1_DisableClockSleep\n
1302 * MC_AHB6LPENCLRR ETH1CK LL_AHB6_GRP1_DisableClockSleep\n
1303 * MC_AHB6LPENCLRR ETH1TX LL_AHB6_GRP1_DisableClockSleep\n
1304 * MC_AHB6LPENCLRR ETH1RX LL_AHB6_GRP1_DisableClockSleep\n
1305 * MC_AHB6LPENCLRR ETH1MAC LL_AHB6_GRP1_DisableClockSleep\n
1306 * MC_AHB6LPENCLRR FMC LL_AHB6_GRP1_DisableClockSleep\n
1307 * MC_AHB6LPENCLRR QSPI LL_AHB6_GRP1_DisableClockSleep\n
1308 * MC_AHB6LPENCLRR SDMMC1 LL_AHB6_GRP1_DisableClockSleep\n
1309 * MC_AHB6LPENCLRR SDMMC2 LL_AHB6_GRP1_DisableClockSleep\n
1310 * MC_AHB6LPENCLRR CRC1 LL_AHB6_GRP1_DisableClockSleep\n
1311 * MC_AHB6LPENCLRR USBH LL_AHB6_GRP1_DisableClockSleep
1312 * @param Periphs This parameter can be a combination of the following values:
1313 * @arg @ref LL_AHB6_GRP1_PERIPH_MDMA
1314 * @arg @ref LL_AHB6_GRP1_PERIPH_GPU
1315 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1CK
1316 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1TX
1317 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1RX
1318 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1MAC
1319 * @arg @ref LL_AHB6_GRP1_PERIPH_FMC
1320 * @arg @ref LL_AHB6_GRP1_PERIPH_QSPI
1321 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC1
1322 * @arg @ref LL_AHB6_GRP1_PERIPH_SDMMC2
1323 * @arg @ref LL_AHB6_GRP1_PERIPH_CRC1
1324 * @arg @ref LL_AHB6_GRP1_PERIPH_USBH
1325 * @retval None
1326 */
LL_AHB6_GRP1_DisableClockSleep(uint32_t Periphs)1327 __STATIC_INLINE void LL_AHB6_GRP1_DisableClockSleep(uint32_t Periphs)
1328 {
1329 WRITE_REG(RCC->MC_AHB6LPENCLRR, Periphs);
1330 }
1331
1332 /**
1333 * @brief Enable AHB6 peripheral clocks in Stop mode
1334 * @rmtoll MC_AHB6LPENSETR ETH1STP LL_AHB6_GRP1_EnableClockStop
1335 * @param Periphs This parameter can be a combination of the following values:
1336 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1STP
1337 * @retval None
1338 */
LL_AHB6_GRP1_EnableClockStop(uint32_t Periphs)1339 __STATIC_INLINE void LL_AHB6_GRP1_EnableClockStop(uint32_t Periphs)
1340 {
1341 __IO uint32_t tmpreg;
1342 WRITE_REG(RCC->MC_AHB6LPENSETR, Periphs);
1343 /* Delay after an RCC peripheral clock enabling */
1344 tmpreg = READ_BIT(RCC->MC_AHB6LPENSETR, Periphs);
1345 (void)tmpreg;
1346 }
1347
1348 /**
1349 * @brief Disable AHB6 peripheral clocks in Sleep modes
1350 * @rmtoll MC_AHB6LPENCLRR ETH1STP LL_AHB6_GRP1_DisableClockStop
1351 * @param Periphs This parameter can be a combination of the following values:
1352 * @arg @ref LL_AHB6_GRP1_PERIPH_ETH1STP
1353 * @retval None
1354 */
LL_AHB6_GRP1_DisableClockStop(uint32_t Periphs)1355 __STATIC_INLINE void LL_AHB6_GRP1_DisableClockStop(uint32_t Periphs)
1356 {
1357 WRITE_REG(RCC->MC_AHB6LPENCLRR, Periphs);
1358 }
1359
1360 /**
1361 * @}
1362 */
1363
1364 /** @defgroup BUS_LL_EF_AXI AXI
1365 * @{
1366 */
1367
1368 /**
1369 * @brief Enable AXI peripherals clock.
1370 * @rmtoll MC_AXIMENSETR SYSRAMEN LL_AXI_GRP1_EnableClock
1371 * @param Periphs This parameter can be a combination of the following values:
1372 * @arg @ref LL_AXI_GRP1_PERIPH_SYSRAMEN
1373 * @retval None
1374 */
LL_AXI_GRP1_EnableClock(uint32_t Periphs)1375 __STATIC_INLINE void LL_AXI_GRP1_EnableClock(uint32_t Periphs)
1376 {
1377 __IO uint32_t tmpreg;
1378 WRITE_REG(RCC->MC_AXIMENSETR, Periphs);
1379 /* Delay after an RCC peripheral clock enabling */
1380 tmpreg = READ_BIT(RCC->MC_AXIMENSETR, Periphs);
1381 (void)tmpreg;
1382 }
1383
1384 /**
1385 * @brief Check if AXI peripheral clock is enabled or not
1386 * @rmtoll MC_AXIMENSETR SYSRAMEN LL_AXI_GRP1_IsEnabledClock
1387 * @param Periphs This parameter can be a combination of the following values:
1388 * @arg @ref LL_AXI_GRP1_PERIPH_SYSRAMEN
1389 * @retval State of Periphs (1 or 0).
1390 */
LL_AXI_GRP1_IsEnabledClock(uint32_t Periphs)1391 __STATIC_INLINE uint32_t LL_AXI_GRP1_IsEnabledClock(uint32_t Periphs)
1392 {
1393 return (READ_BIT(RCC->MC_AXIMENSETR, Periphs) == Periphs);
1394 }
1395
1396 /**
1397 * @brief Disable AXI peripherals clock.
1398 * @rmtoll MC_AXIMENCLRR SYSRAMEN LL_AXI_GRP1_DisableClock
1399 * @param Periphs This parameter can be a combination of the following values:
1400 * @arg @ref LL_AXI_GRP1_PERIPH_SYSRAMEN
1401 * @retval None
1402 */
LL_AXI_GRP1_DisableClock(uint32_t Periphs)1403 __STATIC_INLINE void LL_AXI_GRP1_DisableClock(uint32_t Periphs)
1404 {
1405 WRITE_REG(RCC->MC_AXIMENCLRR, Periphs);
1406 }
1407
1408 /**
1409 * @brief Enable AXI peripheral clocks in Sleep mode
1410 * @rmtoll MC_AXIMLPENSETR SYSRAMEN LL_AXI_GRP1_EnableClockSleep
1411 * @param Periphs This parameter can be a combination of the following values:
1412 * @arg @ref LL_AXI_GRP1_PERIPH_SYSRAMEN
1413 * @retval None
1414 */
LL_AXI_GRP1_EnableClockSleep(uint32_t Periphs)1415 __STATIC_INLINE void LL_AXI_GRP1_EnableClockSleep(uint32_t Periphs)
1416 {
1417 __IO uint32_t tmpreg;
1418 WRITE_REG(RCC->MC_AXIMLPENSETR, Periphs);
1419 /* Delay after an RCC peripheral clock enabling */
1420 tmpreg = READ_BIT(RCC->MC_AXIMLPENSETR, Periphs);
1421 (void)tmpreg;
1422 }
1423
1424 /**
1425 * @brief Disable AXI peripheral clocks in Sleep modes
1426 * @rmtoll MC_AXIMLPENCLRR SYSRAMEN LL_AXI_GRP1_DisableClockSleep
1427 * @param Periphs This parameter can be a combination of the following values:
1428 * @arg @ref LL_AXI_GRP1_PERIPH_SYSRAMEN
1429 * @retval None
1430 */
LL_AXI_GRP1_DisableClockSleep(uint32_t Periphs)1431 __STATIC_INLINE void LL_AXI_GRP1_DisableClockSleep(uint32_t Periphs)
1432 {
1433 WRITE_REG(RCC->MC_AXIMLPENCLRR, Periphs);
1434 }
1435
1436 /**
1437 * @}
1438 */
1439
1440 /** @defgroup BUS_LL_EF_MLAHB MLAHB
1441 * @{
1442 */
1443
1444 /**
1445 * @brief Enable MLAHB peripherals clock.
1446 * @rmtoll MC_MLAHBENSETR RETRAMEN LL_MLAHB_GRP1_EnableClock
1447 * @param Periphs This parameter can be a combination of the following values:
1448 * @arg @ref LL_MLAHB_GRP1_PERIPH_RETRAMEN
1449 * @retval None
1450 */
LL_MLAHB_GRP1_EnableClock(uint32_t Periphs)1451 __STATIC_INLINE void LL_MLAHB_GRP1_EnableClock(uint32_t Periphs)
1452 {
1453 __IO uint32_t tmpreg;
1454 WRITE_REG(RCC->MC_MLAHBENSETR, Periphs);
1455 /* Delay after an RCC peripheral clock enabling */
1456 tmpreg = READ_BIT(RCC->MC_MLAHBENSETR, Periphs);
1457 (void)tmpreg;
1458 }
1459
1460 /**
1461 * @brief Check if MLAHB peripheral clock is enabled or not
1462 * @rmtoll MC_MLAHBENSETR RETRAMEN LL_MLAHB_GRP1_IsEnabledClock
1463 * @param Periphs This parameter can be a combination of the following values:
1464 * @arg @ref LL_MLAHB_GRP1_PERIPH_RETRAMEN
1465 * @retval State of Periphs (1 or 0).
1466 */
LL_MLAHB_GRP1_IsEnabledClock(uint32_t Periphs)1467 __STATIC_INLINE uint32_t LL_MLAHB_GRP1_IsEnabledClock(uint32_t Periphs)
1468 {
1469 return (READ_BIT(RCC->MC_MLAHBENSETR, Periphs) == Periphs);
1470 }
1471
1472 /**
1473 * @brief Disable MLAHB peripherals clock.
1474 * @rmtoll MC_MLAHBENCLRR RETRAMEN LL_MLAHB_GRP1_DisableClock
1475 * @param Periphs This parameter can be a combination of the following values:
1476 * @arg @ref LL_MLAHB_GRP1_PERIPH_RETRAMEN
1477 * @retval None
1478 */
LL_MLAHB_GRP1_DisableClock(uint32_t Periphs)1479 __STATIC_INLINE void LL_MLAHB_GRP1_DisableClock(uint32_t Periphs)
1480 {
1481 WRITE_REG(RCC->MC_MLAHBENCLRR, Periphs);
1482 }
1483
1484 /**
1485 * @brief Enable MLAHB peripheral clocks in Sleep mode
1486 * @rmtoll MC_MLAHBLPENSETR RETRAMEN LL_MLAHB_GRP1_EnableClockSleep
1487 * @param Periphs This parameter can be a combination of the following values:
1488 * @arg @ref LL_MLAHB_GRP1_PERIPH_RETRAMEN
1489 * @retval None
1490 */
LL_MLAHB_GRP1_EnableClockSleep(uint32_t Periphs)1491 __STATIC_INLINE void LL_MLAHB_GRP1_EnableClockSleep(uint32_t Periphs)
1492 {
1493 __IO uint32_t tmpreg;
1494 WRITE_REG(RCC->MC_MLAHBLPENSETR, Periphs);
1495 /* Delay after an RCC peripheral clock enabling */
1496 tmpreg = READ_BIT(RCC->MC_MLAHBLPENSETR, Periphs);
1497 (void)tmpreg;
1498 }
1499
1500 /**
1501 * @brief Disable MLAHB peripheral clocks in Sleep modes
1502 * @rmtoll MC_MLAHBLPENCLRR RETRAMEN LL_MLAHB_GRP1_DisableClockSleep
1503 * @param Periphs This parameter can be a combination of the following values:
1504 * @arg @ref LL_MLAHB_GRP1_PERIPH_RETRAMEN
1505 * @retval None
1506 */
LL_MLAHB_GRP1_DisableClockSleep(uint32_t Periphs)1507 __STATIC_INLINE void LL_MLAHB_GRP1_DisableClockSleep(uint32_t Periphs)
1508 {
1509 WRITE_REG(RCC->MC_MLAHBLPENCLRR, Periphs);
1510 }
1511
1512 /**
1513 * @}
1514 */
1515
1516 /** @defgroup BUS_LL_EF_APB1 APB1
1517 * @{
1518 */
1519
1520 /**
1521 * @brief Enable APB1 peripherals clock.
1522 * @rmtoll MC_APB1ENSETR TIM2 LL_APB1_GRP1_EnableClock\n
1523 * MC_APB1ENSETR TIM3 LL_APB1_GRP1_EnableClock\n
1524 * MC_APB1ENSETR TIM4 LL_APB1_GRP1_EnableClock\n
1525 * MC_APB1ENSETR TIM5 LL_APB1_GRP1_EnableClock\n
1526 * MC_APB1ENSETR TIM6 LL_APB1_GRP1_EnableClock\n
1527 * MC_APB1ENSETR TIM7 LL_APB1_GRP1_EnableClock\n
1528 * MC_APB1ENSETR TIM12 LL_APB1_GRP1_EnableClock\n
1529 * MC_APB1ENSETR TIM13 LL_APB1_GRP1_EnableClock\n
1530 * MC_APB1ENSETR TIM14 LL_APB1_GRP1_EnableClock\n
1531 * MC_APB1ENSETR LPTIM1 LL_APB1_GRP1_EnableClock\n
1532 * MC_APB1ENSETR SPI2 LL_APB1_GRP1_EnableClock\n
1533 * MC_APB1ENSETR SPI3 LL_APB1_GRP1_EnableClock\n
1534 * MC_APB1ENSETR USART2 LL_APB1_GRP1_EnableClock\n
1535 * MC_APB1ENSETR USART3 LL_APB1_GRP1_EnableClock\n
1536 * MC_APB1ENSETR UART4 LL_APB1_GRP1_EnableClock\n
1537 * MC_APB1ENSETR UART5 LL_APB1_GRP1_EnableClock\n
1538 * MC_APB1ENSETR UART7 LL_APB1_GRP1_EnableClock\n
1539 * MC_APB1ENSETR UART8 LL_APB1_GRP1_EnableClock\n
1540 * MC_APB1ENSETR I2C1 LL_APB1_GRP1_EnableClock\n
1541 * MC_APB1ENSETR I2C2 LL_APB1_GRP1_EnableClock\n
1542 * MC_APB1ENSETR I2C3 LL_APB1_GRP1_EnableClock\n
1543 * MC_APB1ENSETR I2C5 LL_APB1_GRP1_EnableClock\n
1544 * MC_APB1ENSETR SPDIF LL_APB1_GRP1_EnableClock\n
1545 * MC_APB1ENSETR CEC LL_APB1_GRP1_EnableClock\n
1546 * MC_APB1ENSETR WWDG1 LL_APB1_GRP1_EnableClock\n
1547 * MC_APB1ENSETR DAC12 LL_APB1_GRP1_EnableClock\n
1548 * MC_APB1ENSETR MDIOS LL_APB1_GRP1_EnableClock
1549 * @param Periphs This parameter can be a combination of the following values:
1550 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1551 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1552 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1553 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1554 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1555 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1556 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1557 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1558 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1559 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1560 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1561 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1562 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1563 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1564 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1565 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1566 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1567 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1568 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1569 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1570 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1571 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5
1572 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIF
1573 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1574 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG1
1575 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1576 * @arg @ref LL_APB1_GRP1_PERIPH_MDIOS
1577 * @retval None
1578 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1579 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1580 {
1581 __IO uint32_t tmpreg;
1582 WRITE_REG(RCC->MC_APB1ENSETR, Periphs);
1583 /* Delay after an RCC peripheral clock enabling */
1584 tmpreg = READ_BIT(RCC->MC_APB1ENSETR, Periphs);
1585 (void)tmpreg;
1586 }
1587
1588 /**
1589 * @brief Check if APB1 peripheral clock is enabled or not
1590 * @rmtoll MC_APB1ENSETR TIM2 LL_APB1_GRP1_IsEnabledClock\n
1591 * MC_APB1ENSETR TIM3 LL_APB1_GRP1_IsEnabledClock\n
1592 * MC_APB1ENSETR TIM4 LL_APB1_GRP1_IsEnabledClock\n
1593 * MC_APB1ENSETR TIM5 LL_APB1_GRP1_IsEnabledClock\n
1594 * MC_APB1ENSETR TIM6 LL_APB1_GRP1_IsEnabledClock\n
1595 * MC_APB1ENSETR TIM7 LL_APB1_GRP1_IsEnabledClock\n
1596 * MC_APB1ENSETR TIM12 LL_APB1_GRP1_IsEnabledClock\n
1597 * MC_APB1ENSETR TIM13 LL_APB1_GRP1_IsEnabledClock\n
1598 * MC_APB1ENSETR TIM14 LL_APB1_GRP1_IsEnabledClock\n
1599 * MC_APB1ENSETR LPTIM1 LL_APB1_GRP1_IsEnabledClock\n
1600 * MC_APB1ENSETR SPI2 LL_APB1_GRP1_IsEnabledClock\n
1601 * MC_APB1ENSETR SPI3 LL_APB1_GRP1_IsEnabledClock\n
1602 * MC_APB1ENSETR USART2 LL_APB1_GRP1_IsEnabledClock\n
1603 * MC_APB1ENSETR USART3 LL_APB1_GRP1_IsEnabledClock\n
1604 * MC_APB1ENSETR UART4 LL_APB1_GRP1_IsEnabledClock\n
1605 * MC_APB1ENSETR UART5 LL_APB1_GRP1_IsEnabledClock\n
1606 * MC_APB1ENSETR UART7 LL_APB1_GRP1_IsEnabledClock\n
1607 * MC_APB1ENSETR UART8 LL_APB1_GRP1_IsEnabledClock\n
1608 * MC_APB1ENSETR I2C1 LL_APB1_GRP1_IsEnabledClock\n
1609 * MC_APB1ENSETR I2C2 LL_APB1_GRP1_IsEnabledClock\n
1610 * MC_APB1ENSETR I2C3 LL_APB1_GRP1_IsEnabledClock\n
1611 * MC_APB1ENSETR I2C5 LL_APB1_GRP1_IsEnabledClock\n
1612 * MC_APB1ENSETR SPDIF LL_APB1_GRP1_IsEnabledClock\n
1613 * MC_APB1ENSETR CEC LL_APB1_GRP1_IsEnabledClock\n
1614 * MC_APB1ENSETR WWDG1 LL_APB1_GRP1_IsEnabledClock\n
1615 * MC_APB1ENSETR DAC12 LL_APB1_GRP1_IsEnabledClock\n
1616 * MC_APB1ENSETR MDIOS LL_APB1_GRP1_IsEnabledClock
1617 * @param Periphs This parameter can be a combination of the following values:
1618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1622 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1623 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1624 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1625 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1626 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1627 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1628 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1629 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1630 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1631 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1632 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1633 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1634 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1635 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1636 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1637 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1638 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1639 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5
1640 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIF
1641 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1642 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG1
1643 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1644 * @arg @ref LL_APB1_GRP1_PERIPH_MDIOS
1645 * @retval State of Periphs (1 or 0).
1646 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1647 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1648 {
1649 return (READ_BIT(RCC->MC_APB1ENSETR, Periphs) == Periphs);
1650 }
1651
1652 /**
1653 * @brief Disable APB1 peripherals clock.
1654 * @rmtoll MC_APB1ENCLRR TIM2 LL_APB1_GRP1_DisableClock\n
1655 * MC_APB1ENCLRR TIM3 LL_APB1_GRP1_DisableClock\n
1656 * MC_APB1ENCLRR TIM4 LL_APB1_GRP1_DisableClock\n
1657 * MC_APB1ENCLRR TIM5 LL_APB1_GRP1_DisableClock\n
1658 * MC_APB1ENCLRR TIM6 LL_APB1_GRP1_DisableClock\n
1659 * MC_APB1ENCLRR TIM7 LL_APB1_GRP1_DisableClock\n
1660 * MC_APB1ENCLRR TIM12 LL_APB1_GRP1_DisableClock\n
1661 * MC_APB1ENCLRR TIM13 LL_APB1_GRP1_DisableClock\n
1662 * MC_APB1ENCLRR TIM14 LL_APB1_GRP1_DisableClock\n
1663 * MC_APB1ENCLRR LPTIM1 LL_APB1_GRP1_DisableClock\n
1664 * MC_APB1ENCLRR SPI2 LL_APB1_GRP1_DisableClock\n
1665 * MC_APB1ENCLRR SPI3 LL_APB1_GRP1_DisableClock\n
1666 * MC_APB1ENCLRR USART2 LL_APB1_GRP1_DisableClock\n
1667 * MC_APB1ENCLRR USART3 LL_APB1_GRP1_DisableClock\n
1668 * MC_APB1ENCLRR UART4 LL_APB1_GRP1_DisableClock\n
1669 * MC_APB1ENCLRR UART5 LL_APB1_GRP1_DisableClock\n
1670 * MC_APB1ENCLRR UART7 LL_APB1_GRP1_DisableClock\n
1671 * MC_APB1ENCLRR UART8 LL_APB1_GRP1_DisableClock\n
1672 * MC_APB1ENCLRR I2C1 LL_APB1_GRP1_DisableClock\n
1673 * MC_APB1ENCLRR I2C2 LL_APB1_GRP1_DisableClock\n
1674 * MC_APB1ENCLRR I2C3 LL_APB1_GRP1_DisableClock\n
1675 * MC_APB1ENCLRR I2C5 LL_APB1_GRP1_DisableClock\n
1676 * MC_APB1ENCLRR SPDIF LL_APB1_GRP1_DisableClock\n
1677 * MC_APB1ENCLRR CEC LL_APB1_GRP1_DisableClock\n
1678 * MC_APB1ENCLRR DAC12 LL_APB1_GRP1_DisableClock\n
1679 * MC_APB1ENCLRR MDIOS LL_APB1_GRP1_DisableClock
1680 * @param Periphs This parameter can be a combination of the following values:
1681 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1682 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1683 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1684 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1685 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1686 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1687 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1688 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1689 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1690 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1691 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1692 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1693 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1694 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1695 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1696 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1697 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1698 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1699 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1700 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1701 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1702 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5
1703 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIF
1704 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1705 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1706 * @arg @ref LL_APB1_GRP1_PERIPH_MDIOS
1707 * @retval None
1708 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1709 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1710 {
1711 WRITE_REG(RCC->MC_APB1ENCLRR, Periphs);
1712 }
1713
1714 /**
1715 * @brief Force APB1 peripherals reset.
1716 * @rmtoll APB1RSTSETR TIM2 LL_APB1_GRP1_ForceReset\n
1717 * APB1RSTSETR TIM3 LL_APB1_GRP1_ForceReset\n
1718 * APB1RSTSETR TIM4 LL_APB1_GRP1_ForceReset\n
1719 * APB1RSTSETR TIM5 LL_APB1_GRP1_ForceReset\n
1720 * APB1RSTSETR TIM6 LL_APB1_GRP1_ForceReset\n
1721 * APB1RSTSETR TIM7 LL_APB1_GRP1_ForceReset\n
1722 * APB1RSTSETR TIM12 LL_APB1_GRP1_ForceReset\n
1723 * APB1RSTSETR TIM13 LL_APB1_GRP1_ForceReset\n
1724 * APB1RSTSETR TIM14 LL_APB1_GRP1_ForceReset\n
1725 * APB1RSTSETR LPTIM1 LL_APB1_GRP1_ForceReset\n
1726 * APB1RSTSETR SPI2 LL_APB1_GRP1_ForceReset\n
1727 * APB1RSTSETR SPI3 LL_APB1_GRP1_ForceReset\n
1728 * APB1RSTSETR USART2 LL_APB1_GRP1_ForceReset\n
1729 * APB1RSTSETR USART3 LL_APB1_GRP1_ForceReset\n
1730 * APB1RSTSETR UART4 LL_APB1_GRP1_ForceReset\n
1731 * APB1RSTSETR UART5 LL_APB1_GRP1_ForceReset\n
1732 * APB1RSTSETR UART7 LL_APB1_GRP1_ForceReset\n
1733 * APB1RSTSETR UART8 LL_APB1_GRP1_ForceReset\n
1734 * APB1RSTSETR I2C1 LL_APB1_GRP1_ForceReset\n
1735 * APB1RSTSETR I2C2 LL_APB1_GRP1_ForceReset\n
1736 * APB1RSTSETR I2C3 LL_APB1_GRP1_ForceReset\n
1737 * APB1RSTSETR I2C5 LL_APB1_GRP1_ForceReset\n
1738 * APB1RSTSETR SPDIF LL_APB1_GRP1_ForceReset\n
1739 * APB1RSTSETR CEC LL_APB1_GRP1_ForceReset\n
1740 * APB1RSTSETR DAC12 LL_APB1_GRP1_ForceReset\n
1741 * APB1RSTSETR MCDIOS LL_APB1_GRP1_ForceReset
1742 * @param Periphs This parameter can be a combination of the following values:
1743 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1744 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1745 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1746 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1747 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1748 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1749 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1750 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1751 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1752 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1753 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1754 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1755 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1756 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1757 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1758 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1759 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1760 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1761 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1762 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1763 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1764 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5
1765 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIF
1766 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1767 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1768 * @arg @ref LL_APB1_GRP1_PERIPH_MDIOS
1769 * @retval None
1770 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1771 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1772 {
1773 WRITE_REG(RCC->APB1RSTSETR, Periphs);
1774 }
1775
1776 /**
1777 * @brief Release APB1 peripherals reset.
1778 * @rmtoll APB1RSTCLRR TIM2 LL_APB1_GRP1_ReleaseReset\n
1779 * APB1RSTCLRR TIM3 LL_APB1_GRP1_ReleaseReset\n
1780 * APB1RSTCLRR TIM4 LL_APB1_GRP1_ReleaseReset\n
1781 * APB1RSTCLRR TIM5 LL_APB1_GRP1_ReleaseReset\n
1782 * APB1RSTCLRR TIM6 LL_APB1_GRP1_ReleaseReset\n
1783 * APB1RSTCLRR TIM7 LL_APB1_GRP1_ReleaseReset\n
1784 * APB1RSTCLRR TIM12 LL_APB1_GRP1_ReleaseReset\n
1785 * APB1RSTCLRR TIM13 LL_APB1_GRP1_ReleaseReset\n
1786 * APB1RSTCLRR TIM14 LL_APB1_GRP1_ReleaseReset\n
1787 * APB1RSTCLRR LPTIM1 LL_APB1_GRP1_ReleaseReset\n
1788 * APB1RSTCLRR SPI2 LL_APB1_GRP1_ReleaseReset\n
1789 * APB1RSTCLRR SPI3 LL_APB1_GRP1_ReleaseReset\n
1790 * APB1RSTCLRR USART2 LL_APB1_GRP1_ReleaseReset\n
1791 * APB1RSTCLRR USART3 LL_APB1_GRP1_ReleaseReset\n
1792 * APB1RSTCLRR UART4 LL_APB1_GRP1_ReleaseReset\n
1793 * APB1RSTCLRR UART5 LL_APB1_GRP1_ReleaseReset\n
1794 * APB1RSTCLRR UART7 LL_APB1_GRP1_ReleaseReset\n
1795 * APB1RSTCLRR UART8 LL_APB1_GRP1_ReleaseReset\n
1796 * APB1RSTCLRR I2C1 LL_APB1_GRP1_ReleaseReset\n
1797 * APB1RSTCLRR I2C2 LL_APB1_GRP1_ReleaseReset\n
1798 * APB1RSTCLRR I2C3 LL_APB1_GRP1_ReleaseReset\n
1799 * APB1RSTCLRR I2C5 LL_APB1_GRP1_ReleaseReset\n
1800 * APB1RSTCLRR SPDIF LL_APB1_GRP1_ReleaseReset\n
1801 * APB1RSTCLRR CEC LL_APB1_GRP1_ReleaseReset\n
1802 * APB1RSTCLRR DAC12 LL_APB1_GRP1_ReleaseReset\n
1803 * APB1RSTCLRR MDIOS LL_APB1_GRP1_ReleaseReset
1804 * @param Periphs This parameter can be a combination of the following values:
1805 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1806 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1807 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1808 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1809 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1810 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1811 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1812 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1813 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1814 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1815 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1816 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1817 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1818 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1819 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1820 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1821 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1822 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1823 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1824 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1825 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1826 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5
1827 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIF
1828 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1829 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1830 * @arg @ref LL_APB1_GRP1_PERIPH_MDIOS
1831 * @retval None
1832 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1833 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1834 {
1835 WRITE_REG(RCC->APB1RSTCLRR, Periphs);
1836 }
1837
1838 /**
1839 * @brief Enable APB1 peripheral clocks in Sleep mode
1840 * @rmtoll MC_APB1LPENSETR TIM2 LL_APB1_GRP1_EnableClockSleep\n
1841 * MC_APB1LPENSETR TIM3 LL_APB1_GRP1_EnableClockSleep\n
1842 * MC_APB1LPENSETR TIM4 LL_APB1_GRP1_EnableClockSleep\n
1843 * MC_APB1LPENSETR TIM5 LL_APB1_GRP1_EnableClockSleep\n
1844 * MC_APB1LPENSETR TIM6 LL_APB1_GRP1_EnableClockSleep\n
1845 * MC_APB1LPENSETR TIM7 LL_APB1_GRP1_EnableClockSleep\n
1846 * MC_APB1LPENSETR TIM12 LL_APB1_GRP1_EnableClockSleep\n
1847 * MC_APB1LPENSETR TIM13 LL_APB1_GRP1_EnableClockSleep\n
1848 * MC_APB1LPENSETR TIM14 LL_APB1_GRP1_EnableClockSleep\n
1849 * MC_APB1LPENSETR LPTIM1 LL_APB1_GRP1_EnableClockSleep\n
1850 * MC_APB1LPENSETR SPI2 LL_APB1_GRP1_EnableClockSleep\n
1851 * MC_APB1LPENSETR SPI3 LL_APB1_GRP1_EnableClockSleep\n
1852 * MC_APB1LPENSETR USART2 LL_APB1_GRP1_EnableClockSleep\n
1853 * MC_APB1LPENSETR USART3 LL_APB1_GRP1_EnableClockSleep\n
1854 * MC_APB1LPENSETR UART4 LL_APB1_GRP1_EnableClockSleep\n
1855 * MC_APB1LPENSETR UART5 LL_APB1_GRP1_EnableClockSleep\n
1856 * MC_APB1LPENSETR UART7 LL_APB1_GRP1_EnableClockSleep\n
1857 * MC_APB1LPENSETR UART8 LL_APB1_GRP1_EnableClockSleep\n
1858 * MC_APB1LPENSETR I2C1 LL_APB1_GRP1_EnableClockSleep\n
1859 * MC_APB1LPENSETR I2C2 LL_APB1_GRP1_EnableClockSleep\n
1860 * MC_APB1LPENSETR I2C3 LL_APB1_GRP1_EnableClockSleep\n
1861 * MC_APB1LPENSETR I2C5 LL_APB1_GRP1_EnableClockSleep\n
1862 * MC_APB1LPENSETR SPDIF LL_APB1_GRP1_EnableClockSleep\n
1863 * MC_APB1LPENSETR CEC LL_APB1_GRP1_EnableClockSleep\n
1864 * MC_APB1LPENSETR WWDG1 LL_APB1_GRP1_EnableClockSleep\n
1865 * MC_APB1LPENSETR DAC12 LL_APB1_GRP1_EnableClockSleep\n
1866 * MC_APB1LPENSETR MDIOS LL_APB1_GRP1_EnableClockSleep
1867 * @param Periphs This parameter can be a combination of the following values:
1868 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1869 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1870 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1871 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1872 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1873 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1874 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1875 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1876 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1877 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1878 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1879 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1880 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1881 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1882 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1883 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1884 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1885 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1886 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1887 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1888 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1889 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5
1890 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIF
1891 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1892 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG1
1893 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1894 * @arg @ref LL_APB1_GRP1_PERIPH_MDIOS
1895 * @retval None
1896 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)1897 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
1898 {
1899 __IO uint32_t tmpreg;
1900 WRITE_REG(RCC->MC_APB1LPENSETR, Periphs);
1901 /* Delay after an RCC peripheral clock enabling */
1902 tmpreg = READ_BIT(RCC->MC_APB1LPENSETR, Periphs);
1903 (void)tmpreg;
1904 }
1905
1906 /**
1907 * @brief Disable APB1 peripheral clocks in Sleep modes
1908 * @rmtoll MC_APB1LPENCLRR TIM2 LL_APB1_GRP1_DisableClockSleep\n
1909 * MC_APB1LPENCLRR TIM3 LL_APB1_GRP1_DisableClockSleep\n
1910 * MC_APB1LPENCLRR TIM4 LL_APB1_GRP1_DisableClockSleep\n
1911 * MC_APB1LPENCLRR TIM5 LL_APB1_GRP1_DisableClockSleep\n
1912 * MC_APB1LPENCLRR TIM6 LL_APB1_GRP1_DisableClockSleep\n
1913 * MC_APB1LPENCLRR TIM7 LL_APB1_GRP1_DisableClockSleep\n
1914 * MC_APB1LPENCLRR TIM12 LL_APB1_GRP1_DisableClockSleep\n
1915 * MC_APB1LPENCLRR TIM13 LL_APB1_GRP1_DisableClockSleep\n
1916 * MC_APB1LPENCLRR TIM14 LL_APB1_GRP1_DisableClockSleep\n
1917 * MC_APB1LPENCLRR LPTIM1 LL_APB1_GRP1_DisableClockSleep\n
1918 * MC_APB1LPENCLRR SPI2 LL_APB1_GRP1_DisableClockSleep\n
1919 * MC_APB1LPENCLRR SPI3 LL_APB1_GRP1_DisableClockSleep\n
1920 * MC_APB1LPENCLRR USART2 LL_APB1_GRP1_DisableClockSleep\n
1921 * MC_APB1LPENCLRR USART3 LL_APB1_GRP1_DisableClockSleep\n
1922 * MC_APB1LPENCLRR UART4 LL_APB1_GRP1_DisableClockSleep\n
1923 * MC_APB1LPENCLRR UART5 LL_APB1_GRP1_DisableClockSleep\n
1924 * MC_APB1LPENCLRR UART7 LL_APB1_GRP1_DisableClockSleep\n
1925 * MC_APB1LPENCLRR UART8 LL_APB1_GRP1_DisableClockSleep\n
1926 * MC_APB1LPENCLRR I2C1 LL_APB1_GRP1_DisableClockSleep\n
1927 * MC_APB1LPENCLRR I2C2 LL_APB1_GRP1_DisableClockSleep\n
1928 * MC_APB1LPENCLRR I2C3 LL_APB1_GRP1_DisableClockSleep\n
1929 * MC_APB1LPENCLRR I2C5 LL_APB1_GRP1_DisableClockSleep\n
1930 * MC_APB1LPENCLRR SPDIF LL_APB1_GRP1_DisableClockSleep\n
1931 * MC_APB1LPENCLRR CEC LL_APB1_GRP1_DisableClockSleep\n
1932 * MC_APB1LPENCLRR WWDG1 LL_APB1_GRP1_DisableClockSleep\n
1933 * MC_APB1LPENCLRR DAC12 LL_APB1_GRP1_DisableClockSleep\n
1934 * MC_APB1LPENCLRR MDIOS LL_APB1_GRP1_DisableClockSleep
1935 * @param Periphs This parameter can be a combination of the following values:
1936 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1937 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1938 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1939 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1940 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1941 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1942 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1943 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1944 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1945 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1946 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1947 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1948 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1949 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1950 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1951 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1952 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1953 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1954 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1955 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1956 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1957 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5
1958 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIF
1959 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1960 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG1
1961 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1962 * @arg @ref LL_APB1_GRP1_PERIPH_MDIOS
1963 * @retval None
1964 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)1965 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
1966 {
1967 WRITE_REG(RCC->MC_APB1LPENCLRR, Periphs);
1968 }
1969
1970 /**
1971 * @}
1972 */
1973
1974 /** @defgroup BUS_LL_EF_APB2 APB2
1975 * @{
1976 */
1977
1978 /**
1979 * @brief Enable APB2 peripherals clock.
1980 * @rmtoll MC_APB2ENSETR TIM1 LL_APB2_GRP1_EnableClock\n
1981 * MC_APB2ENSETR TIM8 LL_APB2_GRP1_EnableClock\n
1982 * MC_APB2ENSETR TIM15 LL_APB2_GRP1_EnableClock\n
1983 * MC_APB2ENSETR TIM16 LL_APB2_GRP1_EnableClock\n
1984 * MC_APB2ENSETR TIM17 LL_APB2_GRP1_EnableClock\n
1985 * MC_APB2ENSETR SPI1 LL_APB2_GRP1_EnableClock\n
1986 * MC_APB2ENSETR SPI4 LL_APB2_GRP1_EnableClock\n
1987 * MC_APB2ENSETR SPI5 LL_APB2_GRP1_EnableClock\n
1988 * MC_APB2ENSETR USART6 LL_APB2_GRP1_EnableClock\n
1989 * MC_APB2ENSETR SAI1 LL_APB2_GRP1_EnableClock\n
1990 * MC_APB2ENSETR SAI2 LL_APB2_GRP1_EnableClock\n
1991 * MC_APB2ENSETR SAI3 LL_APB2_GRP1_EnableClock\n
1992 * MC_APB2ENSETR DFSDM1 LL_APB2_GRP1_EnableClock\n
1993 * MC_APB2ENSETR ADFSDM1 LL_APB2_GRP1_EnableClock\n
1994 * MC_APB2ENSETR FDCAN LL_APB2_GRP1_EnableClock
1995 * @param Periphs This parameter can be a combination of the following values:
1996 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1997 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1998 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1999 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2000 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2001 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2002 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2003 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2004 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2005 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2006 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2007 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
2008 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2009 * @arg @ref LL_APB2_GRP1_PERIPH_ADFSDM1
2010 * @arg @ref LL_APB2_GRP1_PERIPH_FDCAN
2011 * @retval None
2012 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)2013 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
2014 {
2015 __IO uint32_t tmpreg;
2016 WRITE_REG(RCC->MC_APB2ENSETR, Periphs);
2017 /* Delay after an RCC peripheral clock enabling */
2018 tmpreg = READ_BIT(RCC->MC_APB2ENSETR, Periphs);
2019 (void)tmpreg;
2020 }
2021
2022 /**
2023 * @brief Check if APB2 peripheral clock is enabled or not
2024 * @rmtoll MC_APB2ENSETR TIM1 LL_APB2_GRP1_IsEnabledClock\n
2025 * MC_APB2ENSETR TIM8 LL_APB2_GRP1_IsEnabledClock\n
2026 * MC_APB2ENSETR TIM15 LL_APB2_GRP1_IsEnabledClock\n
2027 * MC_APB2ENSETR TIM16 LL_APB2_GRP1_IsEnabledClock\n
2028 * MC_APB2ENSETR TIM17 LL_APB2_GRP1_IsEnabledClock\n
2029 * MC_APB2ENSETR SPI1 LL_APB2_GRP1_IsEnabledClock\n
2030 * MC_APB2ENSETR SPI4 LL_APB2_GRP1_IsEnabledClock\n
2031 * MC_APB2ENSETR SPI5 LL_APB2_GRP1_IsEnabledClock\n
2032 * MC_APB2ENSETR USART6 LL_APB2_GRP1_IsEnabledClock\n
2033 * MC_APB2ENSETR SAI1 LL_APB2_GRP1_IsEnabledClock\n
2034 * MC_APB2ENSETR SAI2 LL_APB2_GRP1_IsEnabledClock\n
2035 * MC_APB2ENSETR SAI3 LL_APB2_GRP1_IsEnabledClock\n
2036 * MC_APB2ENSETR DFSDM1 LL_APB2_GRP1_IsEnabledClock\n
2037 * MC_APB2ENSETR ADFSDM1 LL_APB2_GRP1_IsEnabledClock\n
2038 * MC_APB2ENSETR FDCAN LL_APB2_GRP1_IsEnabledClock
2039 * @param Periphs This parameter can be a combination of the following values:
2040 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2041 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2042 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2043 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2044 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2045 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2046 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2047 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2048 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2049 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2050 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2051 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
2052 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2053 * @arg @ref LL_APB2_GRP1_PERIPH_ADFSDM1
2054 * @arg @ref LL_APB2_GRP1_PERIPH_FDCAN
2055 * @retval State of Periphs (1 or 0).
2056 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2057 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2058 {
2059 return (READ_BIT(RCC->MC_APB2ENSETR, Periphs) == Periphs);
2060 }
2061
2062 /**
2063 * @brief Disable APB2 peripherals clock.
2064 * @rmtoll MC_APB2ENCLRR TIM1 LL_APB2_GRP1_DisableClock\n
2065 * MC_APB2ENCLRR TIM8 LL_APB2_GRP1_DisableClock\n
2066 * MC_APB2ENCLRR TIM15 LL_APB2_GRP1_DisableClock\n
2067 * MC_APB2ENCLRR TIM16 LL_APB2_GRP1_DisableClock\n
2068 * MC_APB2ENCLRR TIM17 LL_APB2_GRP1_DisableClock\n
2069 * MC_APB2ENCLRR SPI1 LL_APB2_GRP1_DisableClock\n
2070 * MC_APB2ENCLRR SPI4 LL_APB2_GRP1_DisableClock\n
2071 * MC_APB2ENCLRR SPI5 LL_APB2_GRP1_DisableClock\n
2072 * MC_APB2ENCLRR USART6 LL_APB2_GRP1_DisableClock\n
2073 * MC_APB2ENCLRR SAI1 LL_APB2_GRP1_DisableClock\n
2074 * MC_APB2ENCLRR SAI2 LL_APB2_GRP1_DisableClock\n
2075 * MC_APB2ENCLRR SAI3 LL_APB2_GRP1_DisableClock\n
2076 * MC_APB2ENCLRR DFSDM1 LL_APB2_GRP1_DisableClock\n
2077 * MC_APB2ENCLRR ADFSDM1 LL_APB2_GRP1_DisableClock\n
2078 * MC_APB2ENCLRR FDCAN LL_APB2_GRP1_DisableClock
2079 * @param Periphs This parameter can be a combination of the following values:
2080 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2081 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2082 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2083 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2084 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2085 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2086 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2087 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2088 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2089 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2090 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2091 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
2092 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2093 * @arg @ref LL_APB2_GRP1_PERIPH_ADFSDM1
2094 * @arg @ref LL_APB2_GRP1_PERIPH_FDCAN
2095 * @retval None
2096 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)2097 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2098 {
2099 WRITE_REG(RCC->MC_APB2ENCLRR, Periphs);
2100 }
2101
2102 /**
2103 * @brief Force APB2 peripherals reset.
2104 * @rmtoll APB2RSTSETR TIM1 LL_APB2_GRP1_ForceReset\n
2105 * APB2RSTSETR TIM8 LL_APB2_GRP1_ForceReset\n
2106 * APB2RSTSETR TIM15 LL_APB2_GRP1_ForceReset\n
2107 * APB2RSTSETR TIM16 LL_APB2_GRP1_ForceReset\n
2108 * APB2RSTSETR TIM17 LL_APB2_GRP1_ForceReset\n
2109 * APB2RSTSETR SPI1 LL_APB2_GRP1_ForceReset\n
2110 * APB2RSTSETR SPI4 LL_APB2_GRP1_ForceReset\n
2111 * APB2RSTSETR SPI5 LL_APB2_GRP1_ForceReset\n
2112 * APB2RSTSETR USART6 LL_APB2_GRP1_ForceReset\n
2113 * APB2RSTSETR SAI1 LL_APB2_GRP1_ForceReset\n
2114 * APB2RSTSETR SAI2 LL_APB2_GRP1_ForceReset\n
2115 * APB2RSTSETR SAI3 LL_APB2_GRP1_ForceReset\n
2116 * APB2RSTSETR DFSDM1 LL_APB2_GRP1_ForceReset\n
2117 * APB2RSTSETR FDCAN LL_APB2_GRP1_ForceReset
2118 * @param Periphs This parameter can be a combination of the following values:
2119 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2120 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2121 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2122 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2123 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2124 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2125 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2126 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2127 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2128 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2129 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2130 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2131 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
2132 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2133 * @arg @ref LL_APB2_GRP1_PERIPH_FDCAN
2134 * @retval None
2135 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)2136 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
2137 {
2138 WRITE_REG(RCC->APB2RSTSETR, Periphs);
2139 }
2140
2141 /**
2142 * @brief Release APB2 peripherals reset.
2143 * @rmtoll APB2RSTCLRR TIM1 LL_APB2_GRP1_ReleaseReset\n
2144 * APB2RSTCLRR TIM8 LL_APB2_GRP1_ReleaseReset\n
2145 * APB2RSTCLRR TIM15 LL_APB2_GRP1_ReleaseReset\n
2146 * APB2RSTCLRR TIM16 LL_APB2_GRP1_ReleaseReset\n
2147 * APB2RSTCLRR TIM17 LL_APB2_GRP1_ReleaseReset\n
2148 * APB2RSTCLRR SPI1 LL_APB2_GRP1_ReleaseReset\n
2149 * APB2RSTCLRR SPI4 LL_APB2_GRP1_ReleaseReset\n
2150 * APB2RSTCLRR SPI5 LL_APB2_GRP1_ReleaseReset\n
2151 * APB2RSTCLRR USART6 LL_APB2_GRP1_ReleaseReset\n
2152 * APB2RSTCLRR SAI1 LL_APB2_GRP1_ReleaseReset\n
2153 * APB2RSTCLRR SAI2 LL_APB2_GRP1_ReleaseReset\n
2154 * APB2RSTCLRR SAI3 LL_APB2_GRP1_ReleaseReset\n
2155 * APB2RSTCLRR DFSDM1 LL_APB2_GRP1_ReleaseReset\n
2156 * APB2RSTCLRR FDCAN LL_APB2_GRP1_ReleaseReset
2157 * @param Periphs This parameter can be a combination of the following values:
2158 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2159 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2160 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2161 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2162 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2163 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2164 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2165 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2166 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2167 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2168 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2169 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2170 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
2171 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2172 * @arg @ref LL_APB2_GRP1_PERIPH_FDCAN
2173 * @retval None
2174 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)2175 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
2176 {
2177 WRITE_REG(RCC->APB2RSTCLRR, Periphs);
2178 }
2179
2180 /**
2181 * @brief Enable APB2 peripheral clocks in Sleep mode
2182 * @rmtoll MC_APB2LPENSETR TIM1 LL_APB2_GRP1_EnableClockSleep\n
2183 * MC_APB2LPENSETR TIM8 LL_APB2_GRP1_EnableClockSleep\n
2184 * MC_APB2LPENSETR TIM15 LL_APB2_GRP1_EnableClockSleep\n
2185 * MC_APB2LPENSETR TIM16 LL_APB2_GRP1_EnableClockSleep\n
2186 * MC_APB2LPENSETR TIM17 LL_APB2_GRP1_EnableClockSleep\n
2187 * MC_APB2LPENSETR SPI1 LL_APB2_GRP1_EnableClockSleep\n
2188 * MC_APB2LPENSETR SPI4 LL_APB2_GRP1_EnableClockSleep\n
2189 * MC_APB2LPENSETR SPI5 LL_APB2_GRP1_EnableClockSleep\n
2190 * MC_APB2LPENSETR USART6 LL_APB2_GRP1_EnableClockSleep\n
2191 * MC_APB2LPENSETR SAI1 LL_APB2_GRP1_EnableClockSleep\n
2192 * MC_APB2LPENSETR SAI2 LL_APB2_GRP1_EnableClockSleep\n
2193 * MC_APB2LPENSETR SAI3 LL_APB2_GRP1_EnableClockSleep\n
2194 * MC_APB2LPENSETR DFSDM1 LL_APB2_GRP1_EnableClockSleep\n
2195 * MC_APB2LPENSETR ADFSDM1 LL_APB2_GRP1_EnableClockSleep\n
2196 * MC_APB2LPENSETR FDCAN LL_APB2_GRP1_EnableClockSleep
2197 * @param Periphs This parameter can be a combination of the following values:
2198 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2199 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2200 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2201 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2202 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2203 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2204 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2205 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2206 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2207 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2208 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2209 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
2210 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2211 * @arg @ref LL_APB2_GRP1_PERIPH_ADFSDM1
2212 * @arg @ref LL_APB2_GRP1_PERIPH_FDCAN
2213 * @retval None
2214 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)2215 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2216 {
2217 __IO uint32_t tmpreg;
2218 WRITE_REG(RCC->MC_APB2LPENSETR, Periphs);
2219 /* Delay after an RCC peripheral clock enabling */
2220 tmpreg = READ_BIT(RCC->MC_APB2LPENSETR, Periphs);
2221 (void)tmpreg;
2222 }
2223
2224 /**
2225 * @brief Disable APB2 peripheral clocks in Sleep modes
2226 * @rmtoll MC_APB2LPENCLRR TIM1 LL_APB2_GRP1_DisableClockSleep\n
2227 * MC_APB2LPENCLRR TIM8 LL_APB2_GRP1_DisableClockSleep\n
2228 * MC_APB2LPENCLRR TIM15 LL_APB2_GRP1_DisableClockSleep\n
2229 * MC_APB2LPENCLRR TIM16 LL_APB2_GRP1_DisableClockSleep\n
2230 * MC_APB2LPENCLRR TIM17 LL_APB2_GRP1_DisableClockSleep\n
2231 * MC_APB2LPENCLRR SPI1 LL_APB2_GRP1_DisableClockSleep\n
2232 * MC_APB2LPENCLRR SPI4 LL_APB2_GRP1_DisableClockSleep\n
2233 * MC_APB2LPENCLRR SPI5 LL_APB2_GRP1_DisableClockSleep\n
2234 * MC_APB2LPENCLRR USART6 LL_APB2_GRP1_DisableClockSleep\n
2235 * MC_APB2LPENCLRR SAI1 LL_APB2_GRP1_DisableClockSleep\n
2236 * MC_APB2LPENCLRR SAI2 LL_APB2_GRP1_DisableClockSleep\n
2237 * MC_APB2LPENCLRR SAI3 LL_APB2_GRP1_DisableClockSleep\n
2238 * MC_APB2LPENCLRR DFSDM1 LL_APB2_GRP1_DisableClockSleep\n
2239 * MC_APB2LPENCLRR ADFSDM1 LL_APB2_GRP1_DisableClockSleep\n
2240 * MC_APB2LPENCLRR FDCAN LL_APB2_GRP1_DisableClockSleep
2241 * @param Periphs This parameter can be a combination of the following values:
2242 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2243 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2244 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2245 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2246 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2247 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2248 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2249 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2250 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2251 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2252 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2253 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
2254 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2255 * @arg @ref LL_APB2_GRP1_PERIPH_ADFSDM1
2256 * @arg @ref LL_APB2_GRP1_PERIPH_FDCAN
2257 * @retval None
2258 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)2259 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2260 {
2261 WRITE_REG(RCC->MC_APB2LPENCLRR, Periphs);
2262 }
2263
2264 /**
2265 * @}
2266 */
2267
2268 /** @defgroup BUS_LL_EF_APB3 APB3
2269 * @{
2270 */
2271
2272 /**
2273 * @brief Enable APB3 peripherals clock.
2274 * @rmtoll MC_APB3ENSETR LPTIM2 LL_APB3_GRP1_EnableClock\n
2275 * MC_APB3ENSETR LPTIM3 LL_APB3_GRP1_EnableClock\n
2276 * MC_APB3ENSETR LPTIM4 LL_APB3_GRP1_EnableClock\n
2277 * MC_APB3ENSETR LPTIM5 LL_APB3_GRP1_EnableClock\n
2278 * MC_APB3ENSETR SAI4 LL_APB3_GRP1_EnableClock\n
2279 * MC_APB3ENSETR SYSCFG LL_APB3_GRP1_EnableClock\n
2280 * MC_APB3ENSETR VREF LL_APB3_GRP1_EnableClock\n
2281 * MC_APB3ENSETR TMPSENS LL_APB3_GRP1_EnableClock\n
2282 * MC_APB3ENSETR PMBCTRL LL_APB3_GRP1_EnableClock\n
2283 * MC_APB3ENSETR HDP LL_APB3_GRP1_EnableClock
2284 * @param Periphs This parameter can be a combination of the following values:
2285 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM2
2286 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3
2287 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2288 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5
2289 * @arg @ref LL_APB3_GRP1_PERIPH_SAI4
2290 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2291 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2292 * @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
2293 * @arg @ref LL_APB3_GRP1_PERIPH_HDP
2294 * @retval None
2295 */
LL_APB3_GRP1_EnableClock(uint32_t Periphs)2296 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
2297 {
2298 __IO uint32_t tmpreg;
2299 WRITE_REG(RCC->MC_APB3ENSETR, Periphs);
2300 /* Delay after an RCC peripheral clock enabling */
2301 tmpreg = READ_BIT(RCC->MC_APB3ENSETR, Periphs);
2302 (void)tmpreg;
2303 }
2304
2305 /**
2306 * @brief Check if APB3 peripheral clock is enabled or not
2307 * @rmtoll MC_APB3ENSETR LPTIM2 LL_APB3_GRP1_IsEnabledClock\n
2308 * MC_APB3ENSETR LPTIM3 LL_APB3_GRP1_IsEnabledClock\n
2309 * MC_APB3ENSETR LPTIM4 LL_APB3_GRP1_IsEnabledClock\n
2310 * MC_APB3ENSETR LPTIM5 LL_APB3_GRP1_IsEnabledClock\n
2311 * MC_APB3ENSETR SAI4 LL_APB3_GRP1_IsEnabledClock\n
2312 * MC_APB3ENSETR SYSCFG LL_APB3_GRP1_IsEnabledClock\n
2313 * MC_APB3ENSETR VREF LL_APB3_GRP1_IsEnabledClock\n
2314 * MC_APB3ENSETR TMPSENS LL_APB3_GRP1_IsEnabledClock\n
2315 * MC_APB3ENSETR PMBCTRL LL_APB3_GRP1_IsEnabledClock\n
2316 * MC_APB3ENSETR HDP LL_APB3_GRP1_IsEnabledClock
2317 * @param Periphs This parameter can be a combination of the following values:
2318 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM2
2319 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3
2320 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2321 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5
2322 * @arg @ref LL_APB3_GRP1_PERIPH_SAI4
2323 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2324 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2325 * @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
2326 * @arg @ref LL_APB3_GRP1_PERIPH_HDP
2327 * @retval State of Periphs (1 or 0).
2328 */
LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)2329 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
2330 {
2331 return (READ_BIT(RCC->MC_APB3ENSETR, Periphs) == Periphs);
2332 }
2333
2334 /**
2335 * @brief Disable APB3 peripherals clock.
2336 * @rmtoll MC_APB3ENCLRR LPTIM2 LL_APB3_GRP1_DisableClock\n
2337 * MC_APB3ENCLRR LPTIM3 LL_APB3_GRP1_DisableClock\n
2338 * MC_APB3ENCLRR LPTIM4 LL_APB3_GRP1_DisableClock\n
2339 * MC_APB3ENCLRR LPTIM5 LL_APB3_GRP1_DisableClock
2340 * MC_APB3ENCLRR SAI4 LL_APB3_GRP1_DisableClock
2341 * MC_APB3ENCLRR SYSCFG LL_APB3_GRP1_DisableClock
2342 * MC_APB3ENCLRR VREF LL_APB3_GRP1_DisableClock
2343 * MC_APB3ENCLRR TMPSENS LL_APB3_GRP1_DisableClock
2344 * MC_APB3ENCLRR PMBCTRL LL_APB3_GRP1_DisableClock
2345 * MC_APB3ENCLRR HDP LL_APB3_GRP1_DisableClock
2346 * @param Periphs This parameter can be a combination of the following values:
2347 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM2
2348 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3
2349 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2350 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5
2351 * @arg @ref LL_APB3_GRP1_PERIPH_SAI4
2352 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2353 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2354 * @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
2355 * @arg @ref LL_APB3_GRP1_PERIPH_HDP
2356 * @retval None
2357 */
LL_APB3_GRP1_DisableClock(uint32_t Periphs)2358 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
2359 {
2360 WRITE_REG(RCC->MC_APB3ENCLRR, Periphs);
2361 }
2362
2363 /**
2364 * @brief Force APB3 peripherals reset.
2365 * @rmtoll APB3RSTSETR LPTIM2 LL_APB3_GRP1_ForceReset\n
2366 * APB3RSTSETR LPTIM3 LL_APB3_GRP1_ForceReset\n
2367 * APB3RSTSETR LPTIM4 LL_APB3_GRP1_ForceReset\n
2368 * APB3RSTSETR LPTIM5 LL_APB3_GRP1_ForceReset\n
2369 * APB3RSTSETR SAI4 LL_APB3_GRP1_ForceReset\n
2370 * APB3RSTSETR SYSCFG LL_APB3_GRP1_ForceReset\n
2371 * APB3RSTSETR VREF LL_APB3_GRP1_ForceReset\n
2372 * APB3RSTSETR TMPSENS LL_APB3_GRP1_ForceReset\n
2373 * APB3RSTSETR PMBCTRL LL_APB3_GRP1_ForceReset
2374 * @param Periphs This parameter can be a combination of the following values:
2375 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2376 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM2
2377 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3
2378 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2379 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5
2380 * @arg @ref LL_APB3_GRP1_PERIPH_SAI4
2381 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2382 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2383 * @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
2384 * @retval None
2385 */
LL_APB3_GRP1_ForceReset(uint32_t Periphs)2386 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
2387 {
2388 WRITE_REG(RCC->APB3RSTSETR, Periphs);
2389 }
2390
2391 /**
2392 * @brief Release APB3 peripherals reset.
2393 * @rmtoll APB3RSTCLRR LPTIM2 LL_APB3_GRP1_ReleaseReset\n
2394 * APB3RSTCLRR LPTIM3 LL_APB3_GRP1_ReleaseReset\n
2395 * APB3RSTCLRR LPTIM4 LL_APB3_GRP1_ReleaseReset\n
2396 * APB3RSTCLRR LPTIM5 LL_APB3_GRP1_ReleaseReset\n
2397 * APB3RSTCLRR SAI4 LL_APB3_GRP1_ReleaseReset\n
2398 * APB3RSTCLRR SYSCFG LL_APB3_GRP1_ReleaseReset\n
2399 * APB3RSTCLRR VREF LL_APB3_GRP1_ReleaseReset\n
2400 * APB3RSTCLRR TMPSENS LL_APB3_GRP1_ReleaseReset\n
2401 * APB3RSTCLRR PMBCTRL LL_APB3_GRP1_ReleaseReset
2402 * @param Periphs This parameter can be a combination of the following values:
2403 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2404 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM2
2405 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3
2406 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2407 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5
2408 * @arg @ref LL_APB3_GRP1_PERIPH_SAI4
2409 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2410 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2411 * @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
2412 * @retval None
2413 */
LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)2414 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
2415 {
2416 WRITE_REG(RCC->APB3RSTCLRR, Periphs);
2417 }
2418
2419 /**
2420 * @brief Enable APB3 peripheral clocks in Sleep mode
2421 * @rmtoll MC_APB3LPENSETR LPTIM2 LL_APB3_GRP1_EnableClockSleep\n
2422 * MC_APB3LPENSETR LPTIM3 LL_APB3_GRP1_EnableClockSleep\n
2423 * MC_APB3LPENSETR LPTIM4 LL_APB3_GRP1_EnableClockSleep\n
2424 * MC_APB3LPENSETR LPTIM5 LL_APB3_GRP1_EnableClockSleep\n
2425 * MC_APB3LPENSETR SAI4 LL_APB3_GRP1_EnableClockSleep\n
2426 * MC_APB3LPENSETR LPTIM5 LL_APB3_GRP1_EnableClockSleep\n
2427 * MC_APB3LPENSETR SYSCFG LL_APB3_GRP1_EnableClockSleep\n
2428 * MC_APB3LPENSETR VREF LL_APB3_GRP1_EnableClockSleep\n
2429 * MC_APB3LPENSETR TMPSENS LL_APB3_GRP1_EnableClockSleep\n
2430 * MC_APB3LPENSETR PMBCTRL LL_APB3_GRP1_EnableClockSleep
2431 * @param Periphs This parameter can be a combination of the following values:
2432 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM2
2433 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3
2434 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2435 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5
2436 * @arg @ref LL_APB3_GRP1_PERIPH_SAI4
2437 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2438 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2439 * @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
2440 * @retval None
2441 */
LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)2442 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
2443 {
2444 __IO uint32_t tmpreg;
2445 WRITE_REG(RCC->MC_APB3LPENSETR, Periphs);
2446 /* Delay after an RCC peripheral clock enabling */
2447 tmpreg = READ_BIT(RCC->MC_APB3LPENSETR, Periphs);
2448 (void)tmpreg;
2449 }
2450
2451 /**
2452 * @brief Disable APB3 peripheral clocks in Sleep modes
2453 * @rmtoll MC_APB3LPENCLRR LPTIM2 LL_APB3_GRP1_DisableClockSleep\n
2454 * MC_APB3LPENCLRR LPTIM3 LL_APB3_GRP1_DisableClockSleep\n
2455 * MC_APB3LPENCLRR LPTIM4 LL_APB3_GRP1_DisableClockSleep\n
2456 * MC_APB3LPENCLRR LPTIM5 LL_APB3_GRP1_DisableClockSleep\n
2457 * MC_APB3LPENCLRR SAI4 LL_APB3_GRP1_DisableClockSleep\n
2458 * MC_APB3LPENCLRR SYSCFG LL_APB3_GRP1_DisableClockSleep\n
2459 * MC_APB3LPENCLRR VREF LL_APB3_GRP1_DisableClockSleep\n
2460 * MC_APB3LPENCLRR TMPSENS LL_APB3_GRP1_DisableClockSleep\n
2461 * MC_APB3LPENCLRR PMBCTRL LL_APB3_GRP1_DisableClockSleep
2462 * @param Periphs This parameter can be a combination of the following values:
2463 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM2
2464 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3
2465 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
2466 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5
2467 * @arg @ref LL_APB3_GRP1_PERIPH_SAI4
2468 * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
2469 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2470 * @arg @ref LL_APB3_GRP1_PERIPH_TMPSENS
2471 * @retval None
2472 */
LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)2473 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
2474 {
2475 WRITE_REG(RCC->MC_APB3LPENCLRR, Periphs);
2476 }
2477
2478 /**
2479 * @}
2480 */
2481
2482 /** @defgroup BUS_LL_EF_APB4 APB4
2483 * @{
2484 */
2485
2486 /**
2487 * @brief Enable APB4 peripherals clock.
2488 * @rmtoll MC_APB4ENSETR LTDC LL_APB4_GRP1_EnableClock\n
2489 * MC_APB4ENSETR DSI LL_APB4_GRP1_EnableClock\n
2490 * MC_APB4ENSETR DDRPERFM LL_APB4_GRP1_EnableClock\n
2491 * MC_APB4ENSETR USBPHY LL_APB4_GRP1_EnableClock\n
2492 * MC_APB4ENSETR STGENRO LL_APB4_GRP1_EnableClock
2493 * @param Periphs This parameter can be a combination of the following values:
2494 * @arg @ref LL_APB4_GRP1_PERIPH_LTDC
2495 * @arg @ref LL_APB4_GRP1_PERIPH_DSI
2496 * @arg @ref LL_APB4_GRP1_PERIPH_DDRPERFM
2497 * @arg @ref LL_APB4_GRP1_PERIPH_USBPHY
2498 * @arg @ref LL_APB4_GRP1_PERIPH_STGENRO
2499 * @retval None
2500 */
LL_APB4_GRP1_EnableClock(uint32_t Periphs)2501 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
2502 {
2503 __IO uint32_t tmpreg;
2504 WRITE_REG(RCC->MC_APB4ENSETR, Periphs);
2505 /* Delay after an RCC peripheral clock enabling */
2506 tmpreg = READ_BIT(RCC->MC_APB4ENSETR, Periphs);
2507 (void)tmpreg;
2508 }
2509
2510 /**
2511 * @brief Check if APB4 peripheral clock is enabled or not
2512 * @rmtoll MC_APB4ENSETR LTDC LL_APB4_GRP1_IsEnabledClock\n
2513 * MC_APB4ENSETR DSI LL_APB4_GRP1_IsEnabledClock\n
2514 * MC_APB4ENSETR DDRPERFM LL_APB4_GRP1_IsEnabledClock\n
2515 * MC_APB4ENSETR USBPHY LL_APB4_GRP1_IsEnabledClock\n
2516 * MC_APB4ENSETR STGENRO LL_APB4_GRP1_IsEnabledClock
2517 * @param Periphs This parameter can be a combination of the following values:
2518 * @arg @ref LL_APB4_GRP1_PERIPH_LTDC
2519 * @arg @ref LL_APB4_GRP1_PERIPH_DSI
2520 * @arg @ref LL_APB4_GRP1_PERIPH_DDRPERFM
2521 * @arg @ref LL_APB4_GRP1_PERIPH_USBPHY
2522 * @arg @ref LL_APB4_GRP1_PERIPH_STGENRO
2523 * @retval State of Periphs (1 or 0).
2524 */
LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)2525 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
2526 {
2527 return (READ_BIT(RCC->MC_APB4ENSETR, Periphs) == Periphs);
2528 }
2529
2530 /**
2531 * @brief Disable APB4 peripherals clock.
2532 * @rmtoll MC_APB4ENCLRR LTDC LL_APB4_GRP1_DisableClock\n
2533 * MC_APB4ENCLRR DSI LL_APB4_GRP1_DisableClock\n
2534 * MC_APB4ENCLRR DDRPERFM LL_APB4_GRP1_DisableClock\n
2535 * MC_APB4ENCLRR USBPHY LL_APB4_GRP1_DisableClock\n
2536 * MC_APB4ENCLRR STGENRO LL_APB4_GRP1_DisableClock
2537 * @param Periphs This parameter can be a combination of the following values:
2538 * @arg @ref LL_APB4_GRP1_PERIPH_LTDC
2539 * @arg @ref LL_APB4_GRP1_PERIPH_DSI
2540 * @arg @ref LL_APB4_GRP1_PERIPH_DDRPERFM
2541 * @arg @ref LL_APB4_GRP1_PERIPH_USBPHY
2542 * @arg @ref LL_APB4_GRP1_PERIPH_STGENRO
2543 * @retval None
2544 */
LL_APB4_GRP1_DisableClock(uint32_t Periphs)2545 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
2546 {
2547 WRITE_REG(RCC->MC_APB4ENCLRR, Periphs);
2548 }
2549
2550 /**
2551 * @brief Force APB4 peripherals reset.
2552 * @rmtoll APB4RSTSETR LTDC LL_APB4_GRP1_ForceReset\n
2553 * APB4RSTSETR DSI LL_APB4_GRP1_ForceReset\n
2554 * APB4RSTSETR DDRPERFM LL_APB4_GRP1_ForceReset\n
2555 * APB4RSTSETR USBPHY LL_APB4_GRP1_ForceReset
2556 * @param Periphs This parameter can be a combination of the following values:
2557 * @arg @ref LL_APB4_GRP1_PERIPH_ALL
2558 * @arg @ref LL_APB4_GRP1_PERIPH_LTDC
2559 * @arg @ref LL_APB4_GRP1_PERIPH_DSI
2560 * @arg @ref LL_APB4_GRP1_PERIPH_DDRPERFM
2561 * @arg @ref LL_APB4_GRP1_PERIPH_USBPHY
2562 * @retval None
2563 */
LL_APB4_GRP1_ForceReset(uint32_t Periphs)2564 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
2565 {
2566 WRITE_REG(RCC->APB4RSTSETR, Periphs);
2567 }
2568
2569 /**
2570 * @brief Release APB4 peripherals reset.
2571 * @rmtoll APB4RSTCLRR LTDC LL_APB4_GRP1_ReleaseReset\n
2572 * APB4RSTCLRR DSI LL_APB4_GRP1_ReleaseReset\n
2573 * APB4RSTCLRR DDRPERFM LL_APB4_GRP1_ReleaseReset\n
2574 * APB4RSTCLRR USBPHY LL_APB4_GRP1_ReleaseReset
2575 * @param Periphs This parameter can be a combination of the following values:
2576 * @arg @ref LL_APB4_GRP1_PERIPH_ALL
2577 * @arg @ref LL_APB4_GRP1_PERIPH_LTDC
2578 * @arg @ref LL_APB4_GRP1_PERIPH_DSI
2579 * @arg @ref LL_APB4_GRP1_PERIPH_DDRPERFM
2580 * @arg @ref LL_APB4_GRP1_PERIPH_USBPHY
2581 * @retval None
2582 */
LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)2583 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
2584 {
2585 WRITE_REG(RCC->APB4RSTCLRR, Periphs);
2586 }
2587
2588 /**
2589 * @brief Enable APB4 peripheral clocks in Sleep mode
2590 * @rmtoll MC_APB4LPENSETR LTDC LL_APB4_GRP1_EnableClockSleep\n
2591 * MC_APB4LPENSETR DSI LL_APB4_GRP1_EnableClockSleep\n
2592 * MC_APB4LPENSETR DDRPERFM LL_APB4_GRP1_EnableClockSleep\n
2593 * MC_APB4LPENSETR USBPHY LL_APB4_GRP1_EnableClockSleep\n
2594 * MC_APB4LPENSETR STGENRO LL_APB4_GRP1_EnableClockSleep
2595 * @param Periphs This parameter can be a combination of the following values:
2596 * @arg @ref LL_APB4_GRP1_PERIPH_LTDC
2597 * @arg @ref LL_APB4_GRP1_PERIPH_DSI
2598 * @arg @ref LL_APB4_GRP1_PERIPH_DDRPERFM
2599 * @arg @ref LL_APB4_GRP1_PERIPH_USBPHY
2600 * @arg @ref LL_APB4_GRP1_PERIPH_STGENRO
2601 * @retval None
2602 */
LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)2603 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
2604 {
2605 __IO uint32_t tmpreg;
2606 WRITE_REG(RCC->MC_APB4LPENSETR, Periphs);
2607 /* Delay after an RCC peripheral clock enabling */
2608 tmpreg = READ_BIT(RCC->MC_APB4LPENSETR, Periphs);
2609 (void)tmpreg;
2610 }
2611
2612 /**
2613 * @brief Disable APB4 peripheral clocks in Sleep modes
2614 * @rmtoll MC_APB4LPENCLRR LTDC LL_APB4_GRP1_DisableClockSleep\n
2615 * MC_APB4LPENCLRR DSI LL_APB4_GRP1_DisableClockSleep\n
2616 * MC_APB4LPENCLRR DDRPERFM LL_APB4_GRP1_DisableClockSleep\n
2617 * MC_APB4LPENCLRR USBPHY LL_APB4_GRP1_DisableClockSleep\n
2618 * MC_APB4LPENCLRR STGENRO LL_APB4_GRP1_DisableClockSleep
2619 * @param Periphs This parameter can be a combination of the following values:
2620 * @arg @ref LL_APB4_GRP1_PERIPH_LTDC
2621 * @arg @ref LL_APB4_GRP1_PERIPH_DSI
2622 * @arg @ref LL_APB4_GRP1_PERIPH_DDRPERFM
2623 * @arg @ref LL_APB4_GRP1_PERIPH_USBPHY
2624 * @arg @ref LL_APB4_GRP1_PERIPH_STGENRO
2625 * @retval None
2626 */
LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)2627 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
2628 {
2629 WRITE_REG(RCC->MC_APB4LPENCLRR, Periphs);
2630 }
2631
2632 /**
2633 * @brief Enable APB4 peripheral clocks in Stop mode
2634 * @rmtoll MC_APB4LPENSETR STGENROSTPEN LL_APB4_GRP1_EnableClockStop
2635 * @param Periphs This parameter can be a combination of the following values:
2636 * @arg @ref LL_APB4_GRP1_PERIPH_STGENROSTP
2637 * @retval None
2638 */
LL_APB4_GRP1_EnableClockStop(uint32_t Periphs)2639 __STATIC_INLINE void LL_APB4_GRP1_EnableClockStop(uint32_t Periphs)
2640 {
2641 __IO uint32_t tmpreg;
2642 WRITE_REG(RCC->MC_APB4LPENSETR, Periphs);
2643 /* Delay after an RCC peripheral clock enabling */
2644 tmpreg = READ_BIT(RCC->MC_APB4LPENSETR, Periphs);
2645 (void)tmpreg;
2646 }
2647
2648 /**
2649 * @brief Disable APB4 peripheral clocks in Stop modes
2650 * @rmtoll MC_APB4LPENCLRR STGENROSTPEN LL_APB4_GRP1_DisableClockStop\n
2651 * @param Periphs This parameter can be a combination of the following values:
2652 * @arg @ref LL_APB4_GRP1_PERIPH_STGENROSTP
2653 * @retval None
2654 */
LL_APB4_GRP1_DisableClockStop(uint32_t Periphs)2655 __STATIC_INLINE void LL_APB4_GRP1_DisableClockStop(uint32_t Periphs)
2656 {
2657 WRITE_REG(RCC->MC_APB4LPENCLRR, Periphs);
2658 }
2659
2660 /**
2661 * @}
2662 */
2663
2664 /** @defgroup BUS_LL_EF_APB5 APB5
2665 * @{
2666 */
2667
2668 /**
2669 * @brief Enable APB5 peripherals clock.
2670 * @rmtoll MC_APB5ENSETR SPI6 LL_APB5_GRP1_EnableClock\n
2671 * MC_APB5ENSETR I2C4 LL_APB5_GRP1_EnableClock\n
2672 * MC_APB5ENSETR I2C6 LL_APB5_GRP1_EnableClock\n
2673 * MC_APB5ENSETR USART1 LL_APB5_GRP1_EnableClock\n
2674 * MC_APB5ENSETR RTCAPB LL_APB5_GRP1_EnableClock\n
2675 * MC_APB5ENSETR TZC1 LL_APB5_GRP1_EnableClock\n
2676 * MC_APB5ENSETR TZC2 LL_APB5_GRP1_EnableClock\n
2677 * MC_APB5ENSETR TZPC LL_APB5_GRP1_EnableClock\n
2678 * MC_APB5ENSETR BSEC LL_APB5_GRP1_EnableClock\n
2679 * MC_APB5ENSETR STGEN LL_APB5_GRP1_EnableClock
2680 * @param Periphs This parameter can be a combination of the following values:
2681 * @arg @ref LL_APB5_GRP1_PERIPH_SPI6
2682 * @arg @ref LL_APB5_GRP1_PERIPH_I2C4
2683 * @arg @ref LL_APB5_GRP1_PERIPH_I2C6
2684 * @arg @ref LL_APB5_GRP1_PERIPH_USART1
2685 * @arg @ref LL_APB5_GRP1_PERIPH_RTCAPB
2686 * @arg @ref LL_APB5_GRP1_PERIPH_TZC1
2687 * @arg @ref LL_APB5_GRP1_PERIPH_TZC2
2688 * @arg @ref LL_APB5_GRP1_PERIPH_TZPC
2689 * @arg @ref LL_APB5_GRP1_PERIPH_BSEC
2690 * @arg @ref LL_APB5_GRP1_PERIPH_STGEN
2691 * @retval None
2692 */
LL_APB5_GRP1_EnableClock(uint32_t Periphs)2693 __STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs)
2694 {
2695 __IO uint32_t tmpreg;
2696 WRITE_REG(RCC->MC_APB5ENSETR, Periphs);
2697 /* Delay after an RCC peripheral clock enabling */
2698 tmpreg = READ_BIT(RCC->MC_APB5ENSETR, Periphs);
2699 (void)tmpreg;
2700 }
2701
2702 /**
2703 * @brief Check if APB5 peripheral clock is enabled or not
2704 * @rmtoll MC_APB5ENSETR SPI6 LL_APB5_GRP1_IsEnabledClock\n
2705 * MC_APB5ENSETR I2C4 LL_APB5_GRP1_IsEnabledClock\n
2706 * MC_APB5ENSETR I2C6 LL_APB5_GRP1_IsEnabledClock\n
2707 * MC_APB5ENSETR USART1 LL_APB5_GRP1_IsEnabledClock\n
2708 * MC_APB5ENSETR RTCAPB LL_APB5_GRP1_IsEnabledClock\n
2709 * MC_APB5ENSETR TZC1 LL_APB5_GRP1_IsEnabledClock\n
2710 * MC_APB5ENSETR TZC2 LL_APB5_GRP1_IsEnabledClock\n
2711 * MC_APB5ENSETR TZPC LL_APB5_GRP1_IsEnabledClock\n
2712 * MC_APB5ENSETR BSEC LL_APB5_GRP1_IsEnabledClock\n
2713 * MC_APB5ENSETR STGEN LL_APB5_GRP1_IsEnabledClock
2714 * @param Periphs This parameter can be a combination of the following values:
2715 * @arg @ref LL_APB5_GRP1_PERIPH_SPI6
2716 * @arg @ref LL_APB5_GRP1_PERIPH_I2C4
2717 * @arg @ref LL_APB5_GRP1_PERIPH_I2C6
2718 * @arg @ref LL_APB5_GRP1_PERIPH_USART1
2719 * @arg @ref LL_APB5_GRP1_PERIPH_RTCAPB
2720 * @arg @ref LL_APB5_GRP1_PERIPH_TZC1
2721 * @arg @ref LL_APB5_GRP1_PERIPH_TZC2
2722 * @arg @ref LL_APB5_GRP1_PERIPH_TZPC
2723 * @arg @ref LL_APB5_GRP1_PERIPH_BSEC
2724 * @arg @ref LL_APB5_GRP1_PERIPH_STGEN
2725 * @retval State of Periphs (1 or 0).
2726 */
LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)2727 __STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)
2728 {
2729 return (READ_BIT(RCC->MC_APB5ENSETR, Periphs) == Periphs);
2730 }
2731
2732 /**
2733 * @brief Disable APB5 peripherals clock.
2734 * @rmtoll MC_APB5ENCLRR SPI6 LL_APB5_GRP1_DisableClock\n
2735 * MC_APB5ENCLRR I2C4 LL_APB5_GRP1_DisableClock\n
2736 * MC_APB5ENCLRR I2C6 LL_APB5_GRP1_DisableClock\n
2737 * MC_APB5ENCLRR USART1 LL_APB5_GRP1_DisableClock\n
2738 * MC_APB5ENCLRR RTCAPB LL_APB5_GRP1_DisableClock\n
2739 * MC_APB5ENCLRR TZC1 LL_APB5_GRP1_DisableClock\n
2740 * MC_APB5ENCLRR TZC2 LL_APB5_GRP1_DisableClock\n
2741 * MC_APB5ENCLRR TZPC LL_APB5_GRP1_DisableClock\n
2742 * MC_APB5ENCLRR BSEC LL_APB5_GRP1_DisableClock\n
2743 * MC_APB5ENCLRR STGEN LL_APB5_GRP1_DisableClock
2744 * @param Periphs This parameter can be a combination of the following values:
2745 * @arg @ref LL_APB5_GRP1_PERIPH_SPI6
2746 * @arg @ref LL_APB5_GRP1_PERIPH_I2C4
2747 * @arg @ref LL_APB5_GRP1_PERIPH_I2C6
2748 * @arg @ref LL_APB5_GRP1_PERIPH_USART1
2749 * @arg @ref LL_APB5_GRP1_PERIPH_RTCAPB
2750 * @arg @ref LL_APB5_GRP1_PERIPH_TZC1
2751 * @arg @ref LL_APB5_GRP1_PERIPH_TZC2
2752 * @arg @ref LL_APB5_GRP1_PERIPH_TZPC
2753 * @arg @ref LL_APB5_GRP1_PERIPH_BSEC
2754 * @arg @ref LL_APB5_GRP1_PERIPH_STGEN
2755 * @retval None
2756 */
LL_APB5_GRP1_DisableClock(uint32_t Periphs)2757 __STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs)
2758 {
2759 WRITE_REG(RCC->MC_APB5ENCLRR, Periphs);
2760 }
2761
2762 /**
2763 * @brief Force APB5 peripherals reset.
2764 * @rmtoll APB5RSTSETR SPI6 LL_APB5_GRP1_ForceReset\n
2765 * APB5RSTSETR I2C4 LL_APB5_GRP1_ForceReset\n
2766 * APB5RSTSETR I2C6 LL_APB5_GRP1_ForceReset\n
2767 * APB5RSTSETR USART1 LL_APB5_GRP1_ForceReset\n
2768 * APB5RSTSETR STGEN LL_APB5_GRP1_ForceReset
2769 * @param Periphs This parameter can be a combination of the following values:
2770 * @arg @ref LL_APB5_GRP1_PERIPH_ALL
2771 * @arg @ref LL_APB5_GRP1_PERIPH_SPI6
2772 * @arg @ref LL_APB5_GRP1_PERIPH_I2C4
2773 * @arg @ref LL_APB5_GRP1_PERIPH_I2C6
2774 * @arg @ref LL_APB5_GRP1_PERIPH_USART1
2775 * @arg @ref LL_APB5_GRP1_PERIPH_STGEN
2776 * @retval None
2777 */
LL_APB5_GRP1_ForceReset(uint32_t Periphs)2778 __STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs)
2779 {
2780 WRITE_REG(RCC->APB5RSTSETR, Periphs);
2781 }
2782
2783 /**
2784 * @brief Release APB5 peripherals reset.
2785 * @rmtoll APB5RSTCLRR SPI6 LL_APB5_GRP1_ReleaseReset\n
2786 * APB5RSTCLRR I2C4 LL_APB5_GRP1_ReleaseReset\n
2787 * APB5RSTCLRR I2C6 LL_APB5_GRP1_ReleaseReset\n
2788 * APB5RSTCLRR USART1 LL_APB5_GRP1_ReleaseReset\n
2789 * APB5RSTCLRR STGEN LL_APB5_GRP1_ReleaseReset
2790 * @param Periphs This parameter can be a combination of the following values:
2791 * @arg @ref LL_APB5_GRP1_PERIPH_ALL
2792 * @arg @ref LL_APB5_GRP1_PERIPH_SPI6
2793 * @arg @ref LL_APB5_GRP1_PERIPH_I2C4
2794 * @arg @ref LL_APB5_GRP1_PERIPH_I2C6
2795 * @arg @ref LL_APB5_GRP1_PERIPH_USART1
2796 * @arg @ref LL_APB5_GRP1_PERIPH_STGEN
2797 * @retval None
2798 */
LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)2799 __STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)
2800 {
2801 WRITE_REG(RCC->APB5RSTCLRR, Periphs);
2802 }
2803
2804 /**
2805 * @brief Enable APB5 peripheral clocks in Sleep mode
2806 * @rmtoll MC_APB5LPENSETR SPI6 LL_APB5_GRP1_EnableClockSleep\n
2807 * MC_APB5LPENSETR I2C4 LL_APB5_GRP1_EnableClockSleep\n
2808 * MC_APB5LPENSETR I2C6 LL_APB5_GRP1_EnableClockSleep\n
2809 * MC_APB5LPENSETR USART1 LL_APB5_GRP1_EnableClockSleep\n
2810 * MC_APB5LPENSETR RTCAPB LL_APB5_GRP1_EnableClockSleep\n
2811 * MC_APB5LPENSETR TZC1 LL_APB5_GRP1_EnableClockSleep\n
2812 * MC_APB5LPENSETR TZC2 LL_APB5_GRP1_EnableClockSleep\n
2813 * MC_APB5LPENSETR TZPC LL_APB5_GRP1_EnableClockSleep\n
2814 * MC_APB5LPENSETR BSEC LL_APB5_GRP1_EnableClockSleep\n
2815 * MC_APB5LPENSETR STGEN LL_APB5_GRP1_EnableClockSleep
2816 * @param Periphs This parameter can be a combination of the following values:
2817 * @arg @ref LL_APB5_GRP1_PERIPH_SPI6
2818 * @arg @ref LL_APB5_GRP1_PERIPH_I2C4
2819 * @arg @ref LL_APB5_GRP1_PERIPH_I2C6
2820 * @arg @ref LL_APB5_GRP1_PERIPH_USART1
2821 * @arg @ref LL_APB5_GRP1_PERIPH_RTCAPB
2822 * @arg @ref LL_APB5_GRP1_PERIPH_TZC1
2823 * @arg @ref LL_APB5_GRP1_PERIPH_TZC2
2824 * @arg @ref LL_APB5_GRP1_PERIPH_TZPC
2825 * @arg @ref LL_APB5_GRP1_PERIPH_BSEC
2826 * @arg @ref LL_APB5_GRP1_PERIPH_STGEN
2827 * @retval None
2828 */
LL_APB5_GRP1_EnableClockSleep(uint32_t Periphs)2829 __STATIC_INLINE void LL_APB5_GRP1_EnableClockSleep(uint32_t Periphs)
2830 {
2831 __IO uint32_t tmpreg;
2832 WRITE_REG(RCC->MC_APB5LPENSETR, Periphs);
2833 /* Delay after an RCC peripheral clock enabling */
2834 tmpreg = READ_BIT(RCC->MC_APB5LPENSETR, Periphs);
2835 (void)tmpreg;
2836 }
2837
2838 /**
2839 * @brief Disable APB5 peripheral clocks in Sleep modes
2840 * @rmtoll MC_APB5LPENCLRR SPI6 LL_APB5_GRP1_DisableClockSleep\n
2841 * MC_APB5LPENCLRR I2C4 LL_APB5_GRP1_DisableClockSleep\n
2842 * MC_APB5LPENCLRR I2C6 LL_APB5_GRP1_DisableClockSleep\n
2843 * MC_APB5LPENCLRR USART1 LL_APB5_GRP1_DisableClockSleep\n
2844 * MC_APB5LPENCLRR RTCAPB LL_APB5_GRP1_DisableClockSleep\n
2845 * MC_APB5LPENCLRR TZC1 LL_APB5_GRP1_DisableClockSleep\n
2846 * MC_APB5LPENCLRR TZC2 LL_APB5_GRP1_DisableClockSleep\n
2847 * MC_APB5LPENCLRR TZPC LL_APB5_GRP1_DisableClockSleep\n
2848 * MC_APB5LPENCLRR BSEC LL_APB5_GRP1_DisableClockSleep\n
2849 * MC_APB5LPENCLRR STGEN LL_APB5_GRP1_DisableClockSleep
2850 * @param Periphs This parameter can be a combination of the following values:
2851 * @arg @ref LL_APB5_GRP1_PERIPH_SPI6
2852 * @arg @ref LL_APB5_GRP1_PERIPH_I2C4
2853 * @arg @ref LL_APB5_GRP1_PERIPH_I2C6
2854 * @arg @ref LL_APB5_GRP1_PERIPH_USART1
2855 * @arg @ref LL_APB5_GRP1_PERIPH_RTCAPB
2856 * @arg @ref LL_APB5_GRP1_PERIPH_TZC1
2857 * @arg @ref LL_APB5_GRP1_PERIPH_TZC2
2858 * @arg @ref LL_APB5_GRP1_PERIPH_TZPC
2859 * @arg @ref LL_APB5_GRP1_PERIPH_BSEC
2860 * @arg @ref LL_APB5_GRP1_PERIPH_STGEN
2861 * @retval None
2862 */
LL_APB5_GRP1_DisableClockSleep(uint32_t Periphs)2863 __STATIC_INLINE void LL_APB5_GRP1_DisableClockSleep(uint32_t Periphs)
2864 {
2865 WRITE_REG(RCC->MC_APB5LPENCLRR, Periphs);
2866 }
2867
2868 /**
2869 * @brief Enable APB5 peripheral clocks in Stop mode
2870 * @rmtoll MC_APB5LPENSETR STGENSTP LL_APB5_GRP1_EnableClockStop
2871 * @param Periphs This parameter can be a combination of the following values:
2872 * @arg @ref LL_APB5_GRP1_PERIPH_STGENSTP
2873 * @retval None
2874 */
LL_APB5_GRP1_EnableClockStop(uint32_t Periphs)2875 __STATIC_INLINE void LL_APB5_GRP1_EnableClockStop(uint32_t Periphs)
2876 {
2877 __IO uint32_t tmpreg;
2878 WRITE_REG(RCC->MC_APB5LPENSETR, Periphs);
2879 /* Delay after an RCC peripheral clock enabling */
2880 tmpreg = READ_BIT(RCC->MC_APB5LPENSETR, Periphs);
2881 (void)tmpreg;
2882 }
2883
2884 /**
2885 * @brief Disable APB5 peripheral clocks in Stop modes
2886 * @rmtoll MC_APB5LPENCLRR STGENSTP LL_APB5_GRP1_DisableClockStop\n
2887 * @param Periphs This parameter can be a combination of the following values:
2888 * @arg @ref LL_APB5_GRP1_PERIPH_STGENSTP
2889 * @retval None
2890 */
LL_APB5_GRP1_DisableClockStop(uint32_t Periphs)2891 __STATIC_INLINE void LL_APB5_GRP1_DisableClockStop(uint32_t Periphs)
2892 {
2893 WRITE_REG(RCC->MC_APB5LPENCLRR, Periphs);
2894 }
2895
2896 /**
2897 * @}
2898 */
2899
2900 /**
2901 * @}
2902 */
2903
2904 /**
2905 * @}
2906 */
2907
2908 #endif /* defined(RCC) */
2909
2910 /**
2911 * @}
2912 */
2913
2914 #ifdef __cplusplus
2915 }
2916 #endif
2917
2918 #endif /* STM32MP1xx_LL_BUS_H */
2919
