1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2020 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28 (+) Access to VREFBUF registers
29
30 @endverbatim
31 ******************************************************************************
32 */
33
34 /* Define to prevent recursive inclusion -------------------------------------*/
35 #ifndef STM32WLxx_LL_SYSTEM_H
36 #define STM32WLxx_LL_SYSTEM_H
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32wlxx.h"
44
45 /** @addtogroup STM32WLxx_LL_Driver
46 * @{
47 */
48
49 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
50
51 /** @defgroup SYSTEM_LL SYSTEM
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57
58 /* Private constants ---------------------------------------------------------*/
59 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
60 * @{
61 */
62 #define LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */
63
64 /**
65 * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
66 */
67 #define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x1FFF75F0UL)) /*!< Address of VREFBUF trimming value for VRS=0,
68 VREF_SC0 in STM32WL datasheet */
69 #define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x1FFF7530UL)) /*!< Address of VREFBUF trimming value for VRS=1,
70 VREF_SC1 in STM32WL datasheet */
71 /**
72 * @}
73 */
74
75 /* Private macros ------------------------------------------------------------*/
76
77 /* Exported types ------------------------------------------------------------*/
78 /* Exported constants --------------------------------------------------------*/
79 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
80 * @{
81 */
82
83 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
84 * @{
85 */
86 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
87 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
88 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
89 /**
90 * @}
91 */
92
93 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
94 * @{
95 */
96 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
97 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
98 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
99 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
100 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
101 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
102 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
103 /**
104 * @}
105 */
106
107 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
108 * @{
109 */
110 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
111 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
112 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
113 /**
114 * @}
115 */
116
117 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
118 * @{
119 */
120 #if defined(CORE_CM0PLUS)
121 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
122 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)((4U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
123 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)((8U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
124 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)((12U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
125 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
126 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)((4U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
127 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)((8U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
128 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)((12U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
129 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
130 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)((4U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
131 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)((8U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
132 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)((12U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
133 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
134 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)((4U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
135 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)((8U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
136 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)((12U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
137 #else
138 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
139 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
140 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
141 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
142 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
143 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
144 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
145 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
146 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
147 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
148 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
149 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
150 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
151 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
152 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
153 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
154 #endif
155 /**
156 * @}
157 */
158
159 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
160 * @{
161 */
162 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
163 with Break Input of TIM1/16/17 */
164 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
165 with TIM1/16/17 Break Input
166 and also the PVDE and PLS bits of the Power Control Interface */
167 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
168 with Break Input of TIM1/16/17 */
169 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
170 with Break Input of TIM1/16/17 */
171 /**
172 * @}
173 */
174
175 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRITE PROTECTION
176 * @{
177 */
178 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
179 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
180 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
181 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
182 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
183 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
184 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
185 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
186 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
187 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
188 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
189 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
190 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
191 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
192 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
193 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
194 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
195 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
196 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
197 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
198 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
199 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
200 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
201 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
202 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
203 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
204 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
205 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
206 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
207 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
208 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
209 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
210 /**
211 * @}
212 */
213
214 #if defined(DUAL_CORE)
215 /** @defgroup SYSTEM_LL_EC_IM SYSCFG CPU1 INTERRUPT MASK
216 * @{
217 */
218 #define LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM /*!< Enabling of interrupt from RTCSTAMPTAMPLSECSS to CPU1 */
219 #define LL_SYSCFG_GRP1_RTCSSRU SYSCFG_IMR1_RTCSSRUIM /*!< Enabling of interrupt from RTC SSRU to CPU1 */
220 #define LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */
221 #define LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */
222 #define LL_SYSCFG_GRP1_EXTI7 SYSCFG_IMR1_EXTI7IM /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1 */
223 #define LL_SYSCFG_GRP1_EXTI8 SYSCFG_IMR1_EXTI8IM /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1 */
224 #define LL_SYSCFG_GRP1_EXTI9 SYSCFG_IMR1_EXTI9IM /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1 */
225 #define LL_SYSCFG_GRP1_EXTI10 SYSCFG_IMR1_EXTI10IM /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */
226 #define LL_SYSCFG_GRP1_EXTI11 SYSCFG_IMR1_EXTI11IM /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */
227 #define LL_SYSCFG_GRP1_EXTI12 SYSCFG_IMR1_EXTI12IM /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */
228 #define LL_SYSCFG_GRP1_EXTI13 SYSCFG_IMR1_EXTI13IM /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */
229 #define LL_SYSCFG_GRP1_EXTI14 SYSCFG_IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */
230 #define LL_SYSCFG_GRP1_EXTI15 SYSCFG_IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */
231
232 #define LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */
233 #define LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */
234 /**
235 * @}
236 */
237
238 /** @defgroup SYSTEM_LL_EC_C2_IM SYSCFG CPU2 INTERRUPT MASK
239 * @{
240 */
241 #define LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers
242 and LSE Clock Security System to CPU2 */
243 #define LL_C2_SYSCFG_GRP1_RTCALARM SYSCFG_C2IMR1_RTCALARMIM /*!< Enabling of interrupt from RTC Alarms to CPU2 */
244 #define LL_C2_SYSCFG_GRP1_RTCSSRU SYSCFG_C2IMR1_RTCSSRUIM /*!< Enabling of interrupt from RTC SSRU to CPU2 */
245 #define LL_C2_SYSCFG_GRP1_RTCWKUP SYSCFG_C2IMR1_RTCWKUPIM /*!< Enabling of interrupt from RTC Wakeup to CPU2 */
246 #define LL_C2_SYSCFG_GRP1_RCC SYSCFG_C2IMR1_RCCIM /*!< Enabling of interrupt from RCC to CPU2 */
247 #define LL_C2_SYSCFG_GRP1_FLASH SYSCFG_C2IMR1_FLASHIM /*!< Enabling of interrupt from FLASH to CPU2 */
248 #define LL_C2_SYSCFG_GRP1_PKA SYSCFG_C2IMR1_PKAIM /*!< Enabling of interrupt from PKA to CPU2 */
249 #define LL_C2_SYSCFG_GRP1_AES SYSCFG_C2IMR1_AESIM /*!< Enabling of interrupt from AES to CPU2 */
250 #define LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM /*!< Enabling of interrupt from Comparator to CPU2 */
251 #define LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */
252 #define LL_C2_SYSCFG_GRP1_DAC SYSCFG_C2IMR1_DACIM /*!< Enabling of interrupt from Digital Analog Converter to CPU2 */
253
254 #define LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */
255 #define LL_C2_SYSCFG_GRP1_EXTI1 SYSCFG_C2IMR1_EXTI1IM /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2 */
256 #define LL_C2_SYSCFG_GRP1_EXTI2 SYSCFG_C2IMR1_EXTI2IM /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2 */
257 #define LL_C2_SYSCFG_GRP1_EXTI3 SYSCFG_C2IMR1_EXTI3IM /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2 */
258 #define LL_C2_SYSCFG_GRP1_EXTI4 SYSCFG_C2IMR1_EXTI4IM /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2 */
259 #define LL_C2_SYSCFG_GRP1_EXTI5 SYSCFG_C2IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2 */
260 #define LL_C2_SYSCFG_GRP1_EXTI6 SYSCFG_C2IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2 */
261 #define LL_C2_SYSCFG_GRP1_EXTI7 SYSCFG_C2IMR1_EXTI7IM /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2 */
262 #define LL_C2_SYSCFG_GRP1_EXTI8 SYSCFG_C2IMR1_EXTI8IM /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2 */
263 #define LL_C2_SYSCFG_GRP1_EXTI9 SYSCFG_C2IMR1_EXTI9IM /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2 */
264 #define LL_C2_SYSCFG_GRP1_EXTI10 SYSCFG_C2IMR1_EXTI10IM /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */
265 #define LL_C2_SYSCFG_GRP1_EXTI11 SYSCFG_C2IMR1_EXTI11IM /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */
266 #define LL_C2_SYSCFG_GRP1_EXTI12 SYSCFG_C2IMR1_EXTI12IM /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */
267 #define LL_C2_SYSCFG_GRP1_EXTI13 SYSCFG_C2IMR1_EXTI13IM /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */
268 #define LL_C2_SYSCFG_GRP1_EXTI14 SYSCFG_C2IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */
269 #define LL_C2_SYSCFG_GRP1_EXTI15 SYSCFG_C2IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */
270
271 #define LL_C2_SYSCFG_GRP2_DMA1CH1 SYSCFG_C2IMR2_DMA1CH1IM /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2 */
272 #define LL_C2_SYSCFG_GRP2_DMA1CH2 SYSCFG_C2IMR2_DMA1CH2IM /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2 */
273 #define LL_C2_SYSCFG_GRP2_DMA1CH3 SYSCFG_C2IMR2_DMA1CH3IM /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2 */
274 #define LL_C2_SYSCFG_GRP2_DMA1CH4 SYSCFG_C2IMR2_DMA1CH4IM /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2 */
275 #define LL_C2_SYSCFG_GRP2_DMA1CH5 SYSCFG_C2IMR2_DMA1CH5IM /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2 */
276 #define LL_C2_SYSCFG_GRP2_DMA1CH6 SYSCFG_C2IMR2_DMA1CH6IM /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */
277 #define LL_C2_SYSCFG_GRP2_DMA1CH7 SYSCFG_C2IMR2_DMA1CH7IM /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */
278
279 #define LL_C2_SYSCFG_GRP2_DMA2CH1 SYSCFG_C2IMR2_DMA2CH1IM /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2 */
280 #define LL_C2_SYSCFG_GRP2_DMA2CH2 SYSCFG_C2IMR2_DMA2CH2IM /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2 */
281 #define LL_C2_SYSCFG_GRP2_DMA2CH3 SYSCFG_C2IMR2_DMA2CH3IM /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2 */
282 #define LL_C2_SYSCFG_GRP2_DMA2CH4 SYSCFG_C2IMR2_DMA2CH4IM /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2 */
283 #define LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */
284 #define LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */
285 #define LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */
286
287 #define LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM /*!< Enabling of interrupt from DMAMUX1 to CPU2 */
288
289 #define LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */
290 #define LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */
291 /**
292 * @}
293 */
294 #endif
295
296 /** @defgroup SYSTEM_LL_EC_RF_TEST_BUS_TYPE SYSCFG RF TEST BUS TYPE
297 * @{
298 */
299 #define LL_SYSCFG_ANALOG_TEST_BUS SYSCFG_RFDCR_RFTBSEL /*!< Analog test bus selected on RF_ADTB[3:0] */
300 #define LL_SYSCFG_DIGITAL_TEST_BUS 0x00000000U /*!< Digital test bus selected on RF_ADTB[3:0] */
301 /**
302 * @}
303 */
304
305
306 #if defined(CORE_CM0PLUS)
307 #else
308 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU CPU1 APB1 GRP1 STOP IP
309 * @{
310 */
311 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted */
312 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */
313 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The watchdog counter clock is stopped when the core is halted */
314 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */
315 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */
316 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen */
317 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */
318 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */
319 /**
320 * @}
321 */
322
323 #if defined(DUAL_CORE)
324 /** @defgroup SYSTEM_LL_EC_C2_APB1_GRP1_STOP_IP DBGMCU CPU2 APB1 GRP1 STOP IP
325 * @{
326 */
327 #define LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted */
328 #define LL_C2_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */
329 #define LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */
330 #define LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */
331 #define LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_C2APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen */
332 #define LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */
333 #define LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */
334 /**
335 * @}
336 */
337 #endif /* DUAL_CORE */
338
339 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU CPU1 APB1 GRP2 STOP IP
340 * @{
341 */
342 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */
343 #define LL_DBGMCU_APB1_GRP2_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted */
344 /**
345 * @}
346 */
347
348 #if defined(DUAL_CORE)
349 /** @defgroup SYSTEM_LL_EC_C2_APB1_GRP2_STOP_IP DBGMCU CPU2 APB1 GRP2 STOP IP
350 * @{
351 */
352 #define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */
353 #define LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted */
354 /**
355 * @}
356 */
357 #endif /* DUAL_CORE */
358
359 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU CPU1 APB2 GRP1 STOP IP
360 * @{
361 */
362 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
363 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
364 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
365 /**
366 * @}
367 */
368
369 #if defined(DUAL_CORE)
370 /** @defgroup SYSTEM_LL_EC_C2_APB2_GRP1_STOP_IP DBGMCU CPU2 APB2 GRP1 STOP IP
371 * @{
372 */
373 #define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
374 #define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
375 #define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
376 /**
377 * @}
378 */
379 #endif /* DUAL_CORE */
380
381 #endif
382
383 #if defined(VREFBUF)
384 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
385 * @{
386 */
387 #define LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREF_OUT1) */
388 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
389 /**
390 * @}
391 */
392 #endif /* VREFBUF */
393
394 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
395 * @{
396 */
397 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero wait state */
398 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */
399 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
400 /**
401 * @}
402 */
403
404 /**
405 * @}
406 */
407
408 /* Exported macro ------------------------------------------------------------*/
409
410 /* Exported functions --------------------------------------------------------*/
411 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
412 * @{
413 */
414
415 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
416 * @{
417 */
418
419 /**
420 * @brief Set memory mapping at address 0x00000000
421 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
422 * @param Memory This parameter can be one of the following values:
423 * @arg @ref LL_SYSCFG_REMAP_FLASH
424 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
425 * @arg @ref LL_SYSCFG_REMAP_SRAM
426 * @retval None
427 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)428 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
429 {
430 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
431 }
432
433 /**
434 * @brief Get memory mapping at address 0x00000000
435 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
436 * @retval Returned value can be one of the following values:
437 * @arg @ref LL_SYSCFG_REMAP_FLASH
438 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
439 * @arg @ref LL_SYSCFG_REMAP_SRAM
440 */
LL_SYSCFG_GetRemapMemory(void)441 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
442 {
443 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
444 }
445
446 /**
447 * @brief Enable I/O analog switch voltage booster.
448 * @note When voltage booster is enabled, I/O analog switches are supplied
449 * by a dedicated voltage booster, from VDD power domain. This is
450 * the recommended configuration with low VDDA voltage operation.
451 * @note The I/O analog switch voltage booster is relevant for peripherals
452 * using I/O in analog input: ADC and COMP.
453 * However, COMP inputs have a high impedance and
454 * voltage booster do not impact performance significantly.
455 * Therefore, the voltage booster is mainly intended for
456 * usage with ADC.
457 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
458 * @retval None
459 */
LL_SYSCFG_EnableAnalogBooster(void)460 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
461 {
462 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
463 }
464
465 /**
466 * @brief Disable I/O analog switch voltage booster.
467 * @note When voltage booster is enabled, I/O analog switches are supplied
468 * by a dedicated voltage booster, from VDD power domain. This is
469 * the recommended configuration with low VDDA voltage operation.
470 * @note The I/O analog switch voltage booster is relevant for peripherals
471 * using I/O in analog input: ADC and COMP.
472 * However, COMP inputs have a high impedance and
473 * voltage booster do not impact performance significantly.
474 * Therefore, the voltage booster is mainly intended for
475 * usage with ADC.
476 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
477 * @retval None
478 */
LL_SYSCFG_DisableAnalogBooster(void)479 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
480 {
481 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
482 }
483
484 /**
485 * @brief Enable the I2C fast mode plus driving capability.
486 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
487 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
488 * @param ConfigFastModePlus This parameter can be a combination of the following values:
489 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
490 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
491 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
492 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
493 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
494 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
495 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
496 * @retval None
497 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)498 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
499 {
500 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
501 }
502
503 /**
504 * @brief Disable the I2C fast mode plus driving capability.
505 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
506 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
507 * @param ConfigFastModePlus This parameter can be a combination of the following values:
508 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
509 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
510 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
511 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
512 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
513 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
514 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
515 * @retval None
516 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)517 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
518 {
519 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
520 }
521
522 /**
523 * @brief Configure source input for the EXTI external interrupt.
524 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
525 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
526 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
527 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
528 * @param Port This parameter can be one of the following values:
529 * @arg @ref LL_SYSCFG_EXTI_PORTA
530 * @arg @ref LL_SYSCFG_EXTI_PORTB
531 * @arg @ref LL_SYSCFG_EXTI_PORTC
532 *
533 * @param Line This parameter can be one of the following values:
534 * @arg @ref LL_SYSCFG_EXTI_LINE0
535 * @arg @ref LL_SYSCFG_EXTI_LINE1
536 * @arg @ref LL_SYSCFG_EXTI_LINE2
537 * @arg @ref LL_SYSCFG_EXTI_LINE3
538 * @arg @ref LL_SYSCFG_EXTI_LINE4
539 * @arg @ref LL_SYSCFG_EXTI_LINE5
540 * @arg @ref LL_SYSCFG_EXTI_LINE6
541 * @arg @ref LL_SYSCFG_EXTI_LINE7
542 * @arg @ref LL_SYSCFG_EXTI_LINE8
543 * @arg @ref LL_SYSCFG_EXTI_LINE9
544 * @arg @ref LL_SYSCFG_EXTI_LINE10
545 * @arg @ref LL_SYSCFG_EXTI_LINE11
546 * @arg @ref LL_SYSCFG_EXTI_LINE12
547 * @arg @ref LL_SYSCFG_EXTI_LINE13
548 * @arg @ref LL_SYSCFG_EXTI_LINE14
549 * @arg @ref LL_SYSCFG_EXTI_LINE15
550 * @retval None
551 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)552 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
553 {
554 #if defined(CORE_CM0PLUS)
555 MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], SYSCFG_EXTICR1_EXTI0 << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL), (Port << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL)));
556 #else
557 MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT), (Port << ((POSITION_VAL((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT))) & 0x0000000FUL)));
558 #endif
559 }
560
561 /**
562 * @brief Get the configured defined for specific EXTI Line
563 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
564 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
565 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
566 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
567 * @param Line This parameter can be one of the following values:
568 * @arg @ref LL_SYSCFG_EXTI_LINE0
569 * @arg @ref LL_SYSCFG_EXTI_LINE1
570 * @arg @ref LL_SYSCFG_EXTI_LINE2
571 * @arg @ref LL_SYSCFG_EXTI_LINE3
572 * @arg @ref LL_SYSCFG_EXTI_LINE4
573 * @arg @ref LL_SYSCFG_EXTI_LINE5
574 * @arg @ref LL_SYSCFG_EXTI_LINE6
575 * @arg @ref LL_SYSCFG_EXTI_LINE7
576 * @arg @ref LL_SYSCFG_EXTI_LINE8
577 * @arg @ref LL_SYSCFG_EXTI_LINE9
578 * @arg @ref LL_SYSCFG_EXTI_LINE10
579 * @arg @ref LL_SYSCFG_EXTI_LINE11
580 * @arg @ref LL_SYSCFG_EXTI_LINE12
581 * @arg @ref LL_SYSCFG_EXTI_LINE13
582 * @arg @ref LL_SYSCFG_EXTI_LINE14
583 * @arg @ref LL_SYSCFG_EXTI_LINE15
584 * @retval Returned value can be one of the following values:
585 * @arg @ref LL_SYSCFG_EXTI_PORTA
586 * @arg @ref LL_SYSCFG_EXTI_PORTB
587 * @arg @ref LL_SYSCFG_EXTI_PORTC
588 */
LL_SYSCFG_GetEXTISource(uint32_t Line)589 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
590 {
591 #if defined(CORE_CM0PLUS)
592 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (SYSCFG_EXTICR1_EXTI0 << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL))) >> ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL));
593 #else
594 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT));
595 #endif
596 }
597
598 /**
599 * @brief Start a hardware SRAM2 erase operation.
600 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase\n
601 * @note This operation can be done only once SRAM2 page write protection unlocked
602 * @retval None
603 */
LL_SYSCFG_EnableSRAM2Erase(void)604 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
605 {
606 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
607 }
608
609 /**
610 * @brief Check if SRAM1 or SRAM2 is busy by erase operation
611 * @rmtoll SYSCFG_SCSR SRAMBSY LL_SYSCFG_IsSRAMEraseOngoing
612 * @retval State of bit (1 or 0).
613 */
LL_SYSCFG_IsSRAMEraseOngoing(void)614 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAMEraseOngoing(void)
615 {
616 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAMBSY) == (SYSCFG_SCSR_SRAMBSY)) ? 1UL : 0UL);
617 }
618
619 /**
620 * @brief Check if PKA SRAMis busy by erase operation
621 * @rmtoll SYSCFG_SCSR PKASRAMBSY LL_SYSCFG_IsPKASRAMEraseOngoing
622 * @retval State of bit (1 or 0).
623 */
LL_SYSCFG_IsPKASRAMEraseOngoing(void)624 __STATIC_INLINE uint32_t LL_SYSCFG_IsPKASRAMEraseOngoing(void)
625 {
626 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_PKASRAMBSY) == (SYSCFG_SCSR_PKASRAMBSY)) ? 1UL : 0UL);
627 }
628
629 /**
630 * @brief Set connections to TIM1/16/17 Break inputs
631 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
632 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
633 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
634 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
635 * @param Break This parameter can be a combination of the following values:
636 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
637 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
638 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
639 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
640 * @retval None
641 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)642 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
643 {
644 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
645 }
646
647 /**
648 * @brief Get connections to TIM1/16/17 Break inputs
649 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
650 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
651 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
652 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
653 * @retval Returned value can be can be a combination of the following values:
654 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
655 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
656 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
657 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
658 */
LL_SYSCFG_GetTIMBreakInputs(void)659 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
660 {
661 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
662 }
663
664 /**
665 * @brief Check if SRAM2 parity error detected
666 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
667 * @retval State of bit (1 or 0).
668 */
LL_SYSCFG_IsActiveFlag_SP(void)669 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
670 {
671 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
672 }
673
674 /**
675 * @brief Clear SRAM2 parity error flag
676 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
677 * @retval None
678 */
LL_SYSCFG_ClearFlag_SP(void)679 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
680 {
681 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
682 }
683
684 /**
685 * @brief Enable SRAM2 page write protection for Pages in range 0 to 31
686 * @note Write protection is cleared only by a system reset
687 * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
688 * @param SRAM2WRP This parameter can be a combination of the following values:
689 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
690 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
691 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
692 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
693 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
694 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
695 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
696 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
697 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
698 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
699 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
700 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
701 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
702 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
703 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
704 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
705 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16
706 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17
707 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18
708 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19
709 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20
710 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21
711 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22
712 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23
713 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24
714 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25
715 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26
716 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27
717 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28
718 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29
719 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30
720 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31
721 * @retval None
722 */
723 /* Legacy define */
724 #define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)725 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
726 {
727 SET_BIT(SYSCFG->SWPR, SRAM2WRP);
728 }
729
730
731 /**
732 * @brief SRAM2 page write protection lock prior to erase
733 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
734 * @retval None
735 */
LL_SYSCFG_LockSRAM2WRP(void)736 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
737 {
738 /* Writing a wrong key reactivates the write protection */
739 WRITE_REG(SYSCFG->SKR, 0x00U);
740 }
741
742 /**
743 * @brief SRAM2 page write protection unlock prior to erase
744 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
745 * @retval None
746 */
LL_SYSCFG_UnlockSRAM2WRP(void)747 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
748 {
749 /* unlock the write protection of the SRAM2ER bit */
750 WRITE_REG(SYSCFG->SKR, 0xCAU);
751 WRITE_REG(SYSCFG->SKR, 0x53U);
752 }
753
754 #if defined(DUAL_CORE)
755 /**
756 * @brief Enable CPU1 Interrupt Mask
757 * @rmtoll SYSCFG_IMR1 RTCSTAMPTAMPLSECSS1IM LL_SYSCFG_GRP1_EnableIT\n
758 * SYSCFG_IMR1 RTCSSRUIM LL_SYSCFG_GRP1_EnableIT\n
759 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_EnableIT
760 * @param Interrupt This parameter can be a combination of the following values:
761 * @arg @ref LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS
762 * @arg @ref LL_SYSCFG_GRP1_RTCSSRU
763 * @arg @ref LL_SYSCFG_GRP1_EXTI5
764 * @arg @ref LL_SYSCFG_GRP1_EXTI6
765 * @arg @ref LL_SYSCFG_GRP1_EXTI7
766 * @arg @ref LL_SYSCFG_GRP1_EXTI8
767 * @arg @ref LL_SYSCFG_GRP1_EXTI9
768 * @arg @ref LL_SYSCFG_GRP1_EXTI10
769 * @arg @ref LL_SYSCFG_GRP1_EXTI11
770 * @arg @ref LL_SYSCFG_GRP1_EXTI12
771 * @arg @ref LL_SYSCFG_GRP1_EXTI13
772 * @arg @ref LL_SYSCFG_GRP1_EXTI14
773 * @arg @ref LL_SYSCFG_GRP1_EXTI15
774 * @retval None
775 */
LL_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)776 __STATIC_INLINE void LL_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)
777 {
778 CLEAR_BIT(SYSCFG->IMR1, Interrupt);
779 }
780
781 /**
782 * @brief Enable CPU1 Interrupt Mask
783 * @rmtoll SYSCFG_IMR1 PVM3IM LL_SYSCFG_GRP2_EnableIT\n
784 * SYSCFG_IMR1 PVDIM LL_SYSCFG_GRP2_EnableIT
785 * @param Interrupt This parameter can be a combination of the following values:
786 * @arg @ref LL_SYSCFG_GRP2_PVM3
787 * @arg @ref LL_SYSCFG_GRP2_PVD
788 * @retval None
789 */
LL_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)790 __STATIC_INLINE void LL_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)
791 {
792 CLEAR_BIT(SYSCFG->IMR2, Interrupt);
793 }
794
795 /**
796 * @brief Disable CPU1 Interrupt Mask
797 * @rmtoll SYSCFG_IMR1 RTCSTAMPTAMPLSECSS1IM LL_SYSCFG_GRP1_DisableIT\n
798 * SYSCFG_IMR1 RTCSSRUIM LL_SYSCFG_GRP1_DisableIT\n
799 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_DisableIT
800 * @param Interrupt This parameter can be a combination of the following values:
801 * @arg @ref LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS
802 * @arg @ref LL_SYSCFG_GRP1_RTCSSRU
803 * @arg @ref LL_SYSCFG_GRP1_EXTI5
804 * @arg @ref LL_SYSCFG_GRP1_EXTI6
805 * @arg @ref LL_SYSCFG_GRP1_EXTI7
806 * @arg @ref LL_SYSCFG_GRP1_EXTI8
807 * @arg @ref LL_SYSCFG_GRP1_EXTI9
808 * @arg @ref LL_SYSCFG_GRP1_EXTI10
809 * @arg @ref LL_SYSCFG_GRP1_EXTI11
810 * @arg @ref LL_SYSCFG_GRP1_EXTI12
811 * @arg @ref LL_SYSCFG_GRP1_EXTI13
812 * @arg @ref LL_SYSCFG_GRP1_EXTI14
813 * @arg @ref LL_SYSCFG_GRP1_EXTI15
814 * @retval None
815 */
LL_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)816 __STATIC_INLINE void LL_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)
817 {
818 SET_BIT(SYSCFG->IMR1, Interrupt);
819 }
820
821 /**
822 * @brief Disable CPU1 Interrupt Mask
823 * @rmtoll SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_DisableIT\n
824 * SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_DisableIT
825 * @param Interrupt This parameter can be a combination of the following values:
826 * @arg @ref LL_SYSCFG_GRP2_PVM3
827 * @arg @ref LL_SYSCFG_GRP2_PVD
828 * @retval None
829 */
LL_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)830 __STATIC_INLINE void LL_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)
831 {
832 SET_BIT(SYSCFG->IMR2, Interrupt);
833 }
834
835 /**
836 * @brief Indicate if CPU1 Interrupt Mask is enabled
837 * @rmtoll SYSCFG_IMR1 RTCSTAMPTAMPLSECSS1IM LL_SYSCFG_GRP1_IsEnabledIT\n
838 * SYSCFG_IMR1 RTCSSRUIM LL_SYSCFG_GRP1_IsEnabledIT\n
839 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_IsEnabledIT
840 * @param Interrupt This parameter can be one of the following values:
841 * @arg @ref LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS
842 * @arg @ref LL_SYSCFG_GRP1_RTCSSRU
843 * @arg @ref LL_SYSCFG_GRP1_EXTI5
844 * @arg @ref LL_SYSCFG_GRP1_EXTI6
845 * @arg @ref LL_SYSCFG_GRP1_EXTI7
846 * @arg @ref LL_SYSCFG_GRP1_EXTI8
847 * @arg @ref LL_SYSCFG_GRP1_EXTI9
848 * @arg @ref LL_SYSCFG_GRP1_EXTI10
849 * @arg @ref LL_SYSCFG_GRP1_EXTI11
850 * @arg @ref LL_SYSCFG_GRP1_EXTI12
851 * @arg @ref LL_SYSCFG_GRP1_EXTI13
852 * @arg @ref LL_SYSCFG_GRP1_EXTI14
853 * @arg @ref LL_SYSCFG_GRP1_EXTI15
854 * @retval State of bit (1 or 0).
855 */
LL_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)856 __STATIC_INLINE uint32_t LL_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)
857 {
858 return ((READ_BIT(SYSCFG->IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL);
859 }
860
861 /**
862 * @brief Indicate if CPU1 Interrupt Mask is enabled
863 * @rmtoll SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_IsEnabledIT\n
864 * SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_IsEnabledIT
865 * @param Interrupt This parameter can be one of the following values:
866 * @arg @ref LL_SYSCFG_GRP2_PVM3
867 * @arg @ref LL_SYSCFG_GRP2_PVD
868 * @retval State of bit (1 or 0).
869 */
LL_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)870 __STATIC_INLINE uint32_t LL_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)
871 {
872 return ((READ_BIT(SYSCFG->IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL);
873 }
874
875 /**
876 * @brief Enable CPU2 Interrupt Mask
877 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_EnableIT\n
878 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_EnableIT\n
879 * SYSCFG_C2IMR1 RTCSSRUIM LL_C2_SYSCFG_GRP1_EnableIT\n
880 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_EnableIT\n
881 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_EnableIT\n
882 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_EnableIT\n
883 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_EnableIT\n
884 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_EnableIT\n
885 * SYSCFG_C2IMR1 AESIM LL_C2_SYSCFG_GRP1_EnableIT\n
886 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_EnableIT\n
887 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_EnableIT\n
888 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_EnableIT
889 * @param Interrupt This parameter can be a combination of the following values:
890 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
891 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
892 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSSRU
893 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
894 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
895 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
896 * @arg @ref LL_C2_SYSCFG_GRP1_PKA
897 * @arg @ref LL_C2_SYSCFG_GRP1_AES
898 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
899 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
900 * @arg @ref LL_C2_SYSCFG_GRP1_DAC
901 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
902 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
903 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
904 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
905 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
906 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
907 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
908 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
909 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
910 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
911 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
912 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
913 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
914 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
915 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
916 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
917 * @retval None
918 */
LL_C2_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)919 __STATIC_INLINE void LL_C2_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)
920 {
921 CLEAR_BIT(SYSCFG->C2IMR1, Interrupt);
922 }
923
924 /**
925 * @brief Enable CPU2 Interrupt Mask
926 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_EnableIT\n
927 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_EnableIT\n
928 * SYSCFG_C2IMR2 DMAMUX1IM LL_C2_SYSCFG_GRP2_EnableIT\n
929 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_EnableIT\n
930 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_EnableIT
931 * @param Interrupt This parameter can be a combination of the following values:
932 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
933 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
934 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
935 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
936 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
937 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
938 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
939 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
940 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
941 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
942 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
943 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
944 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
945 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
946 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
947 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
948 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
949 * @retval None
950 */
LL_C2_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)951 __STATIC_INLINE void LL_C2_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)
952 {
953 CLEAR_BIT(SYSCFG->C2IMR2, Interrupt);
954 }
955
956 /**
957 * @brief Disable CPU2 Interrupt Mask
958 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSS LL_C2_SYSCFG_GRP1_DisableIT\n
959 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_DisableIT\n
960 * SYSCFG_C2IMR1 RTCSSRUIM LL_C2_SYSCFG_GRP1_DisableIT\n
961 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_DisableIT\n
962 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_DisableIT\n
963 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_DisableIT\n
964 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_DisableIT\n
965 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_DisableIT\n
966 * SYSCFG_C2IMR1 AESIM LL_C2_SYSCFG_GRP1_DisableIT\n
967 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_DisableIT\n
968 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_DisableIT\n
969 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_DisableIT
970 * @param Interrupt This parameter can be a combination of the following values:
971 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
972 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
973 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSSRU
974 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
975 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
976 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
977 * @arg @ref LL_C2_SYSCFG_GRP1_AES
978 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
979 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
980 * @arg @ref LL_C2_SYSCFG_GRP1_DAC
981 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
982 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
983 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
984 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
985 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
986 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
987 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
988 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
989 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
990 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
991 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
992 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
993 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
994 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
995 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
996 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
997 * @retval None
998 */
LL_C2_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)999 __STATIC_INLINE void LL_C2_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)
1000 {
1001 SET_BIT(SYSCFG->C2IMR1, Interrupt);
1002 }
1003
1004 /**
1005 * @brief Disable CPU2 Interrupt Mask
1006 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_DisableIT\n
1007 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_DisableIT\n
1008 * SYSCFG_C2IMR2 DMAMUX1IM LL_C2_SYSCFG_GRP2_DisableIT\n
1009 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_DisableIT\n
1010 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_DisableIT
1011 * @param Interrupt This parameter can be a combination of the following values:
1012 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
1013 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
1014 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
1015 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
1016 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
1017 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
1018 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
1019 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
1020 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
1021 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
1022 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
1023 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
1024 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
1025 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
1026 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
1027 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
1028 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
1029 * @retval None
1030 */
LL_C2_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)1031 __STATIC_INLINE void LL_C2_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)
1032 {
1033 SET_BIT(SYSCFG->C2IMR2, Interrupt);
1034 }
1035
1036 /**
1037 * @brief Indicate if CPU2 Interrupt Mask is enabled
1038 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSS LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1039 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1040 * SYSCFG_C2IMR1 RTCSSRUIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1041 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1042 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1043 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1044 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1045 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1046 * SYSCFG_C2IMR1 AESIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1047 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1048 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1049 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_IsEnabledIT
1050 * @param Interrupt This parameter can be a combination of the following values:
1051 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
1052 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
1053 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSSRU
1054 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
1055 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
1056 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
1057 * @arg @ref LL_C2_SYSCFG_GRP1_PKA
1058 * @arg @ref LL_C2_SYSCFG_GRP1_AES
1059 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
1060 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
1061 * @arg @ref LL_C2_SYSCFG_GRP1_DAC
1062 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
1063 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
1064 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
1065 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
1066 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
1067 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
1068 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
1069 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
1070 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
1071 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
1072 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
1073 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
1074 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
1075 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
1076 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
1077 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
1078 * @retval State of bit (1 or 0).
1079 */
LL_C2_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)1080 __STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)
1081 {
1082 return ((READ_BIT(SYSCFG->C2IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1083 }
1084
1085 /**
1086 * @brief Indicate if CPU2 Interrupt Mask is enabled
1087 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1088 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1089 * SYSCFG_C2IMR2 DMAMUX1IM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1090 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1091 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_IsEnabledIT
1092 * @param Interrupt This parameter can be a combination of the following values:
1093 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
1094 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
1095 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
1096 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
1097 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
1098 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
1099 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
1100 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
1101 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
1102 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
1103 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
1104 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
1105 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
1106 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
1107 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
1108 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
1109 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
1110 * @retval State of bit (1 or 0).
1111 */
LL_C2_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)1112 __STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)
1113 {
1114 return ((READ_BIT(SYSCFG->C2IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1115 }
1116 #endif /* DUAL_CORE */
1117
1118 /**
1119 * @brief Set radio debug test bus type, analog or digital
1120 * @rmtoll SYSCFG_RFDR RFTBSEL LL_SYSCFG_SetRadioDebugTestBus
1121 * @param RadioDebugTestBus This parameter can be one of the following values:
1122 * @arg @ref LL_SYSCFG_ANALOG_TEST_BUS
1123 * @arg @ref LL_SYSCFG_DIGITAL_TEST_BUS
1124 * @retval None
1125 */
LL_SYSCFG_SetRadioDebugTestBus(uint32_t RadioDebugTestBus)1126 __STATIC_INLINE void LL_SYSCFG_SetRadioDebugTestBus(uint32_t RadioDebugTestBus)
1127 {
1128 MODIFY_REG(SYSCFG->RFDCR, SYSCFG_RFDCR_RFTBSEL, RadioDebugTestBus);
1129 }
1130
1131 /**
1132 * @brief Get radio debug test bus type, analog or digital
1133 * @rmtoll SYSCFG_RFDR RFTBSEL LL_SYSCFG_GetRadioDebugTestBus
1134 * @retval Returned value can be one of the following values:
1135 * @arg @ref LL_SYSCFG_ANALOG_TEST_BUS
1136 * @arg @ref LL_SYSCFG_DIGITAL_TEST_BUS
1137 */
LL_SYSCFG_GetRadioDebugTestBus(void)1138 __STATIC_INLINE uint32_t LL_SYSCFG_GetRadioDebugTestBus(void)
1139 {
1140 return (uint32_t)(READ_BIT(SYSCFG->RFDCR, SYSCFG_RFDCR_RFTBSEL));
1141 }
1142 /**
1143 * @}
1144 */
1145
1146 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1147 * @note DBGMCU is only accessible by Cortex M4
1148 * To access on DBGMCU, Cortex M0+ need to request to the Cortex M4
1149 * the action.
1150 * @{
1151 */
1152
1153 #if defined(CORE_CM0PLUS)
1154 #else
1155 /**
1156 * @brief Return the device identifier
1157 * @note For STM32WLxxxx devices, the device ID is 0x497
1158 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1159 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x497)
1160 */
LL_DBGMCU_GetDeviceID(void)1161 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1162 {
1163 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1164 }
1165
1166 /**
1167 * @brief Return the device revision identifier
1168 * @note This field indicates the revision of the device.
1169 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1170 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1171 */
LL_DBGMCU_GetRevisionID(void)1172 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1173 {
1174 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1175 }
1176
1177 /**
1178 * @brief Enable the CPU1 Debug Module during SLEEP mode
1179 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1180 * @retval None
1181 */
LL_DBGMCU_EnableDBGSleepMode(void)1182 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1183 {
1184 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1185 }
1186
1187 /**
1188 * @brief Disable the CPU1 Debug Module during SLEEP mode
1189 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1190 * @retval None
1191 */
LL_DBGMCU_DisableDBGSleepMode(void)1192 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1193 {
1194 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1195 }
1196
1197 /**
1198 * @brief Enable the Debug Module during STOP mode
1199 * @note This bit does not influence CPU2 operation, CPU2 cannot be debugged
1200 * in Stop mode even when this bit is enabled
1201 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1202 * @retval None
1203 */
LL_DBGMCU_EnableDBGStopMode(void)1204 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1205 {
1206 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1207 }
1208
1209 /**
1210 * @brief Disable the Debug Module during STOP mode
1211 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1212 * @retval None
1213 */
LL_DBGMCU_DisableDBGStopMode(void)1214 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1215 {
1216 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1217 }
1218
1219 /**
1220 * @brief Enable the Debug Module during STANDBY mode
1221 * @note This bit does not influence CPU2 operation, CPU2 cannot be debugged
1222 * in Standby mode even when this bit is enabled
1223 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1224 * @retval None
1225 */
LL_DBGMCU_EnableDBGStandbyMode(void)1226 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1227 {
1228 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1229 }
1230
1231 /**
1232 * @brief Disable the Debug Module during STANDBY mode
1233 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1234 * @retval None
1235 */
LL_DBGMCU_DisableDBGStandbyMode(void)1236 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1237 {
1238 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1239 }
1240
1241 /**
1242 * @brief Freeze CPU1 APB1 peripherals (group1 peripherals)
1243 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1244 * @param Periphs This parameter can be a combination of the following values:
1245 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1246 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1247 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1248 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1249 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1250 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1251 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1252 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1253 * @retval None
1254 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1255 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1256 {
1257 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1258 }
1259
1260 #if defined(DUAL_CORE)
1261 /**
1262 * @brief Freeze CPU2 APB1 peripherals (group1 peripherals)
1263 * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_FreezePeriph
1264 * @param Periphs This parameter can be a combination of the following values:
1265 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
1266 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
1267 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
1268 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
1269 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP
1270 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
1271 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
1272 * @retval None
1273 */
LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1274 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1275 {
1276 SET_BIT(DBGMCU->C2APB1FZR1, Periphs);
1277 }
1278 #endif /* DUAL_CORE */
1279
1280 /**
1281 * @brief Freeze CPU1 APB1 peripherals (group2 peripherals)
1282 * @rmtoll DBGMCU_APB1FZR2 LL_DBGMCU_APB1_GRP2_LPTIM2_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1283 * DBGMCU_APB1FZR2 LL_DBGMCU_APB1_GRP2_LPTIM3_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1284 * @param Periphs This parameter can be a combination of the following values:
1285 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1286 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM3_STOP
1287 * @retval None
1288 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1289 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1290 {
1291 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1292 }
1293
1294 #if defined(DUAL_CORE)
1295 /**
1296 * @brief Freeze CPU2 APB1 peripherals (group2 peripherals)
1297 * @rmtoll DBGMCU_APB1FZR2 LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP LL_C2_DBGMCU_APB1_GRP2_FreezePeriph
1298 * DBGMCU_APB1FZR2 LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP LL_C2_DBGMCU_APB1_GRP2_FreezePeriph
1299 * @param Periphs This parameter can be a combination of the following values:
1300 * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
1301 * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP
1302 * @retval None
1303 */
LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1304 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1305 {
1306 SET_BIT(DBGMCU->C2APB1FZR2, Periphs);
1307 }
1308 #endif /* DUAL_CORE */
1309
1310 /**
1311 * @brief Unfreeze CPU1 APB1 peripherals (group1 peripherals)
1312 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1313 * @param Periphs This parameter can be a combination of the following values:
1314 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1315 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1316 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1317 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1318 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1319 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1320 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1321 * @retval None
1322 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1323 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1324 {
1325 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1326 }
1327
1328 #if defined(DUAL_CORE)
1329 /**
1330 * @brief Unfreeze CPU2 APB1 peripherals (group1 peripherals)
1331 * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph
1332 * @param Periphs This parameter can be a combination of the following values:
1333 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
1334 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
1335 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
1336 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
1337 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
1338 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
1339 * @retval None
1340 */
LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1341 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1342 {
1343 CLEAR_BIT(DBGMCU->C2APB1FZR1, Periphs);
1344 }
1345 #endif /* DUAL_CORE */
1346
1347 /**
1348 * @brief Unfreeze CPU1 APB1 peripherals (group2 peripherals)
1349 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1350 * @param Periphs This parameter can be a combination of the following values:
1351 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1352 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM3_STOP
1353 * @retval None
1354 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1355 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1356 {
1357 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1358 }
1359
1360 #if defined(DUAL_CORE)
1361 /**
1362 * @brief Unfreeze CPU2 APB1 peripherals (group2 peripherals)
1363 * @rmtoll DBGMCU_C2APB1FZR2 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph
1364 * @param Periphs This parameter can be a combination of the following values:
1365 * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
1366 * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP
1367 * @retval None
1368 */
LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1369 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1370 {
1371 CLEAR_BIT(DBGMCU->C2APB1FZR2, Periphs);
1372 }
1373 #endif /* DUAL_CORE */
1374
1375 /**
1376 * @brief Freeze CPU1 APB2 peripherals
1377 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1378 * @param Periphs This parameter can be a combination of the following values:
1379 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1380 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1381 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1382 * @retval None
1383 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1384 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1385 {
1386 SET_BIT(DBGMCU->APB2FZR, Periphs);
1387 }
1388
1389 #if defined(DUAL_CORE)
1390 /**
1391 * @brief Freeze CPU2 APB2 peripherals
1392 * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_FreezePeriph
1393 * @param Periphs This parameter can be a combination of the following values:
1394 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
1395 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
1396 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
1397 * @retval None
1398 */
LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1399 __STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1400 {
1401 SET_BIT(DBGMCU->C2APB2FZR, Periphs);
1402 }
1403 #endif /* DUAL_CORE */
1404
1405 /**
1406 * @brief Unfreeze CPU1 APB2 peripherals
1407 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1408 * @param Periphs This parameter can be a combination of the following values:
1409 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1410 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1411 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1412 * @retval None
1413 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1414 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1415 {
1416 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1417 }
1418
1419 #if defined(DUAL_CORE)
1420 /**
1421 * @brief Unfreeze CPU2 APB2 peripherals
1422 * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph
1423 * @param Periphs This parameter can be a combination of the following values:
1424 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
1425 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
1426 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
1427 * @retval None
1428 */
LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1429 __STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1430 {
1431 CLEAR_BIT(DBGMCU->C2APB2FZR, Periphs);
1432 }
1433 #endif /* DUAL_CORE */
1434
1435 #endif
1436 /**
1437 * @}
1438 */
1439
1440 #if defined(VREFBUF)
1441 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1442 * @{
1443 */
1444
1445 /**
1446 * @brief Enable Internal voltage reference
1447 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1448 * @retval None
1449 */
LL_VREFBUF_Enable(void)1450 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1451 {
1452 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1453 }
1454
1455 /**
1456 * @brief Disable Internal voltage reference
1457 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1458 * @retval None
1459 */
LL_VREFBUF_Disable(void)1460 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1461 {
1462 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1463 }
1464
1465 /**
1466 * @brief Enable high impedance (VREF+pin is high impedance)
1467 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1468 * @retval None
1469 */
LL_VREFBUF_EnableHIZ(void)1470 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1471 {
1472 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1473 }
1474
1475 /**
1476 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1477 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1478 * @retval None
1479 */
LL_VREFBUF_DisableHIZ(void)1480 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1481 {
1482 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1483 }
1484
1485 /**
1486 * @brief Set the Voltage reference scale
1487 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1488 * @param Scale This parameter can be one of the following values:
1489 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1490 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1491 * @retval None
1492 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1493 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1494 {
1495 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1496 }
1497
1498 /**
1499 * @brief Get the Voltage reference scale
1500 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1501 * @retval Returned value can be one of the following values:
1502 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1503 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1504 */
LL_VREFBUF_GetVoltageScaling(void)1505 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1506 {
1507 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1508 }
1509
1510 /**
1511 * @brief Get the VREFBUF trimming value for VRS=0 (VREF_SC0)
1512 * @retval Between 0 and 0x3F
1513 */
LL_VREFBUF_SC0_GetCalibration(void)1514 __STATIC_INLINE uint32_t LL_VREFBUF_SC0_GetCalibration(void)
1515 {
1516 return (uint32_t)(*VREFBUF_SC0_CAL_ADDR);
1517 }
1518
1519 /**
1520 * @brief Get the VREFBUF trimming value for VRS=1 (VREF_SC1)
1521 * @retval Between 0 and 0x3F
1522 */
LL_VREFBUF_SC1_GetCalibration(void)1523 __STATIC_INLINE uint32_t LL_VREFBUF_SC1_GetCalibration(void)
1524 {
1525 return (uint32_t)(*VREFBUF_SC1_CAL_ADDR);
1526 }
1527
1528 /**
1529 * @brief Check if Voltage reference buffer is ready
1530 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1531 * @retval State of bit (1 or 0).
1532 */
LL_VREFBUF_IsVREFReady(void)1533 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1534 {
1535 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
1536 }
1537
1538 /**
1539 * @brief Get the trimming code for VREFBUF calibration
1540 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1541 * @retval Between 0 and 0x3F
1542 */
LL_VREFBUF_GetTrimming(void)1543 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1544 {
1545 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1546 }
1547
1548 /**
1549 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1550 * @note Each VrefBuf voltage scale is calibrated in production for each device,
1551 * data stored in flash memory.
1552 * Functions @ref LL_VREFBUF_SC0_GetCalibration and
1553 * @ref LL_VREFBUF_SC0_GetCalibration can be used to retrieve
1554 * these calibration data.
1555 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1556 * @param Value Between 0 and 0x3F
1557 * @retval None
1558 */
LL_VREFBUF_SetTrimming(uint32_t Value)1559 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1560 {
1561 WRITE_REG(VREFBUF->CCR, Value);
1562 }
1563
1564 /**
1565 * @}
1566 */
1567 #endif /* VREFBUF */
1568
1569 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1570 * @{
1571 */
1572
1573 /**
1574 * @brief Set FLASH Latency
1575 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1576 * @param Latency This parameter can be one of the following values:
1577 * @arg @ref LL_FLASH_LATENCY_0
1578 * @arg @ref LL_FLASH_LATENCY_1
1579 * @arg @ref LL_FLASH_LATENCY_2
1580 * @retval None
1581 */
LL_FLASH_SetLatency(uint32_t Latency)1582 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1583 {
1584 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1585 }
1586
1587 /**
1588 * @brief Get FLASH Latency
1589 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1590 * @retval Returned value can be one of the following values:
1591 * @arg @ref LL_FLASH_LATENCY_0
1592 * @arg @ref LL_FLASH_LATENCY_1
1593 * @arg @ref LL_FLASH_LATENCY_2
1594 */
LL_FLASH_GetLatency(void)1595 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1596 {
1597 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1598 }
1599
1600 /**
1601 * @brief Enable Prefetch
1602 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1603 * @retval None
1604 */
LL_FLASH_EnablePrefetch(void)1605 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1606 {
1607 #if defined(CORE_CM0PLUS)
1608 SET_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN);
1609 #else
1610 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1611 #endif
1612 }
1613
1614 /**
1615 * @brief Disable Prefetch
1616 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1617 * @rmtoll FLASH_C2ACR PRFTEN LL_FLASH_DisablePrefetch
1618 * @retval None
1619 */
LL_FLASH_DisablePrefetch(void)1620 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1621 {
1622 #if defined(CORE_CM0PLUS)
1623 CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN);
1624 #else
1625 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1626 #endif
1627 }
1628
1629 /**
1630 * @brief Check if Prefetch buffer is enabled
1631 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1632 * @rmtoll FLASH_C2ACR C2PRFTEN LL_FLASH_IsPrefetchEnabled
1633 * @retval State of bit (1 or 0).
1634 */
LL_FLASH_IsPrefetchEnabled(void)1635 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1636 {
1637 #if defined(CORE_CM0PLUS)
1638 return ((READ_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN) == (FLASH_C2ACR_PRFTEN)) ? 1UL : 0UL);
1639 #else
1640 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
1641 #endif
1642 }
1643
1644 /**
1645 * @brief Enable Instruction cache
1646 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1647 * @rmtoll FLASH_C2ACR ICEN LL_FLASH_EnableInstCache
1648 * @retval None
1649 */
LL_FLASH_EnableInstCache(void)1650 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1651 {
1652 #if defined(CORE_CM0PLUS)
1653 SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN);
1654 #else
1655 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1656 #endif
1657 }
1658
1659 /**
1660 * @brief Disable Instruction cache
1661 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1662 * @rmtoll FLASH_C2ACR ICEN LL_FLASH_DisableInstCache
1663 * @retval None
1664 */
LL_FLASH_DisableInstCache(void)1665 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1666 {
1667 #if defined(CORE_CM0PLUS)
1668 CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN);
1669 #else
1670 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1671 #endif
1672 }
1673
1674 #if defined(CORE_CM0PLUS)
1675 #else
1676 /**
1677 * @brief Enable Data cache
1678 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
1679 * @retval None
1680 */
LL_FLASH_EnableDataCache(void)1681 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1682 {
1683 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1684 }
1685
1686 /**
1687 * @brief Disable Data cache
1688 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
1689 * @retval None
1690 */
LL_FLASH_DisableDataCache(void)1691 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1692 {
1693 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1694 }
1695 #endif
1696
1697 /**
1698 * @brief Enable Instruction cache reset
1699 * @note bit can be written only when the instruction cache is disabled
1700 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
1701 * @rmtoll FLASH_C2ACR ICRST LL_FLASH_EnableInstCacheReset
1702 * @retval None
1703 */
LL_FLASH_EnableInstCacheReset(void)1704 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1705 {
1706 #if defined(CORE_CM0PLUS)
1707 SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST);
1708 #else
1709 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1710 #endif
1711 }
1712
1713 /**
1714 * @brief Disable Instruction cache reset
1715 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
1716 * @rmtoll FLASH_C2ACR ICRST LL_FLASH_DisableInstCacheReset
1717 * @retval None
1718 */
LL_FLASH_DisableInstCacheReset(void)1719 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1720 {
1721 #if defined(CORE_CM0PLUS)
1722 CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST);
1723 #else
1724 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1725 #endif
1726 }
1727
1728 #if defined(CORE_CM0PLUS)
1729 #else
1730 /**
1731 * @brief Enable Data cache reset
1732 * @note bit can be written only when the data cache is disabled
1733 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
1734 * @retval None
1735 */
LL_FLASH_EnableDataCacheReset(void)1736 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1737 {
1738 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1739 }
1740
1741 /**
1742 * @brief Disable Data cache reset
1743 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
1744 * @retval None
1745 */
LL_FLASH_DisableDataCacheReset(void)1746 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1747 {
1748 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1749 }
1750 #endif
1751
1752 /**
1753 * @brief Suspend new program or erase operation request
1754 * @note Any new Flash program and erase operation on both CPU side will be suspended
1755 * until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are
1756 * cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash
1757 * CPU2 status register (FLASH_C2SR) register will be set when at least one PES
1758 * bit in FLASH_ACR or FLASH_C2ACR is set.
1759 * @rmtoll FLASH_ACR PES LL_FLASH_SuspendOperation
1760 * @rmtoll FLASH_C2ACR PES LL_FLASH_SuspendOperation
1761 * @retval None
1762 */
LL_FLASH_SuspendOperation(void)1763 __STATIC_INLINE void LL_FLASH_SuspendOperation(void)
1764 {
1765 #if defined(CORE_CM0PLUS)
1766 SET_BIT(FLASH->C2ACR, FLASH_C2ACR_PES);
1767 #else
1768 SET_BIT(FLASH->ACR, FLASH_ACR_PES);
1769 #endif
1770 }
1771
1772 /**
1773 * @brief Allow new program or erase operation request
1774 * @note Any new Flash program and erase operation on both CPU side will be allowed
1775 * until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is
1776 * set. The PESD bit in both the Flash status register (FLASH_SR) and Flash
1777 * CPU2 status register (FLASH_C2SR) register will be clear when both PES
1778 * bit in FLASH_ACR or FLASH_C2ACR is cleared.
1779 * @rmtoll FLASH_ACR PES LL_FLASH_AllowOperation
1780 * @rmtoll FLASH_C2ACR PES LL_FLASH_AllowOperation
1781 * @retval None
1782 */
LL_FLASH_AllowOperation(void)1783 __STATIC_INLINE void LL_FLASH_AllowOperation(void)
1784 {
1785 #if defined(CORE_CM0PLUS)
1786 CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_PES);
1787 #else
1788 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PES);
1789 #endif
1790 }
1791
1792 /**
1793 * @brief Check if new program or erase operation request from CPU2 is suspended
1794 * @rmtoll FLASH_ACR PES LL_FLASH_IsOperationSuspended
1795 * @rmtoll FLASH_C2ACR PES LL_FLASH_IsOperationSuspended
1796 * @retval State of bit (1 or 0).
1797 */
LL_FLASH_IsOperationSuspended(void)1798 __STATIC_INLINE uint32_t LL_FLASH_IsOperationSuspended(void)
1799 {
1800 #if defined(CORE_CM0PLUS)
1801 return ((READ_BIT(FLASH->C2ACR, FLASH_C2ACR_PES) == (FLASH_C2ACR_PES)) ? 1UL : 0UL);
1802 #else
1803 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PES) == (FLASH_ACR_PES)) ? 1UL : 0UL);
1804 #endif
1805 }
1806
1807 /**
1808 * @brief Check if new program or erase operation request from CPU1 or CPU2 is suspended
1809 * @rmtoll FLASH_SR PESD LL_FLASH_IsActiveFlag_OperationSuspended
1810 * @rmtoll FLASH_C2SR PESD LL_FLASH_IsActiveFlag_OperationSuspended
1811 * @retval State of bit (1 or 0).
1812 */
LL_FLASH_IsActiveFlag_OperationSuspended(void)1813 __STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OperationSuspended(void)
1814 {
1815 #if defined(CORE_CM0PLUS)
1816 return ((READ_BIT(FLASH->C2SR, FLASH_C2SR_PESD) == (FLASH_C2SR_PESD)) ? 1UL : 0UL);
1817 #else
1818 return ((READ_BIT(FLASH->SR, FLASH_SR_PESD) == (FLASH_SR_PESD)) ? 1UL : 0UL);
1819 #endif
1820 }
1821
1822 /**
1823 * @brief Set EMPTY flag information as Flash User area empty
1824 * @rmtoll FLASH_ACR EMPTY LL_FLASH_SetEmptyFlag
1825 * @retval None
1826 */
LL_FLASH_SetEmptyFlag(void)1827 __STATIC_INLINE void LL_FLASH_SetEmptyFlag(void)
1828 {
1829 SET_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
1830 }
1831
1832 /**
1833 * @brief Clear EMPTY flag information as Flash User area programmed
1834 * @rmtoll FLASH_ACR EMPTY LL_FLASH_ClearEmptyFlag
1835 * @retval None
1836 */
LL_FLASH_ClearEmptyFlag(void)1837 __STATIC_INLINE void LL_FLASH_ClearEmptyFlag(void)
1838 {
1839 CLEAR_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
1840 }
1841
1842 /**
1843 * @brief Check if the EMPTY flag is set or reset
1844 * @rmtoll FLASH_ACR EMPTY LL_FLASH_IsEmptyFlag
1845 * @retval State of bit (1 or 0).
1846 */
LL_FLASH_IsEmptyFlag(void)1847 __STATIC_INLINE uint32_t LL_FLASH_IsEmptyFlag(void)
1848 {
1849 return ((READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY) == FLASH_ACR_EMPTY) ? 1UL : 0UL);
1850 }
1851
1852 #if defined(DUAL_CORE)
1853 /**
1854 * @brief Get IPCC buffer base address
1855 * @rmtoll FLASH_IPCCBR IPCCDBA LL_FLASH_GetIPCCBufferAddr
1856 * @retval IPCC data buffer base address offset
1857 */
LL_FLASH_GetIPCCBufferAddr(void)1858 __STATIC_INLINE uint32_t LL_FLASH_GetIPCCBufferAddr(void)
1859 {
1860 return (uint32_t)(READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA));
1861 }
1862 #endif /* DUAL_CORE */
1863
1864 #if defined(DUAL_CORE)
1865 /**
1866 * @brief Get CPU2 boot reset vector
1867 * @rmtoll FLASH_SRRVR SBRV LL_FLASH_GetC2BootResetVect
1868 * @retval CPU2 boot reset vector
1869 */
LL_FLASH_GetC2BootResetVect(void)1870 __STATIC_INLINE uint32_t LL_FLASH_GetC2BootResetVect(void)
1871 {
1872 return (uint32_t)(READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV));
1873 }
1874 #endif /* DUAL_CORE */
1875
1876 /**
1877 * @brief Return the Unique Device Number
1878 * @retval Values between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1879 */
LL_FLASH_GetUDN(void)1880 __STATIC_INLINE uint32_t LL_FLASH_GetUDN(void)
1881 {
1882 return (READ_REG(*((uint32_t *)UID64_BASE)));
1883 }
1884
1885 /**
1886 * @brief Return the Device ID
1887 * For STM32WLxxxx devices, the device ID is 0x15
1888 * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x15)
1889 */
LL_FLASH_GetDeviceID(void)1890 __STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void)
1891 {
1892 return ((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU);
1893 }
1894
1895 /**
1896 * @brief Return the ST Company ID
1897 * @note For STM32WLxxxx devices, the ST Company ID is 0x0080E1
1898 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Company ID is 0x0080E1)
1899 */
LL_FLASH_GetSTCompanyID(void)1900 __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void)
1901 {
1902 return (((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U) & 0x00FFFFFFU);
1903 }
1904 /**
1905 * @}
1906 */
1907
1908 /**
1909 * @}
1910 */
1911
1912 /**
1913 * @}
1914 */
1915
1916 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1917
1918 /**
1919 * @}
1920 */
1921
1922 #ifdef __cplusplus
1923 }
1924 #endif
1925
1926 #endif /* STM32WLxx_LL_SYSTEM_H */
1927
