1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef __STM32F1xx_LL_BUS_H
39 #define __STM32F1xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32f1xx.h"
47
48 /** @addtogroup STM32F1xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60
61 /* Private constants ---------------------------------------------------------*/
62 #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
63 #define RCC_AHBRSTR_SUPPORT
64 #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
65
66 /* Private macros ------------------------------------------------------------*/
67
68 /* Exported types ------------------------------------------------------------*/
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
71 * @{
72 */
73
74 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
75 * @{
76 */
77 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
78 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
79 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
80 #if defined(DMA2)
81 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
82 #endif /*DMA2*/
83 #if defined(ETH)
84 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
85 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
86 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
87 #endif /*ETH*/
88 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
89 #if defined(FSMC_Bank1)
90 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
91 #endif /*FSMC_Bank1*/
92 #if defined(USB_OTG_FS)
93 #define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
94 #endif /*USB_OTG_FS*/
95 #if defined(SDIO)
96 #define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
97 #endif /*SDIO*/
98 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
99 /**
100 * @}
101 */
102
103 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
104 * @{
105 */
106 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
107 #define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
108 #if defined(CAN1)
109 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
110 #endif /*CAN1*/
111 #if defined(CAN2)
112 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
113 #endif /*CAN2*/
114 #if defined(CEC)
115 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
116 #endif /*CEC*/
117 #if defined(DAC)
118 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
119 #endif /*DAC*/
120 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
121 #if defined(I2C2)
122 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
123 #endif /*I2C2*/
124 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
125 #if defined(SPI2)
126 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
127 #endif /*SPI2*/
128 #if defined(SPI3)
129 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
130 #endif /*SPI3*/
131 #if defined(TIM12)
132 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
133 #endif /*TIM12*/
134 #if defined(TIM13)
135 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
136 #endif /*TIM13*/
137 #if defined(TIM14)
138 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
139 #endif /*TIM14*/
140 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
141 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
142 #if defined(TIM4)
143 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
144 #endif /*TIM4*/
145 #if defined(TIM5)
146 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
147 #endif /*TIM5*/
148 #if defined(TIM6)
149 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
150 #endif /*TIM6*/
151 #if defined(TIM7)
152 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
153 #endif /*TIM7*/
154 #if defined(UART4)
155 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
156 #endif /*UART4*/
157 #if defined(UART5)
158 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
159 #endif /*UART5*/
160 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
161 #if defined(USART3)
162 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
163 #endif /*USART3*/
164 #if defined(USB)
165 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
166 #endif /*USB*/
167 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
168 /**
169 * @}
170 */
171
172 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
173 * @{
174 */
175 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
176 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
177 #if defined(ADC2)
178 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
179 #endif /*ADC2*/
180 #if defined(ADC3)
181 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
182 #endif /*ADC3*/
183 #define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
184 #define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
185 #define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
186 #define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
187 #define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
188 #if defined(GPIOE)
189 #define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
190 #endif /*GPIOE*/
191 #if defined(GPIOF)
192 #define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
193 #endif /*GPIOF*/
194 #if defined(GPIOG)
195 #define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
196 #endif /*GPIOG*/
197 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
198 #if defined(TIM10)
199 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
200 #endif /*TIM10*/
201 #if defined(TIM11)
202 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
203 #endif /*TIM11*/
204 #if defined(TIM15)
205 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
206 #endif /*TIM15*/
207 #if defined(TIM16)
208 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
209 #endif /*TIM16*/
210 #if defined(TIM17)
211 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
212 #endif /*TIM17*/
213 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
214 #if defined(TIM8)
215 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
216 #endif /*TIM8*/
217 #if defined(TIM9)
218 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
219 #endif /*TIM9*/
220 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
221 /**
222 * @}
223 */
224
225 /**
226 * @}
227 */
228
229 /* Exported macro ------------------------------------------------------------*/
230
231 /* Exported functions --------------------------------------------------------*/
232 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
233 * @{
234 */
235
236 /** @defgroup BUS_LL_EF_AHB1 AHB1
237 * @{
238 */
239
240 /**
241 * @brief Enable AHB1 peripherals clock.
242 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
243 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
244 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
245 * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
246 * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
247 * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
248 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
249 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
250 * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
251 * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
252 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
253 * @param Periphs This parameter can be a combination of the following values:
254 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
255 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
256 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
257 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
258 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
259 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
260 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
261 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
262 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
263 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
264 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
265 *
266 * (*) value not defined in all devices.
267 * @retval None
268 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)269 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
270 {
271 __IO uint32_t tmpreg;
272 SET_BIT(RCC->AHBENR, Periphs);
273 /* Delay after an RCC peripheral clock enabling */
274 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
275 (void)tmpreg;
276 }
277
278 /**
279 * @brief Check if AHB1 peripheral clock is enabled or not
280 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
281 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
282 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
283 * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
284 * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
285 * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
286 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
287 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
288 * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
289 * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
290 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
291 * @param Periphs This parameter can be a combination of the following values:
292 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
293 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
294 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
295 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
296 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
297 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
298 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
299 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
300 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
301 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
302 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
303 *
304 * (*) value not defined in all devices.
305 * @retval State of Periphs (1 or 0).
306 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)307 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
308 {
309 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
310 }
311
312 /**
313 * @brief Disable AHB1 peripherals clock.
314 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
315 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
316 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
317 * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
318 * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
319 * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
320 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
321 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
322 * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
323 * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
324 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
325 * @param Periphs This parameter can be a combination of the following values:
326 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
327 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
328 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
329 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
330 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
331 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
332 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
333 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
334 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
335 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
336 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
337 *
338 * (*) value not defined in all devices.
339 * @retval None
340 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)341 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
342 {
343 CLEAR_BIT(RCC->AHBENR, Periphs);
344 }
345
346 #if defined(RCC_AHBRSTR_SUPPORT)
347 /**
348 * @brief Force AHB1 peripherals reset.
349 * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
350 * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
351 * @param Periphs This parameter can be a combination of the following values:
352 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
353 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
354 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
355 *
356 * (*) value not defined in all devices.
357 * @retval None
358 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)359 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
360 {
361 SET_BIT(RCC->AHBRSTR, Periphs);
362 }
363
364 /**
365 * @brief Release AHB1 peripherals reset.
366 * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
367 * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
368 * @param Periphs This parameter can be a combination of the following values:
369 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
370 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
371 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
372 *
373 * (*) value not defined in all devices.
374 * @retval None
375 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)376 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
377 {
378 CLEAR_BIT(RCC->AHBRSTR, Periphs);
379 }
380 #endif /* RCC_AHBRSTR_SUPPORT */
381
382 /**
383 * @}
384 */
385
386 /** @defgroup BUS_LL_EF_APB1 APB1
387 * @{
388 */
389
390 /**
391 * @brief Enable APB1 peripherals clock.
392 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
393 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
394 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
395 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
396 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
397 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
398 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
399 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
400 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
401 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
402 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
403 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
404 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
405 * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
406 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
407 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
408 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
409 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
410 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
411 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
412 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
413 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
414 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
415 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
416 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
417 * @param Periphs This parameter can be a combination of the following values:
418 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
419 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
420 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
421 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
422 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
423 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
424 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
425 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
426 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
427 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
428 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
429 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
430 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
431 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
432 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
433 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
434 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
435 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
436 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
437 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
438 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
439 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
440 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
441 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
442 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
443 *
444 * (*) value not defined in all devices.
445 * @retval None
446 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)447 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
448 {
449 __IO uint32_t tmpreg;
450 SET_BIT(RCC->APB1ENR, Periphs);
451 /* Delay after an RCC peripheral clock enabling */
452 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
453 (void)tmpreg;
454 }
455
456 /**
457 * @brief Check if APB1 peripheral clock is enabled or not
458 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
459 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
460 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
461 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
462 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
463 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
464 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
465 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
466 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
467 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
468 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
469 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
470 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
471 * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
472 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
473 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
474 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
475 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
476 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
477 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
478 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
479 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
480 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
481 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
482 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
483 * @param Periphs This parameter can be a combination of the following values:
484 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
485 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
486 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
487 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
488 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
489 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
490 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
491 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
492 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
493 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
494 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
495 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
496 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
497 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
498 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
499 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
500 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
501 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
502 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
503 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
504 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
505 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
506 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
507 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
508 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
509 *
510 * (*) value not defined in all devices.
511 * @retval State of Periphs (1 or 0).
512 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)513 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
514 {
515 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
516 }
517
518 /**
519 * @brief Disable APB1 peripherals clock.
520 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
521 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
522 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
523 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
524 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
525 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
526 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
527 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
528 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
529 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
530 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
531 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
532 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
533 * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
534 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
535 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
536 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
537 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
538 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
539 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
540 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
541 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
542 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
543 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
544 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
545 * @param Periphs This parameter can be a combination of the following values:
546 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
547 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
548 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
549 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
550 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
551 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
552 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
553 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
554 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
555 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
556 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
557 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
558 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
559 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
560 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
561 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
562 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
563 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
564 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
565 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
566 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
567 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
568 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
569 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
570 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
571 *
572 * (*) value not defined in all devices.
573 * @retval None
574 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)575 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
576 {
577 CLEAR_BIT(RCC->APB1ENR, Periphs);
578 }
579
580 /**
581 * @brief Force APB1 peripherals reset.
582 * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
583 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
584 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
585 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
586 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
587 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
588 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
589 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
590 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
591 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
592 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
593 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
594 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
595 * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
596 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
597 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
598 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
599 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
600 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
601 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
602 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
603 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
604 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
605 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
606 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
607 * @param Periphs This parameter can be a combination of the following values:
608 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
609 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
610 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
611 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
612 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
613 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
614 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
615 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
616 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
617 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
618 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
622 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
623 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
624 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
625 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
626 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
627 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
628 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
629 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
630 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
631 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
632 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
633 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
634 *
635 * (*) value not defined in all devices.
636 * @retval None
637 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)638 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
639 {
640 SET_BIT(RCC->APB1RSTR, Periphs);
641 }
642
643 /**
644 * @brief Release APB1 peripherals reset.
645 * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
646 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
647 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
648 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
649 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
650 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
651 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
652 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
653 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
654 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
655 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
656 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
657 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
658 * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
659 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
660 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
661 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
662 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
663 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
664 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
665 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
666 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
667 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
668 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
669 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
670 * @param Periphs This parameter can be a combination of the following values:
671 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
672 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
673 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
674 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
675 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
676 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
677 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
678 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
679 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
680 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
681 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
682 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
683 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
684 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
685 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
686 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
687 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
688 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
689 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
690 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
691 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
692 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
693 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
694 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
695 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
696 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
697 *
698 * (*) value not defined in all devices.
699 * @retval None
700 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)701 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
702 {
703 CLEAR_BIT(RCC->APB1RSTR, Periphs);
704 }
705
706 /**
707 * @}
708 */
709
710 /** @defgroup BUS_LL_EF_APB2 APB2
711 * @{
712 */
713
714 /**
715 * @brief Enable APB2 peripherals clock.
716 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
717 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
718 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
719 * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
720 * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
721 * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
722 * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
723 * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
724 * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
725 * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
726 * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
727 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
728 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
729 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
730 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
731 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
732 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
733 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
734 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
735 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
736 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
737 * @param Periphs This parameter can be a combination of the following values:
738 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
739 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
740 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
741 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
742 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
743 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
744 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
745 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
746 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
747 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
748 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
749 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
750 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
751 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
752 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
753 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
754 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
755 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
756 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
757 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
758 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
759 *
760 * (*) value not defined in all devices.
761 * @retval None
762 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)763 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
764 {
765 __IO uint32_t tmpreg;
766 SET_BIT(RCC->APB2ENR, Periphs);
767 /* Delay after an RCC peripheral clock enabling */
768 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
769 (void)tmpreg;
770 }
771
772 /**
773 * @brief Check if APB2 peripheral clock is enabled or not
774 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
775 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
776 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
777 * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
778 * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
779 * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
780 * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
781 * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
782 * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
783 * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
784 * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
785 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
786 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
787 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
788 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
789 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
790 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
791 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
792 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
793 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
794 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
795 * @param Periphs This parameter can be a combination of the following values:
796 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
797 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
798 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
799 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
800 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
801 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
802 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
803 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
804 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
805 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
806 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
807 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
808 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
809 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
810 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
811 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
812 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
813 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
814 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
815 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
816 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
817 *
818 * (*) value not defined in all devices.
819 * @retval State of Periphs (1 or 0).
820 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)821 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
822 {
823 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
824 }
825
826 /**
827 * @brief Disable APB2 peripherals clock.
828 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
829 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
830 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
831 * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
832 * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
833 * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
834 * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
835 * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
836 * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
837 * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
838 * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
839 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
840 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
841 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
842 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
843 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
844 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
845 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
846 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
847 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
848 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
849 * @param Periphs This parameter can be a combination of the following values:
850 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
851 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
852 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
853 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
854 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
855 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
856 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
857 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
858 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
859 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
860 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
861 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
862 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
863 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
864 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
865 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
866 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
867 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
868 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
869 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
870 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
871 *
872 * (*) value not defined in all devices.
873 * @retval None
874 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)875 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
876 {
877 CLEAR_BIT(RCC->APB2ENR, Periphs);
878 }
879
880 /**
881 * @brief Force APB2 peripherals reset.
882 * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
883 * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
884 * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
885 * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
886 * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
887 * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
888 * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
889 * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
890 * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
891 * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
892 * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
893 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
894 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
895 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
896 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
897 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
898 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
899 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
900 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
901 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
902 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
903 * @param Periphs This parameter can be a combination of the following values:
904 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
905 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
906 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
907 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
908 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
909 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
910 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
911 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
912 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
913 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
914 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
915 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
916 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
917 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
918 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
919 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
920 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
921 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
922 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
923 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
924 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
925 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
926 *
927 * (*) value not defined in all devices.
928 * @retval None
929 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)930 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
931 {
932 SET_BIT(RCC->APB2RSTR, Periphs);
933 }
934
935 /**
936 * @brief Release APB2 peripherals reset.
937 * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
938 * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
939 * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
940 * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
941 * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
942 * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
943 * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
944 * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
945 * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
946 * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
947 * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
948 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
949 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
950 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
951 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
952 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
953 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
954 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
955 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
956 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
957 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
958 * @param Periphs This parameter can be a combination of the following values:
959 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
960 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
961 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
962 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
963 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
964 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
965 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
966 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
967 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
968 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
969 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
970 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
971 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
972 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
973 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
974 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
975 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
976 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
977 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
978 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
979 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
980 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
981 *
982 * (*) value not defined in all devices.
983 * @retval None
984 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)985 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
986 {
987 CLEAR_BIT(RCC->APB2RSTR, Periphs);
988 }
989
990 /**
991 * @}
992 */
993
994
995 /**
996 * @}
997 */
998
999 /**
1000 * @}
1001 */
1002
1003 #endif /* defined(RCC) */
1004
1005 /**
1006 * @}
1007 */
1008
1009 #ifdef __cplusplus
1010 }
1011 #endif
1012
1013 #endif /* __STM32F1xx_LL_BUS_H */
1014
1015 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1016
