1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32F4xx_LL_BUS_H
37 #define __STM32F4xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32f4xx.h"
45
46 /** @addtogroup STM32F4xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /* Private macros ------------------------------------------------------------*/
60 /* Exported types ------------------------------------------------------------*/
61 /* Exported constants --------------------------------------------------------*/
62 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
63 * @{
64 */
65
66 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
67 * @{
68 */
69 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
70 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
71 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
72 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
73 #if defined(GPIOD)
74 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
75 #endif /* GPIOD */
76 #if defined(GPIOE)
77 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
78 #endif /* GPIOE */
79 #if defined(GPIOF)
80 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
81 #endif /* GPIOF */
82 #if defined(GPIOG)
83 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
84 #endif /* GPIOG */
85 #if defined(GPIOH)
86 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
87 #endif /* GPIOH */
88 #if defined(GPIOI)
89 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
90 #endif /* GPIOI */
91 #if defined(GPIOJ)
92 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
93 #endif /* GPIOJ */
94 #if defined(GPIOK)
95 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
96 #endif /* GPIOK */
97 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
98 #if defined(RCC_AHB1ENR_BKPSRAMEN)
99 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
100 #endif /* RCC_AHB1ENR_BKPSRAMEN */
101 #if defined(RCC_AHB1ENR_CCMDATARAMEN)
102 #define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN
103 #endif /* RCC_AHB1ENR_CCMDATARAMEN */
104 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
105 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
106 #if defined(RCC_AHB1ENR_RNGEN)
107 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN
108 #endif /* RCC_AHB1ENR_RNGEN */
109 #if defined(DMA2D)
110 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
111 #endif /* DMA2D */
112 #if defined(ETH)
113 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
114 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
115 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
116 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
117 #endif /* ETH */
118 #if defined(USB_OTG_HS)
119 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
120 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
121 #endif /* USB_OTG_HS */
122 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
123 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
124 #if defined(RCC_AHB1LPENR_SRAM2LPEN)
125 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
126 #endif /* RCC_AHB1LPENR_SRAM2LPEN */
127 #if defined(RCC_AHB1LPENR_SRAM3LPEN)
128 #define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN
129 #endif /* RCC_AHB1LPENR_SRAM3LPEN */
130 /**
131 * @}
132 */
133
134 #if defined(RCC_AHB2_SUPPORT)
135 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
136 * @{
137 */
138 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
139 #if defined(DCMI)
140 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
141 #endif /* DCMI */
142 #if defined(CRYP)
143 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
144 #endif /* CRYP */
145 #if defined(AES)
146 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
147 #endif /* AES */
148 #if defined(HASH)
149 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
150 #endif /* HASH */
151 #if defined(RCC_AHB2ENR_RNGEN)
152 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
153 #endif /* RCC_AHB2ENR_RNGEN */
154 #if defined(USB_OTG_FS)
155 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
156 #endif /* USB_OTG_FS */
157 /**
158 * @}
159 */
160 #endif /* RCC_AHB2_SUPPORT */
161
162 #if defined(RCC_AHB3_SUPPORT)
163 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
164 * @{
165 */
166 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
167 #if defined(FSMC_Bank1)
168 #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
169 #endif /* FSMC_Bank1 */
170 #if defined(FMC_Bank1)
171 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
172 #endif /* FMC_Bank1 */
173 #if defined(QUADSPI)
174 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
175 #endif /* QUADSPI */
176 /**
177 * @}
178 */
179 #endif /* RCC_AHB3_SUPPORT */
180
181 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
182 * @{
183 */
184 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
185 #if defined(TIM2)
186 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
187 #endif /* TIM2 */
188 #if defined(TIM3)
189 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
190 #endif /* TIM3 */
191 #if defined(TIM4)
192 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
193 #endif /* TIM4 */
194 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
195 #if defined(TIM6)
196 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
197 #endif /* TIM6 */
198 #if defined(TIM7)
199 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
200 #endif /* TIM7 */
201 #if defined(TIM12)
202 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
203 #endif /* TIM12 */
204 #if defined(TIM13)
205 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
206 #endif /* TIM13 */
207 #if defined(TIM14)
208 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
209 #endif /* TIM14 */
210 #if defined(LPTIM1)
211 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
212 #endif /* LPTIM1 */
213 #if defined(RCC_APB1ENR_RTCAPBEN)
214 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN
215 #endif /* RCC_APB1ENR_RTCAPBEN */
216 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
217 #if defined(SPI2)
218 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
219 #endif /* SPI2 */
220 #if defined(SPI3)
221 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
222 #endif /* SPI3 */
223 #if defined(SPDIFRX)
224 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
225 #endif /* SPDIFRX */
226 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
227 #if defined(USART3)
228 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
229 #endif /* USART3 */
230 #if defined(UART4)
231 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
232 #endif /* UART4 */
233 #if defined(UART5)
234 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
235 #endif /* UART5 */
236 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
237 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
238 #if defined(I2C3)
239 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
240 #endif /* I2C3 */
241 #if defined(FMPI2C1)
242 #define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN
243 #endif /* FMPI2C1 */
244 #if defined(CAN1)
245 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
246 #endif /* CAN1 */
247 #if defined(CAN2)
248 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
249 #endif /* CAN2 */
250 #if defined(CAN3)
251 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
252 #endif /* CAN3 */
253 #if defined(CEC)
254 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
255 #endif /* CEC */
256 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
257 #if defined(DAC1)
258 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
259 #endif /* DAC1 */
260 #if defined(UART7)
261 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
262 #endif /* UART7 */
263 #if defined(UART8)
264 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
265 #endif /* UART8 */
266 /**
267 * @}
268 */
269
270 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
271 * @{
272 */
273 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
274 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
275 #if defined(TIM8)
276 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
277 #endif /* TIM8 */
278 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
279 #if defined(USART6)
280 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
281 #endif /* USART6 */
282 #if defined(UART9)
283 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
284 #endif /* UART9 */
285 #if defined(UART10)
286 #define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN
287 #endif /* UART10 */
288 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
289 #if defined(ADC2)
290 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
291 #endif /* ADC2 */
292 #if defined(ADC3)
293 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
294 #endif /* ADC3 */
295 #if defined(SDIO)
296 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
297 #endif /* SDIO */
298 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
299 #if defined(SPI4)
300 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
301 #endif /* SPI4 */
302 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
303 #if defined(RCC_APB2ENR_EXTITEN)
304 #define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN
305 #endif /* RCC_APB2ENR_EXTITEN */
306 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
307 #if defined(TIM10)
308 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
309 #endif /* TIM10 */
310 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
311 #if defined(SPI5)
312 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
313 #endif /* SPI5 */
314 #if defined(SPI6)
315 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
316 #endif /* SPI6 */
317 #if defined(SAI1)
318 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
319 #endif /* SAI1 */
320 #if defined(SAI2)
321 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
322 #endif /* SAI2 */
323 #if defined(LTDC)
324 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
325 #endif /* LTDC */
326 #if defined(DSI)
327 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
328 #endif /* DSI */
329 #if defined(DFSDM1_Channel0)
330 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
331 #endif /* DFSDM1_Channel0 */
332 #if defined(DFSDM2_Channel0)
333 #define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN
334 #endif /* DFSDM2_Channel0 */
335 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
336 /**
337 * @}
338 */
339
340 /**
341 * @}
342 */
343
344 /* Exported macro ------------------------------------------------------------*/
345 /* Exported functions --------------------------------------------------------*/
346 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
347 * @{
348 */
349
350 /** @defgroup BUS_LL_EF_AHB1 AHB1
351 * @{
352 */
353
354 /**
355 * @brief Enable AHB1 peripherals clock.
356 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
357 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
358 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
359 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
360 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
361 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
362 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
363 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
364 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
365 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
366 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
367 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
368 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
369 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n
370 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
371 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
372 * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n
373 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
374 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
375 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
376 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
377 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
378 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
379 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
380 * @param Periphs This parameter can be a combination of the following values:
381 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
382 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
383 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
384 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
385 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
386 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
387 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
388 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
389 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
390 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
391 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
392 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
393 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
394 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
395 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
396 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
397 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
398 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
399 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
400 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
401 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
402 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
403 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
404 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
405 *
406 * (*) value not defined in all devices.
407 * @retval None
408 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)409 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
410 {
411 __IO uint32_t tmpreg;
412 SET_BIT(RCC->AHB1ENR, Periphs);
413 /* Delay after an RCC peripheral clock enabling */
414 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
415 (void)tmpreg;
416 }
417
418 /**
419 * @brief Check if AHB1 peripheral clock is enabled or not
420 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
421 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
422 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
423 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
424 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
425 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
426 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
427 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
428 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
429 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
430 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
431 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
432 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
433 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n
434 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
435 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
436 * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
437 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
438 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
439 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
440 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
441 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
442 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
443 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
444 * @param Periphs This parameter can be a combination of the following values:
445 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
446 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
447 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
448 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
449 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
450 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
451 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
452 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
453 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
454 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
455 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
456 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
457 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
458 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
459 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
460 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
461 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
462 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
463 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
464 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
465 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
466 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
467 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
468 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
469 *
470 * (*) value not defined in all devices.
471 * @retval State of Periphs (1 or 0).
472 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)473 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
474 {
475 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
476 }
477
478 /**
479 * @brief Disable AHB1 peripherals clock.
480 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
481 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
482 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
483 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
484 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
485 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
486 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
487 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
488 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
489 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
490 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
491 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
492 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
493 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n
494 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
495 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
496 * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n
497 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
498 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
499 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
500 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
501 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
502 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
503 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
504 * @param Periphs This parameter can be a combination of the following values:
505 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
506 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
507 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
508 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
509 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
510 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
511 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
512 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
513 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
514 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
515 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
516 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
517 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
518 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
519 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
520 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
521 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
522 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
523 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
524 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
525 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
526 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
527 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
528 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
529 *
530 * (*) value not defined in all devices.
531 * @retval None
532 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)533 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
534 {
535 CLEAR_BIT(RCC->AHB1ENR, Periphs);
536 }
537
538 /**
539 * @brief Force AHB1 peripherals reset.
540 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
541 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
542 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
543 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
544 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
545 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
546 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
547 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
548 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
549 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
550 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
551 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
552 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
553 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
554 * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n
555 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
556 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
557 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
558 * @param Periphs This parameter can be a combination of the following values:
559 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
560 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
561 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
562 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
563 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
564 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
565 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
566 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
567 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
568 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
569 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
570 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
571 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
572 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
573 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
574 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
575 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
576 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
577 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
578 *
579 * (*) value not defined in all devices.
580 * @retval None
581 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)582 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
583 {
584 SET_BIT(RCC->AHB1RSTR, Periphs);
585 }
586
587 /**
588 * @brief Release AHB1 peripherals reset.
589 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
590 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
591 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
592 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
593 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
594 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
595 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
596 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
597 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
598 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
599 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
600 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
601 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
602 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
603 * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
604 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
605 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
606 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
607 * @param Periphs This parameter can be a combination of the following values:
608 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
609 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
610 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
611 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
612 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
613 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
614 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
615 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
616 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
617 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
618 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
619 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
620 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
621 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
622 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
623 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
624 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
625 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
626 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
627 *
628 * (*) value not defined in all devices.
629 * @retval None
630 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)631 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
632 {
633 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
634 }
635
636 /**
637 * @brief Enable AHB1 peripheral clocks in low-power mode
638 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
639 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
640 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
641 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
642 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
643 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
644 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
645 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
646 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
647 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
648 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
649 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
650 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
651 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
652 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
653 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
654 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n
655 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
656 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
657 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
658 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
659 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
660 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
661 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
662 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
663 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
664 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
665 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
666 * @param Periphs This parameter can be a combination of the following values:
667 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
668 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
669 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
670 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
671 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
672 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
673 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
674 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
675 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
676 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
677 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
678 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
679 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
680 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
681 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
682 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
683 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
684 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
685 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
686 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
687 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
688 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
689 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
690 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
691 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
692 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
693 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
694 *
695 * (*) value not defined in all devices.
696 * @retval None
697 */
LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)698 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
699 {
700 __IO uint32_t tmpreg;
701 SET_BIT(RCC->AHB1LPENR, Periphs);
702 /* Delay after an RCC peripheral clock enabling */
703 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
704 (void)tmpreg;
705 }
706
707 /**
708 * @brief Disable AHB1 peripheral clocks in low-power mode
709 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
710 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
711 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
712 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
713 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
714 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
715 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
716 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
717 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
718 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
719 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
720 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
721 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
722 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
723 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
724 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
725 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n
726 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
727 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
728 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
729 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
730 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
731 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
732 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
733 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
734 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
735 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
736 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
737 * @param Periphs This parameter can be a combination of the following values:
738 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
739 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
740 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
741 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
742 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
743 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
744 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
745 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
746 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
747 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
748 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
749 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
750 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
751 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
752 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
753 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
754 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
755 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
756 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
757 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
758 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
759 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
760 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
761 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
762 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
763 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
764 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
765 *
766 * (*) value not defined in all devices.
767 * @retval None
768 */
LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)769 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
770 {
771 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
772 }
773
774 /**
775 * @}
776 */
777
778 #if defined(RCC_AHB2_SUPPORT)
779 /** @defgroup BUS_LL_EF_AHB2 AHB2
780 * @{
781 */
782
783 /**
784 * @brief Enable AHB2 peripherals clock.
785 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
786 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
787 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
788 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
789 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
790 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
791 * @param Periphs This parameter can be a combination of the following values:
792 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
793 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
794 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
795 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
796 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
797 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
798 *
799 * (*) value not defined in all devices.
800 * @retval None
801 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)802 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
803 {
804 __IO uint32_t tmpreg;
805 SET_BIT(RCC->AHB2ENR, Periphs);
806 /* Delay after an RCC peripheral clock enabling */
807 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
808 (void)tmpreg;
809 }
810
811 /**
812 * @brief Check if AHB2 peripheral clock is enabled or not
813 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
814 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
815 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
816 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
817 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
818 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
819 * @param Periphs This parameter can be a combination of the following values:
820 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
821 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
822 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
823 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
824 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
825 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
826 *
827 * (*) value not defined in all devices.
828 * @retval State of Periphs (1 or 0).
829 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)830 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
831 {
832 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
833 }
834
835 /**
836 * @brief Disable AHB2 peripherals clock.
837 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
838 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
839 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
840 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
841 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
842 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
843 * @param Periphs This parameter can be a combination of the following values:
844 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
845 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
846 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
847 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
848 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
849 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
850 *
851 * (*) value not defined in all devices.
852 * @retval None
853 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)854 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
855 {
856 CLEAR_BIT(RCC->AHB2ENR, Periphs);
857 }
858
859 /**
860 * @brief Force AHB2 peripherals reset.
861 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
862 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
863 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
864 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
865 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
866 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
867 * @param Periphs This parameter can be a combination of the following values:
868 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
869 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
870 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
871 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
872 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
873 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
874 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
875 *
876 * (*) value not defined in all devices.
877 * @retval None
878 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)879 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
880 {
881 SET_BIT(RCC->AHB2RSTR, Periphs);
882 }
883
884 /**
885 * @brief Release AHB2 peripherals reset.
886 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
887 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
888 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
889 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
890 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
891 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
892 * @param Periphs This parameter can be a combination of the following values:
893 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
894 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
895 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
896 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
897 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
898 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
899 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
900 *
901 * (*) value not defined in all devices.
902 * @retval None
903 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)904 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
905 {
906 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
907 }
908
909 /**
910 * @brief Enable AHB2 peripheral clocks in low-power mode
911 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
912 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
913 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
914 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
915 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
916 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
917 * @param Periphs This parameter can be a combination of the following values:
918 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
919 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
920 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
921 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
922 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
923 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
924 *
925 * (*) value not defined in all devices.
926 * @retval None
927 */
LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)928 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
929 {
930 __IO uint32_t tmpreg;
931 SET_BIT(RCC->AHB2LPENR, Periphs);
932 /* Delay after an RCC peripheral clock enabling */
933 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
934 (void)tmpreg;
935 }
936
937 /**
938 * @brief Disable AHB2 peripheral clocks in low-power mode
939 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
940 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
941 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
942 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
943 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
944 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
945 * @param Periphs This parameter can be a combination of the following values:
946 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
947 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
948 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
949 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
950 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
951 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
952 *
953 * (*) value not defined in all devices.
954 * @retval None
955 */
LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)956 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
957 {
958 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
959 }
960
961 /**
962 * @}
963 */
964 #endif /* RCC_AHB2_SUPPORT */
965
966 #if defined(RCC_AHB3_SUPPORT)
967 /** @defgroup BUS_LL_EF_AHB3 AHB3
968 * @{
969 */
970
971 /**
972 * @brief Enable AHB3 peripherals clock.
973 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
974 * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n
975 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
976 * @param Periphs This parameter can be a combination of the following values:
977 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
978 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
979 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
980 *
981 * (*) value not defined in all devices.
982 * @retval None
983 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)984 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
985 {
986 __IO uint32_t tmpreg;
987 SET_BIT(RCC->AHB3ENR, Periphs);
988 /* Delay after an RCC peripheral clock enabling */
989 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
990 (void)tmpreg;
991 }
992
993 /**
994 * @brief Check if AHB3 peripheral clock is enabled or not
995 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
996 * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n
997 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
998 * @param Periphs This parameter can be a combination of the following values:
999 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1000 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1001 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1002 *
1003 * (*) value not defined in all devices.
1004 * @retval State of Periphs (1 or 0).
1005 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)1006 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1007 {
1008 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
1009 }
1010
1011 /**
1012 * @brief Disable AHB3 peripherals clock.
1013 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
1014 * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n
1015 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
1016 * @param Periphs This parameter can be a combination of the following values:
1017 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1018 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1019 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1020 *
1021 * (*) value not defined in all devices.
1022 * @retval None
1023 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)1024 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
1025 {
1026 CLEAR_BIT(RCC->AHB3ENR, Periphs);
1027 }
1028
1029 /**
1030 * @brief Force AHB3 peripherals reset.
1031 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
1032 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n
1033 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
1034 * @param Periphs This parameter can be a combination of the following values:
1035 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1036 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1037 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1038 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1039 *
1040 * (*) value not defined in all devices.
1041 * @retval None
1042 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)1043 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
1044 {
1045 SET_BIT(RCC->AHB3RSTR, Periphs);
1046 }
1047
1048 /**
1049 * @brief Release AHB3 peripherals reset.
1050 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
1051 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n
1052 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
1053 * @param Periphs This parameter can be a combination of the following values:
1054 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1055 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1056 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1057 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1058 *
1059 * (*) value not defined in all devices.
1060 * @retval None
1061 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)1062 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
1063 {
1064 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
1065 }
1066
1067 /**
1068 * @brief Enable AHB3 peripheral clocks in low-power mode
1069 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
1070 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
1071 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
1072 * @param Periphs This parameter can be a combination of the following values:
1073 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1074 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1075 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1076 *
1077 * (*) value not defined in all devices.
1078 * @retval None
1079 */
LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)1080 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
1081 {
1082 __IO uint32_t tmpreg;
1083 SET_BIT(RCC->AHB3LPENR, Periphs);
1084 /* Delay after an RCC peripheral clock enabling */
1085 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
1086 (void)tmpreg;
1087 }
1088
1089 /**
1090 * @brief Disable AHB3 peripheral clocks in low-power mode
1091 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1092 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1093 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
1094 * @param Periphs This parameter can be a combination of the following values:
1095 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1096 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1097 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1098 *
1099 * (*) value not defined in all devices.
1100 * @retval None
1101 */
LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)1102 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
1103 {
1104 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
1105 }
1106
1107 /**
1108 * @}
1109 */
1110 #endif /* RCC_AHB3_SUPPORT */
1111
1112 /** @defgroup BUS_LL_EF_APB1 APB1
1113 * @{
1114 */
1115
1116 /**
1117 * @brief Enable APB1 peripherals clock.
1118 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
1119 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
1120 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
1121 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
1122 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
1123 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
1124 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
1125 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
1126 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
1127 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1128 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
1129 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
1130 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
1131 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1132 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
1133 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
1134 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
1135 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
1136 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
1137 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
1138 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
1139 * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n
1140 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
1141 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
1142 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
1143 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
1144 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
1145 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
1146 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
1147 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
1148 * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock
1149 * @param Periphs This parameter can be a combination of the following values:
1150 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1151 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1155 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1158 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1159 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1160 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1161 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1162 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1163 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1164 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1165 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1166 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1167 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1168 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1169 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1170 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1171 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1172 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1173 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1174 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1175 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1176 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1177 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1178 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1179 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1180 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1181 *
1182 * (*) value not defined in all devices.
1183 * @retval None
1184 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1185 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1186 {
1187 __IO uint32_t tmpreg;
1188 SET_BIT(RCC->APB1ENR, Periphs);
1189 /* Delay after an RCC peripheral clock enabling */
1190 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
1191 (void)tmpreg;
1192 }
1193
1194 /**
1195 * @brief Check if APB1 peripheral clock is enabled or not
1196 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1197 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1198 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1199 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1200 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1201 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1202 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1203 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1204 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1205 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1206 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1207 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1208 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1209 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1210 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1211 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1212 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1213 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1214 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1215 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1216 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1217 * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n
1218 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1219 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1220 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
1221 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1222 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
1223 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
1224 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1225 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
1226 * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock
1227 * @param Periphs This parameter can be a combination of the following values:
1228 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1229 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1230 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1231 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1232 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1233 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1234 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1235 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1236 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1237 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1238 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1239 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1240 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1241 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1242 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1243 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1244 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1245 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1246 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1247 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1248 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1249 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1250 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1251 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1252 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1253 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1254 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1255 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1256 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1257 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1258 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1259 *
1260 * (*) value not defined in all devices.
1261 * @retval State of Periphs (1 or 0).
1262 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1263 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1264 {
1265 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
1266 }
1267
1268 /**
1269 * @brief Disable APB1 peripherals clock.
1270 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
1271 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
1272 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
1273 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
1274 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
1275 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
1276 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
1277 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
1278 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
1279 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1280 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
1281 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
1282 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
1283 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1284 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
1285 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
1286 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
1287 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
1288 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
1289 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
1290 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
1291 * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n
1292 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
1293 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
1294 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
1295 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
1296 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
1297 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
1298 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
1299 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
1300 * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock
1301 * @param Periphs This parameter can be a combination of the following values:
1302 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1303 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1304 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1305 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1306 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1307 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1308 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1309 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1310 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1311 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1312 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1313 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1314 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1315 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1316 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1317 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1318 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1319 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1320 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1321 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1322 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1323 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1324 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1325 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1326 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1327 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1328 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1329 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1330 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1331 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1332 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1333 *
1334 * (*) value not defined in all devices.
1335 * @retval None
1336 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1337 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1338 {
1339 CLEAR_BIT(RCC->APB1ENR, Periphs);
1340 }
1341
1342 /**
1343 * @brief Force APB1 peripherals reset.
1344 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1345 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1346 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1347 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1348 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1349 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1350 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1351 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1352 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1353 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
1354 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
1355 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1356 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1357 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1358 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
1359 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
1360 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
1361 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
1362 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1363 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1364 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1365 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n
1366 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
1367 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
1368 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
1369 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
1370 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
1371 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
1372 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
1373 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
1374 * @param Periphs This parameter can be a combination of the following values:
1375 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1376 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1377 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1378 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1379 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1380 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1381 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1382 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1383 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1384 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1385 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1386 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1387 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1388 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1389 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1390 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1391 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1392 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1393 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1394 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1395 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1396 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1397 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1398 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1399 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1400 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1401 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1402 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1403 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1404 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1405 *
1406 * (*) value not defined in all devices.
1407 * @retval None
1408 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1409 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1410 {
1411 SET_BIT(RCC->APB1RSTR, Periphs);
1412 }
1413
1414 /**
1415 * @brief Release APB1 peripherals reset.
1416 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1417 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1418 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1419 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1420 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1421 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1422 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
1423 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
1424 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
1425 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
1426 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
1427 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1428 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1429 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
1430 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1431 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1432 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1433 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1434 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1435 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1436 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
1437 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n
1438 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
1439 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
1440 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
1441 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1442 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
1443 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
1444 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1445 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
1446 * @param Periphs This parameter can be a combination of the following values:
1447 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1448 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1449 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1450 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1451 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1452 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1453 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1454 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1455 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1456 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1457 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1458 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1459 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1460 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1461 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1462 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1463 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1464 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1465 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1466 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1467 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1468 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1469 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1470 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1471 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1472 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1473 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1474 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1475 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1476 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1477 *
1478 * (*) value not defined in all devices.
1479 * @retval None
1480 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1481 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1482 {
1483 CLEAR_BIT(RCC->APB1RSTR, Periphs);
1484 }
1485
1486 /**
1487 * @brief Enable APB1 peripheral clocks in low-power mode
1488 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1489 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1490 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1491 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1492 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
1493 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1494 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
1495 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
1496 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
1497 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1498 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
1499 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1500 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1501 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
1502 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1503 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1504 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1505 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1506 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1507 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1508 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1509 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1510 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1511 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1512 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1513 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
1514 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
1515 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
1516 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1517 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
1518 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower
1519 * @param Periphs This parameter can be a combination of the following values:
1520 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1521 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1522 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1523 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1524 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1526 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1527 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1528 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1529 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1530 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1531 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1532 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1533 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1534 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1535 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1536 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1537 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1538 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1539 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1540 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1541 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1542 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1543 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1544 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1545 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1546 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1547 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1548 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1549 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1550 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1551 *
1552 * (*) value not defined in all devices.
1553 * @retval None
1554 */
LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)1555 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
1556 {
1557 __IO uint32_t tmpreg;
1558 SET_BIT(RCC->APB1LPENR, Periphs);
1559 /* Delay after an RCC peripheral clock enabling */
1560 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
1561 (void)tmpreg;
1562 }
1563
1564 /**
1565 * @brief Disable APB1 peripheral clocks in low-power mode
1566 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1567 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1568 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1569 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1570 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
1571 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1572 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
1573 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
1574 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
1575 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1576 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
1577 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1578 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1579 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
1580 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1581 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1582 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1583 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1584 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1585 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1586 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1587 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1588 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1589 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1590 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1591 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
1592 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
1593 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
1594 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1595 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
1596 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower
1597 * @param Periphs This parameter can be a combination of the following values:
1598 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1599 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1600 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1601 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1602 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1603 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1604 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1605 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1606 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1607 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1608 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1609 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1610 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1611 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1612 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1613 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1614 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1615 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1616 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1617 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1618 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1619 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1620 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1621 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1622 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1623 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1624 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1625 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1626 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1627 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1628 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1629 *
1630 * (*) value not defined in all devices.
1631 * @retval None
1632 */
LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)1633 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
1634 {
1635 CLEAR_BIT(RCC->APB1LPENR, Periphs);
1636 }
1637
1638 /**
1639 * @}
1640 */
1641
1642 /** @defgroup BUS_LL_EF_APB2 APB2
1643 * @{
1644 */
1645
1646 /**
1647 * @brief Enable APB2 peripherals clock.
1648 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1649 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1650 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1651 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
1652 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n
1653 * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n
1654 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
1655 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
1656 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
1657 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
1658 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1659 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1660 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1661 * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n
1662 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1663 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
1664 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
1665 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
1666 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
1667 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1668 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1669 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1670 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
1671 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1672 * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock
1673 * @param Periphs This parameter can be a combination of the following values:
1674 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1675 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1676 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1677 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1678 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1679 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1680 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1681 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1682 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1683 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1684 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1685 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1686 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1687 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1688 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1689 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1690 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1691 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1692 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1693 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1694 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1695 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1696 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1697 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1698 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1699
1700 *
1701 * (*) value not defined in all devices.
1702 * @retval None
1703 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1704 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1705 {
1706 __IO uint32_t tmpreg;
1707 SET_BIT(RCC->APB2ENR, Periphs);
1708 /* Delay after an RCC peripheral clock enabling */
1709 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1710 (void)tmpreg;
1711 }
1712
1713 /**
1714 * @brief Check if APB2 peripheral clock is enabled or not
1715 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1716 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1717 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1718 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
1719 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n
1720 * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n
1721 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
1722 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
1723 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
1724 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
1725 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1726 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1727 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1728 * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n
1729 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1730 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
1731 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
1732 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
1733 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
1734 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1735 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1736 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1737 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
1738 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1739 * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock
1740 * @param Periphs This parameter can be a combination of the following values:
1741 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1742 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1743 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1744 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1745 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1746 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1747 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1748 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1749 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1750 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1751 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1752 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1753 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1754 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1755 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1756 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1757 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1758 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1759 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1760 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1761 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1762 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1763 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1764 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1765 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1766 *
1767 * (*) value not defined in all devices.
1768 * @retval State of Periphs (1 or 0).
1769 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1770 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1771 {
1772 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
1773 }
1774
1775 /**
1776 * @brief Disable APB2 peripherals clock.
1777 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1778 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1779 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1780 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
1781 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n
1782 * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n
1783 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
1784 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
1785 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
1786 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
1787 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1788 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1789 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1790 * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n
1791 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
1792 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
1793 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
1794 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
1795 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
1796 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1797 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1798 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1799 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
1800 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1801 * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock
1802 * @param Periphs This parameter can be a combination of the following values:
1803 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1804 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1805 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1806 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1807 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1808 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1809 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1810 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1811 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1812 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1813 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1814 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1815 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1816 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1817 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1818 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1819 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1820 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1821 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1822 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1823 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1824 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1825 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1826 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1827 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1828 *
1829 * (*) value not defined in all devices.
1830 * @retval None
1831 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1832 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1833 {
1834 CLEAR_BIT(RCC->APB2ENR, Periphs);
1835 }
1836
1837 /**
1838 * @brief Force APB2 peripherals reset.
1839 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1840 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1841 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1842 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
1843 * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n
1844 * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n
1845 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1846 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
1847 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1848 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1849 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1850 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
1851 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
1852 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
1853 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
1854 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
1855 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1856 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1857 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1858 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
1859 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1860 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset
1861 * @param Periphs This parameter can be a combination of the following values:
1862 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1863 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1864 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1865 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1866 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1867 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1868 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1869 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1870 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1871 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1872 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1873 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1874 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1875 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1876 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1877 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1878 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1879 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1880 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1881 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1882 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1883 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1884 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1885 *
1886 * (*) value not defined in all devices.
1887 * @retval None
1888 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1889 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1890 {
1891 SET_BIT(RCC->APB2RSTR, Periphs);
1892 }
1893
1894 /**
1895 * @brief Release APB2 peripherals reset.
1896 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1897 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1898 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1899 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
1900 * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n
1901 * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n
1902 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1903 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
1904 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1905 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1906 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1907 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
1908 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
1909 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
1910 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
1911 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
1912 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1913 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1914 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1915 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
1916 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1917 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset
1918 * @param Periphs This parameter can be a combination of the following values:
1919 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1920 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1921 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1922 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1923 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1924 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1925 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1926 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1927 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1928 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1929 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1930 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1931 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1932 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1933 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1935 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1936 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1937 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1938 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1939 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1940 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1941 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1942 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1943 *
1944 * (*) value not defined in all devices.
1945 * @retval None
1946 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1947 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1948 {
1949 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1950 }
1951
1952 /**
1953 * @brief Enable APB2 peripheral clocks in low-power mode
1954 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1955 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
1956 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1957 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1958 * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1959 * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1960 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1961 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1962 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
1963 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
1964 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1965 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
1966 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
1967 * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n
1968 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1969 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1970 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
1971 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
1972 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1973 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1974 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1975 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
1976 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1977 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1978 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1979 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower
1980 * @param Periphs This parameter can be a combination of the following values:
1981 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1982 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1983 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1984 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1985 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1986 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1987 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1988 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1989 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1990 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1991 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1992 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1993 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1994 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1995 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1996 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1997 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1998 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1999 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2000 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2001 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2002 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2003 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2004 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
2005 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
2006 *
2007 * (*) value not defined in all devices.
2008 * @retval None
2009 */
LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)2010 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
2011 {
2012 __IO uint32_t tmpreg;
2013 SET_BIT(RCC->APB2LPENR, Periphs);
2014 /* Delay after an RCC peripheral clock enabling */
2015 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2016 (void)tmpreg;
2017 }
2018
2019 /**
2020 * @brief Disable APB2 peripheral clocks in low-power mode
2021 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2022 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
2023 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2024 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
2025 * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n
2026 * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n
2027 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2028 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
2029 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
2030 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
2031 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2032 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
2033 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
2034 * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n
2035 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
2036 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
2037 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
2038 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
2039 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
2040 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2041 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
2042 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
2043 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
2044 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2045 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
2046 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower
2047 * @param Periphs This parameter can be a combination of the following values:
2048 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2049 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2050 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2051 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
2052 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2053 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
2054 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
2055 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
2056 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
2057 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
2058 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2059 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2060 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
2061 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
2062 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2063 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
2064 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
2065 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
2066 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2067 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2068 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2069 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2070 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2071 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
2072 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
2073 *
2074 * (*) value not defined in all devices.
2075 * @retval None
2076 */
LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)2077 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
2078 {
2079 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2080 }
2081
2082 /**
2083 * @}
2084 */
2085
2086 /**
2087 * @}
2088 */
2089
2090 /**
2091 * @}
2092 */
2093
2094 #endif /* defined(RCC) */
2095
2096 /**
2097 * @}
2098 */
2099
2100 #ifdef __cplusplus
2101 }
2102 #endif
2103
2104 #endif /* __STM32F4xx_LL_BUS_H */
2105
2106
