1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 @endverbatim
28 */
29
30 /* Define to prevent recursive inclusion -------------------------------------*/
31 #ifndef STM32WBAxx_LL_SYSTEM_H
32 #define STM32WBAxx_LL_SYSTEM_H
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 /* Includes ------------------------------------------------------------------*/
39 #include "stm32wbaxx.h"
40
41 /** @addtogroup STM32WBAxx_LL_Driver
42 * @{
43 */
44
45 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
46
47 /** @defgroup SYSTEM_LL SYSTEM
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
56 * @{
57 */
58
59 /**
60 * @brief Power-down in Run mode Flash key
61 */
62 #define FLASH_PDKEY1_1 0x04152637U /*!< Flash power down key1 */
63 #define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
64 to unlock the RUN_PD bit in FLASH_ACR */
65 /**
66 * @}
67 */
68
69 /** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection
70 * @{
71 */
72 #define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell (available in the SYSCFG_CCVR)*/
73 #define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/
74 /**
75 * @}
76 */
77
78
79 /** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE
80 * @{
81 */
82 #define LL_SYSCFG_MEMORIES_ERASE_ON_GOING 0U /*Memory erase on going*/
83 #define LL_SYSCFG_MEMORIES_ERASE_ENDED SYSCFG_MESR_MCLR /*Memory erase done */
84 /**
85 * @}
86 */
87
88 /* Private macros ------------------------------------------------------------*/
89
90 /* Exported types ------------------------------------------------------------*/
91 /* Exported constants --------------------------------------------------------*/
92 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
93 * @{
94 */
95
96 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
97 * @{
98 */
99 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */
100 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */
101 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast Mode Plus on PA15 */
102 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast Mode Plus on PB3 */
103 /**
104 * @}
105 */
106
107 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
108 * @{
109 */
110 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
111 with Break Input of TIM1/16/17 */
112 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
113 with TIM1/16/17 Break Input and also
114 the PVDE and PLS bits of the Power Control Interface */
115 #define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal
116 with Break Input of TIM1/16/17 */
117 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33
118 with Break Input of TIM1/16/17 */
119 /**
120 * @}
121 */
122
123 /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
124 * @note Only available when system implements security (TZEN=1)
125 * @{
126 */
127 #define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */
128 #define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */
129 #define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
130 #define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
131 #define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
132 #define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
133 /**
134 * @}
135 */
136
137 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
138 * @{
139 */
140 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
141 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
142 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
143 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
144 #if defined(I2C1)
145 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
146 #endif /* I2C1 */
147 /**
148 * @}
149 */
150
151 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
152 * @{
153 */
154 #if defined(LPTIM2)
155 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
156 #endif /* LPTIM2 */
157 /**
158 * @}
159 */
160
161 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
162 * @{
163 */
164 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
165 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
166 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
167 /**
168 * @}
169 */
170
171 /** @defgroup SYSTEM_LL_EC_APB7_GRP1_STOP_IP DBGMCU APB7 GRP1 STOP IP
172 * @{
173 */
174 #define LL_DBGMCU_APB7_GRP1_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/
175 #define LL_DBGMCU_APB7_GRP1_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
176 #define LL_DBGMCU_APB7_GRP1_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/
177 /**
178 * @}
179 */
180
181
182 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
183 * @{
184 */
185 #define LL_FLASH_LATENCY_0 0 /*!< FLASH Zero wait state */
186 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */
187 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
188 #define LL_FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Three wait states */
189 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_2 /*!< FLASH Four wait states */
190 #define LL_FLASH_LATENCY_5 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Five wait state */
191 #define LL_FLASH_LATENCY_6 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Six wait state */
192 #define LL_FLASH_LATENCY_7 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Seven wait states */
193 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_3 /*!< FLASH Eight wait states */
194 #define LL_FLASH_LATENCY_9 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_0) /*!< FLASH Nine wait states */
195 #define LL_FLASH_LATENCY_10 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1) /*!< FLASH Ten wait state */
196 #define LL_FLASH_LATENCY_11 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Eleven wait state */
197 #define LL_FLASH_LATENCY_12 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2) /*!< FLASH Twelve wait states */
198 #define LL_FLASH_LATENCY_13 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Thirteen wait states */
199 #define LL_FLASH_LATENCY_14 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Fourteen wait states */
200 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY /*!< FLASH Fifteen wait states */
201 /**
202 * @}
203 */
204
205 /**
206 * @}
207 */
208
209 /* Exported macros -----------------------------------------------------------*/
210
211 /* Exported functions --------------------------------------------------------*/
212 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
213 * @{
214 */
215
216 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
217 * @{
218 */
219
220 /**
221 * @brief Enable I/O analog switch voltage booster.
222 * @note When voltage booster is enabled, I/O analog switches are supplied
223 * by a dedicated voltage booster, from VDD power domain. This is
224 * the recommended configuration with low VDDA voltage operation.
225 * @note The I/O analog switch voltage booster is relevant for peripherals
226 * using I/O in analog input: ADC, COMP, OPAMP.
227 * However, COMP and OPAMP inputs have a high impedance and
228 * voltage booster do not impact performance significantly.
229 * Therefore, the voltage booster is mainly intended for
230 * usage with ADC.
231 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
232 * @retval None
233 */
LL_SYSCFG_EnableAnalogBooster(void)234 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
235 {
236 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
237 }
238
239 /**
240 * @brief Disable I/O analog switch voltage booster.
241 * @note When voltage booster is enabled, I/O analog switches are supplied
242 * by a dedicated voltage booster, from VDD power domain. This is
243 * the recommended configuration with low VDDA voltage operation.
244 * @note The I/O analog switch voltage booster is relevant for peripherals
245 * using I/O in analog input: ADC, COMP, OPAMP.
246 * However, COMP and OPAMP inputs have a high impedance and
247 * voltage booster do not impact performance significantly.
248 * Therefore, the voltage booster is mainly intended for
249 * usage with ADC.
250 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
251 * @retval None
252 */
LL_SYSCFG_DisableAnalogBooster(void)253 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
254 {
255 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
256 }
257
258 /**
259 * @brief Enable the I2C fast mode plus driving capability.
260 * @rmtoll SYSCFG_CFGR1 I2C_PABx_FMP LL_SYSCFG_EnableFastModePlus\n
261 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
262 * @param ConfigFastModePlus This parameter can be a combination of the following values:
263 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA6
264 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA7
265 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA15
266 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB3
267 * @retval None
268 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)269 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
270 {
271 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
272 }
273
274 /**
275 * @brief Disable the I2C fast mode plus driving capability.
276 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
277 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
278 * @param ConfigFastModePlus This parameter can be a combination of the following values:
279 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA6
280 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA7
281 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA15
282 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB3
283 * @retval None
284 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)285 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
286 {
287 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
288 }
289
290 /**
291 * @brief Enable Floating Point Unit Invalid operation Interrupt
292 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
293 * @retval None
294 */
LL_SYSCFG_EnableIT_FPU_IOC(void)295 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
296 {
297 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
298 }
299
300 /**
301 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
302 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
303 * @retval None
304 */
LL_SYSCFG_EnableIT_FPU_DZC(void)305 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
306 {
307 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
308 }
309
310 /**
311 * @brief Enable Floating Point Unit Underflow Interrupt
312 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
313 * @retval None
314 */
LL_SYSCFG_EnableIT_FPU_UFC(void)315 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
316 {
317 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
318 }
319
320 /**
321 * @brief Enable Floating Point Unit Overflow Interrupt
322 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
323 * @retval None
324 */
LL_SYSCFG_EnableIT_FPU_OFC(void)325 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
326 {
327 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
328 }
329
330 /**
331 * @brief Enable Floating Point Unit Input denormal Interrupt
332 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
333 * @retval None
334 */
LL_SYSCFG_EnableIT_FPU_IDC(void)335 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
336 {
337 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
338 }
339
340 /**
341 * @brief Enable Floating Point Unit Inexact Interrupt
342 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
343 * @retval None
344 */
LL_SYSCFG_EnableIT_FPU_IXC(void)345 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
346 {
347 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
348 }
349
350 /**
351 * @brief Disable Floating Point Unit Invalid operation Interrupt
352 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
353 * @retval None
354 */
LL_SYSCFG_DisableIT_FPU_IOC(void)355 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
356 {
357 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
358 }
359
360 /**
361 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
362 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
363 * @retval None
364 */
LL_SYSCFG_DisableIT_FPU_DZC(void)365 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
366 {
367 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
368 }
369
370 /**
371 * @brief Disable Floating Point Unit Underflow Interrupt
372 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
373 * @retval None
374 */
LL_SYSCFG_DisableIT_FPU_UFC(void)375 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
376 {
377 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
378 }
379
380 /**
381 * @brief Disable Floating Point Unit Overflow Interrupt
382 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
383 * @retval None
384 */
LL_SYSCFG_DisableIT_FPU_OFC(void)385 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
386 {
387 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
388 }
389
390 /**
391 * @brief Disable Floating Point Unit Input denormal Interrupt
392 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
393 * @retval None
394 */
LL_SYSCFG_DisableIT_FPU_IDC(void)395 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
396 {
397 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
398 }
399
400 /**
401 * @brief Disable Floating Point Unit Inexact Interrupt
402 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
403 * @retval None
404 */
LL_SYSCFG_DisableIT_FPU_IXC(void)405 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
406 {
407 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
408 }
409
410 /**
411 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
412 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
413 * @retval State of bit (1 or 0).
414 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)415 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
416 {
417 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
418 }
419
420 /**
421 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
422 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
423 * @retval State of bit (1 or 0).
424 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)425 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
426 {
427 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
428 }
429
430 /**
431 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
432 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
433 * @retval State of bit (1 or 0).
434 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)435 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
436 {
437 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
438 }
439
440 /**
441 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
442 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
443 * @retval State of bit (1 or 0).
444 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)445 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
446 {
447 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
448 }
449
450 /**
451 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
452 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
453 * @retval State of bit (1 or 0).
454 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)455 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
456 {
457 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
458 }
459
460 /**
461 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
462 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
463 * @retval State of bit (1 or 0).
464 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)465 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
466 {
467 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
468 }
469
470 /**
471 * @brief Set connections to TIM1/8/15/16/17 Break inputs
472 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
473 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
474 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
475 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
476 * @param Break This parameter can be a combination of the following values:
477 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
478 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
479 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
480 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
481 * @retval None
482 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)483 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
484 {
485 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
486 }
487
488 /**
489 * @brief Get connections to TIM1/8/15/16/17 Break inputs
490 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
491 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
492 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
493 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
494 * @retval Returned value can be can be a combination of the following values:
495 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
496 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
497 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
498 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
499 */
LL_SYSCFG_GetTIMBreakInputs(void)500 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
501 {
502 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
503 }
504
505 /**
506 * @}
507 */
508
509 /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management
510 * @{
511 */
512
513 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
514
515 /**
516 * @brief Configure Secure mode
517 * @note Only available from secure state when system implements security (TZEN=1)
518 * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
519 * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
520 * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
521 * @param Configuration This parameter shall be the full combination
522 * of the following values:
523 * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
524 * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
525 * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
526 * @retval None
527 */
LL_SYSCFG_ConfigSecure(uint32_t Configuration)528 __STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration)
529 {
530 WRITE_REG(SYSCFG->SECCFGR, Configuration);
531 }
532
533 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
534
535 /**
536 * @brief Get Secure mode configuration
537 * @note Only available when system implements security (TZEN=1)
538 * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
539 * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
540 * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
541 * @retval Returned value is the combination of the following values:
542 * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
543 * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
544 * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
545 */
LL_SYSCFG_GetConfigSecure(void)546 __STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void)
547 {
548 return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU));
549 }
550
551 /**
552 * @}
553 */
554
555 /**
556 * @}
557 */
558
559 /** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION
560 * @{
561 */
562
563 /**
564 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD
565 * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue
566 * @retval Returned value is the PMOS compensation cell
567 */
LL_SYSCFG_GetPMOSVddCompensationValue(void)568 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void)
569 {
570 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1));
571 }
572
573 /**
574 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD
575 * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue
576 * @retval Returned value is the NMOS compensation cell
577 */
LL_SYSCFG_GetNMOSVddCompensationValue(void)578 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void)
579 {
580 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1));
581 }
582
583
584
585 /**
586 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD
587 * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode
588 * @param PMOSCode PMOS compensation code
589 * This code is applied to the PMOS compensation cell when the CS1 bit of the
590 * SYSCFG_CMPCR is set
591 * @retval None
592 */
LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)593 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)
594 {
595 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos);
596 }
597
598 /**
599 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD
600 * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode
601 * @retval Returned value is the PMOS compensation cell
602 */
LL_SYSCFG_GetPMOSVddCompensationCode(void)603 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void)
604 {
605 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1));
606 }
607
608 /**
609 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD
610 * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode
611 * @param NMOSCode NMOS compensation code
612 * This code is applied to the NMOS compensation cell when the CS2 bit of the
613 * SYSCFG_CMPCR is set
614 * @retval None
615 */
LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)616 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)
617 {
618 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos);
619 }
620
621 /**
622 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD
623 * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode
624 * @retval Returned value is the Vdd compensation cell code for NMOS transistors
625 */
LL_SYSCFG_GetNMOSVddCompensationCode(void)626 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void)
627 {
628 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1));
629 }
630
631 /**
632 * @brief Enable the Compensation Cell of GPIO supplied by VDD
633 * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell
634 * @note The vdd compensation cell can be used only when the device supply
635 * voltage ranges from 1.71 to 3.6 V
636 * @retval None
637 */
LL_SYSCFG_EnableVddCompensationCell(void)638 __STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void)
639 {
640 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
641 }
642
643 /**
644 * @brief Disable the Compensation Cell of GPIO supplied by VDD
645 * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell
646 * @note The Vdd compensation cell can be used only when the device supply
647 * voltage ranges from 1.71 to 3.6 V
648 * @retval None
649 */
LL_SYSCFG_DisableVddCompensationCell(void)650 __STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void)
651 {
652 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
653 }
654
655 /**
656 * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable
657 * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell
658 * @retval State of bit (1 or 0).
659 */
LL_SYSCFG_IsEnabled_VddCompensationCell(void)660 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void)
661 {
662 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL);
663 }
664
665 /**
666 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD
667 * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR
668 * @retval State of bit (1 or 0).
669 */
LL_SYSCFG_IsActiveFlag_VddCMPCR(void)670 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void)
671 {
672 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL);
673 }
674
675 /**
676 * @brief Set the compensation cell code selection of GPIO supplied by VDD
677 * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode
678 * @param CompCode: Selects the code to be applied for the Vdd compensation cell
679 * This parameter can be one of the following values:
680 * @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
681 * @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
682 * @retval None
683 */
LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)684 __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)
685 {
686 SET_BIT(SYSCFG->CCCSR, CompCode);
687 }
688
689 /**
690 * @brief Get the compensation cell code selection of GPIO supplied by VDD
691 * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode
692 * @retval Returned value can be one of the following values:
693 * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
694 * @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
695 */
LL_SYSCFG_GetVddCellCompensationCode(void)696 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void)
697 {
698 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1));
699 }
700
701 /**
702 * @}
703 */
704
705 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
706 * @{
707 */
708
709 /**
710 * @brief Return the device identifier
711 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
712 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
713 */
LL_DBGMCU_GetDeviceID(void)714 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
715 {
716 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
717 }
718
719 /**
720 * @brief Return the device revision identifier
721 * @note This field indicates the revision of the device.
722 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
723 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
724 */
LL_DBGMCU_GetRevisionID(void)725 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
726 {
727 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
728 }
729
730 /**
731 * @brief Enable the Debug Module during STOP mode
732 * @rmtoll DBGMCU_SCR DBG_STOP LL_DBGMCU_EnableDBGStopMode
733 * @retval None
734 */
LL_DBGMCU_EnableDBGStopMode(void)735 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
736 {
737 SET_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STOP);
738 }
739
740 /**
741 * @brief Disable the Debug Module during STOP mode
742 * @rmtoll DBGMCU_SCR DBG_STOP LL_DBGMCU_DisableDBGStopMode
743 * @retval None
744 */
LL_DBGMCU_DisableDBGStopMode(void)745 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
746 {
747 CLEAR_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STOP);
748 }
749
750 /**
751 * @brief Enable the Debug Module during STANDBY mode
752 * @rmtoll DBGMCU_SCR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
753 * @retval None
754 */
LL_DBGMCU_EnableDBGStandbyMode(void)755 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
756 {
757 SET_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STANDBY);
758 }
759
760 /**
761 * @brief Disable the Debug Module during STANDBY mode
762 * @rmtoll DBGMCU_SCR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
763 * @retval None
764 */
LL_DBGMCU_DisableDBGStandbyMode(void)765 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
766 {
767 CLEAR_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STANDBY);
768 }
769
770 /**
771 * @brief Freeze APB1 peripherals (group1 peripherals)
772 * @rmtoll DBGMCU_APB1LFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
773 * @param Periphs This parameter can be a combination of the following values:
774 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
775 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
776 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
777 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
778 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
779 * @retval None
780 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)781 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
782 {
783 SET_BIT(DBGMCU->APB1LFZR, Periphs);
784 }
785
786 /**
787 * @brief Freeze APB1 peripherals (group2 peripherals)
788 * @rmtoll DBGMCU_APB1HFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
789 * @param Periphs This parameter can be a combination of the following values:
790 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
791 * @retval None
792 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)793 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
794 {
795 SET_BIT(DBGMCU->APB1HFZR, Periphs);
796 }
797
798 /**
799 * @brief Unfreeze APB1 peripherals (group1 peripherals)
800 * @rmtoll DBGMCU_APB1LFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
801 * @param Periphs This parameter can be a combination of the following values:
802 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
803 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
804 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
805 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
806 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
807 * @retval None
808 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)809 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
810 {
811 CLEAR_BIT(DBGMCU->APB1LFZR, Periphs);
812 }
813
814 /**
815 * @brief Unfreeze APB1 peripherals (group2 peripherals)
816 * @rmtoll DBGMCU_APB1HFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
817 * @param Periphs This parameter can be a combination of the following values:
818 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
819 * @retval None
820 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)821 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
822 {
823 CLEAR_BIT(DBGMCU->APB1HFZR, Periphs);
824 }
825
826 /**
827 * @brief Freeze APB2 peripherals
828 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
829 * @param Periphs This parameter can be a combination of the following values:
830 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
831 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
832 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
833 * @retval None
834 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)835 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
836 {
837 SET_BIT(DBGMCU->APB2FZR, Periphs);
838 }
839
840 /**
841 * @brief Unfreeze APB2 peripherals
842 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
843 * @param Periphs This parameter can be a combination of the following values:
844 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
845 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
846 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
847 * @retval None
848 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)849 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
850 {
851 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
852 }
853
854 /**
855 * @brief Freeze APB7 peripherals
856 * @rmtoll DBGMCU_APB7FZ DBG_TIMx_STOP LL_DBGMCU_APB7_GRP1_FreezePeriph
857 * @param Periphs This parameter can be a combination of the following values:
858 * @arg @ref LL_DBGMCU_APB7_GRP1_I2C3_STOP
859 * @arg @ref LL_DBGMCU_APB7_GRP1_LPTIM1_STOP
860 * @arg @ref LL_DBGMCU_APB7_GRP1_RTC_STOP
861 * @retval None
862 */
LL_DBGMCU_APB7_GRP1_FreezePeriph(uint32_t Periphs)863 __STATIC_INLINE void LL_DBGMCU_APB7_GRP1_FreezePeriph(uint32_t Periphs)
864 {
865 SET_BIT(DBGMCU->APB7FZR, Periphs);
866 }
867
868 /**
869 * @brief Unfreeze APB7 peripherals
870 * @rmtoll DBGMCU_APB7FZR DBG_TIMx_STOP LL_DBGMCU_APB7_GRP1_UnFreezePeriph
871 * @param Periphs This parameter can be a combination of the following values:
872 * @arg @ref LL_DBGMCU_APB7_GRP1_I2C3_STOP
873 * @arg @ref LL_DBGMCU_APB7_GRP1_LPTIM1_STOP
874 * @arg @ref LL_DBGMCU_APB7_GRP1_RTC_STOP
875 * @retval None
876 */
LL_DBGMCU_APB7_GRP1_UnFreezePeriph(uint32_t Periphs)877 __STATIC_INLINE void LL_DBGMCU_APB7_GRP1_UnFreezePeriph(uint32_t Periphs)
878 {
879 CLEAR_BIT(DBGMCU->APB7FZR, Periphs);
880 }
881
882 /**
883 * @}
884 */
885
886
887
888 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
889 * @{
890 */
891 /**
892 * @brief Set FLASH Latency
893 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
894 * @param Latency This parameter can be one of the following values:
895 * @arg @ref LL_FLASH_LATENCY_0
896 * @arg @ref LL_FLASH_LATENCY_1
897 * @arg @ref LL_FLASH_LATENCY_2
898 * @arg @ref LL_FLASH_LATENCY_3
899 * @arg @ref LL_FLASH_LATENCY_4
900 * @arg @ref LL_FLASH_LATENCY_5
901 * @arg @ref LL_FLASH_LATENCY_6
902 * @arg @ref LL_FLASH_LATENCY_7
903 * @arg @ref LL_FLASH_LATENCY_8
904 * @arg @ref LL_FLASH_LATENCY_9
905 * @arg @ref LL_FLASH_LATENCY_10
906 * @arg @ref LL_FLASH_LATENCY_11
907 * @arg @ref LL_FLASH_LATENCY_12
908 * @arg @ref LL_FLASH_LATENCY_13
909 * @arg @ref LL_FLASH_LATENCY_14
910 * @arg @ref LL_FLASH_LATENCY_15
911 * @retval None
912 */
LL_FLASH_SetLatency(uint32_t Latency)913 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
914 {
915 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
916 }
917
918 /**
919 * @brief Get FLASH Latency
920 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
921 * @retval Returned value can be one of the following values:
922 * @arg @ref LL_FLASH_LATENCY_0
923 * @arg @ref LL_FLASH_LATENCY_1
924 * @arg @ref LL_FLASH_LATENCY_2
925 * @arg @ref LL_FLASH_LATENCY_3
926 * @arg @ref LL_FLASH_LATENCY_4
927 * @arg @ref LL_FLASH_LATENCY_5
928 * @arg @ref LL_FLASH_LATENCY_6
929 * @arg @ref LL_FLASH_LATENCY_7
930 * @arg @ref LL_FLASH_LATENCY_8
931 * @arg @ref LL_FLASH_LATENCY_9
932 * @arg @ref LL_FLASH_LATENCY_10
933 * @arg @ref LL_FLASH_LATENCY_11
934 * @arg @ref LL_FLASH_LATENCY_12
935 * @arg @ref LL_FLASH_LATENCY_13
936 * @arg @ref LL_FLASH_LATENCY_14
937 * @arg @ref LL_FLASH_LATENCY_15
938 */
LL_FLASH_GetLatency(void)939 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
940 {
941 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
942 }
943
944 /**
945 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
946 * @note Flash memory can be put in power-down mode only when the code is executed
947 * from RAM
948 * @note Flash must not be accessed when power down is enabled
949 * @note Flash must not be put in power-down while a program or an erase operation
950 * is on-going
951 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
952 * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n
953 * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown
954 * @retval None
955 */
LL_FLASH_EnableRunPowerDown(void)956 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
957 {
958 /* Following values must be written consecutively to unlock the RUN_PD bit in
959 FLASH_ACR */
960 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_1);
961 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_2);
962
963 /*Request to enter flash in power mode */
964 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ);
965 }
966
967 /**
968 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
969 * @note Flash must not be put in power-down while a program or an erase operation
970 * is on-going
971 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
972 * @retval None
973 */
LL_FLASH_EnableSleepPowerDown(void)974 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
975 {
976 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
977 }
978
979 /**
980 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
981 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
982 * @retval None
983 */
LL_FLASH_DisableSleepPowerDown(void)984 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
985 {
986 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
987 }
988
989 /**
990 * @brief Return the Unique Device Number
991 * @retval Values between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
992 */
LL_FLASH_GetUDN(void)993 __STATIC_INLINE uint32_t LL_FLASH_GetUDN(void)
994 {
995 return (READ_REG(*((uint32_t *)UID64_BASE)));
996 }
997
998 /**
999 * @brief Return the Device ID
1000 * For STM32WBA52xx devices, the device ID is 0x2A
1001 * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x2A)
1002 */
LL_FLASH_GetDeviceID(void)1003 __STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void)
1004 {
1005 return ((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU);
1006 }
1007
1008 /**
1009 * @brief Return the ST Company ID
1010 * @note For STM32WBAxxxx devices, the ST Company ID is 0x0080E1
1011 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Company ID is 0x0080E1)
1012 */
LL_FLASH_GetSTCompanyID(void)1013 __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void)
1014 {
1015 return (((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U) & 0x00FFFFFFU);
1016 }
1017 /**
1018 * @}
1019 */
1020
1021
1022 /** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS SYSCFG ERASE MEMORIE STATUS
1023 * @{
1024 */
1025
1026 /**
1027 * @brief Clear Status of End of Erase for ICACHE and PKA RAMs
1028 * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus
1029 * @retval None
1030 */
LL_SYSCFG_ClearEraseEndStatus(void)1031 __STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void)
1032 {
1033 SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE);
1034 }
1035
1036 /**
1037 * @brief Get Status of End of Erase for ICACHE and PKA RAMs
1038 * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus
1039 * @retval Returned value can be one of the following values:
1040 * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
1041 * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
1042 */
LL_SYSCFG_GetEraseEndStatus(void)1043 __STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void)
1044 {
1045 return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE));
1046 }
1047
1048
1049 /**
1050 * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
1051 * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus
1052 * @retval None
1053 */
LL_SYSCFG_ClearEraseAfterResetStatus(void)1054 __STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void)
1055 {
1056 SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR);
1057 }
1058
1059 /**
1060 * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
1061 * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus
1062 * @retval Returned value can be one of the following values:
1063 * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
1064 * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
1065 */
LL_SYSCFG_GetEraseAfterResetStatus(void)1066 __STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void)
1067 {
1068 return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR));
1069 }
1070 /**
1071 * @}
1072 */
1073
1074 /**
1075 * @}
1076 */
1077
1078 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1079
1080 /**
1081 * @}
1082 */
1083
1084 #ifdef __cplusplus
1085 }
1086 #endif
1087
1088 #endif /* STM32WBAxx_LL_SYSTEM_H */
1089
1090
