1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32F2xx_LL_BUS_H
37 #define __STM32F2xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32f2xx.h"
45
46 /** @addtogroup STM32F2xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /* Private macros ------------------------------------------------------------*/
60 /* Exported types ------------------------------------------------------------*/
61 /* Exported constants --------------------------------------------------------*/
62 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
63 * @{
64 */
65
66 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
67 * @{
68 */
69 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
70 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
71 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
72 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
73 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
74 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
75 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
76 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
77 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
78 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
79 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
80 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
81 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
82 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
83 #if defined(ETH)
84 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
85 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
86 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
87 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
88 #endif /* ETH */
89 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
90 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
91 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
92 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
93 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
94 /**
95 * @}
96 */
97
98 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
99 * @{
100 */
101 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
102 #if defined(DCMI)
103 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
104 #endif /* DCMI */
105 #if defined(CRYP)
106 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
107 #endif /* CRYP */
108 #if defined(HASH)
109 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
110 #endif /* HASH */
111 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
112 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
113 /**
114 * @}
115 */
116
117 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
118 * @{
119 */
120 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
121 #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
122 /**
123 * @}
124 */
125
126 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
127 * @{
128 */
129 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
130 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
131 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
132 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
133 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
134 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
135 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
136 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
137 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
138 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
139 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
140 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
141 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
142 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
143 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
144 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
145 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
146 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
147 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
148 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
149 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
150 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
151 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
152 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
153 /**
154 * @}
155 */
156
157 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
158 * @{
159 */
160 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
161 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
162 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
163 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
164 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
165 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
166 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
167 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
168 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
169 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
170 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
171 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
172 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
173 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
174 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
175 /**
176 * @}
177 */
178
179 /**
180 * @}
181 */
182
183 /* Exported macro ------------------------------------------------------------*/
184 /* Exported functions --------------------------------------------------------*/
185 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
186 * @{
187 */
188
189 /** @defgroup BUS_LL_EF_AHB1 AHB1
190 * @{
191 */
192
193 /**
194 * @brief Enable AHB1 peripherals clock.
195 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
196 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
197 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
198 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
199 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
200 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
201 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
202 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
203 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
204 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
205 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
206 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
207 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
208 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
209 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
210 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
211 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
212 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
213 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
214 * @param Periphs This parameter can be a combination of the following values:
215 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
216 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
217 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
218 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
219 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
220 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
221 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
222 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
223 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
224 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
225 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
226 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
227 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
228 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
229 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
230 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
231 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
232 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
233 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
234 *
235 * (*) value not defined in all devices.
236 * @retval None
237 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)238 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
239 {
240 __IO uint32_t tmpreg;
241 SET_BIT(RCC->AHB1ENR, Periphs);
242 /* Delay after an RCC peripheral clock enabling */
243 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
244 (void)tmpreg;
245 }
246
247 /**
248 * @brief Check if AHB1 peripheral clock is enabled or not
249 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
250 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
251 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
252 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
253 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
254 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
255 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
256 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
257 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
258 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
259 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
260 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
261 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
262 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
263 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
264 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
265 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
266 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
267 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
268 * @param Periphs This parameter can be a combination of the following values:
269 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
270 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
271 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
272 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
273 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
274 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
275 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
276 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
277 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
278 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
279 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
280 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
281 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
282 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
283 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
284 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
285 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
286 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
287 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
288 *
289 * (*) value not defined in all devices.
290 * @retval State of Periphs (1 or 0).
291 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)292 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
293 {
294 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
295 }
296
297 /**
298 * @brief Disable AHB1 peripherals clock.
299 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
300 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
301 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
302 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
303 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
304 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
305 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
306 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
307 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
308 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
309 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
310 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
311 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
312 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
313 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
314 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
315 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
316 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
317 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
318 * @param Periphs This parameter can be a combination of the following values:
319 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
320 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
321 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
322 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
323 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
324 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
325 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
326 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
327 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
328 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
329 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
330 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
331 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
332 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
333 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
334 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
335 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
336 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
337 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
338 *
339 * (*) value not defined in all devices.
340 * @retval None
341 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)342 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
343 {
344 CLEAR_BIT(RCC->AHB1ENR, Periphs);
345 }
346
347 /**
348 * @brief Force AHB1 peripherals reset.
349 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
350 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
351 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
352 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
353 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
354 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
355 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
356 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
357 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
358 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
359 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
360 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
361 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
362 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
363 * @param Periphs This parameter can be a combination of the following values:
364 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
365 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
366 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
367 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
368 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
369 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
370 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
371 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
372 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
373 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
374 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
375 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
376 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
377 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
378 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
379 *
380 * (*) value not defined in all devices.
381 * @retval None
382 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)383 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
384 {
385 SET_BIT(RCC->AHB1RSTR, Periphs);
386 }
387
388 /**
389 * @brief Release AHB1 peripherals reset.
390 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
391 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
392 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
393 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
394 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
395 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
396 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
397 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
398 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
399 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
400 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
401 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
402 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
403 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
404 * @param Periphs This parameter can be a combination of the following values:
405 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
406 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
407 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
410 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
411 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
412 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
413 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
414 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
415 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
416 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
417 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
418 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
419 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
420 *
421 * (*) value not defined in all devices.
422 * @retval None
423 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)424 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
425 {
426 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
427 }
428
429 /**
430 * @brief Enable AHB1 peripheral clocks in low-power mode
431 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
432 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
433 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
434 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
435 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
436 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
437 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
438 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
439 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
440 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
441 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
442 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
443 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
444 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
445 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
446 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
447 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
448 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
449 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
450 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
451 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
452 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
453 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
454 * @param Periphs This parameter can be a combination of the following values:
455 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
456 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
457 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
458 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
459 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
460 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
461 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
462 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
463 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
464 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
465 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
466 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
467 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
468 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
469 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
470 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
471 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
472 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
473 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
474 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
475 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
476 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
477 *
478 * (*) value not defined in all devices.
479 * @retval None
480 */
LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)481 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
482 {
483 __IO uint32_t tmpreg;
484 SET_BIT(RCC->AHB1LPENR, Periphs);
485 /* Delay after an RCC peripheral clock enabling */
486 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
487 (void)tmpreg;
488 }
489
490 /**
491 * @brief Disable AHB1 peripheral clocks in low-power mode
492 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
493 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
494 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
495 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
496 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
497 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
498 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
499 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
500 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
501 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
502 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
503 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
504 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
505 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
506 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
507 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
508 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
509 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
510 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
511 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
512 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
513 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
514 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
515 * @param Periphs This parameter can be a combination of the following values:
516 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
517 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
518 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
519 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
520 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
521 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
522 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
523 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
524 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
525 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
526 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
527 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
528 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
529 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
530 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
531 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
532 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
533 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
534 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
535 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
536 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
537 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
538 *
539 * (*) value not defined in all devices.
540 * @retval None
541 */
LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)542 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
543 {
544 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
545 }
546
547 /**
548 * @}
549 */
550
551 /** @defgroup BUS_LL_EF_AHB2 AHB2
552 * @{
553 */
554
555 /**
556 * @brief Enable AHB2 peripherals clock.
557 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
558 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
559 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
560 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
561 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
562 * @param Periphs This parameter can be a combination of the following values:
563 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
564 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
565 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
566 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
567 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
568 *
569 * (*) value not defined in all devices.
570 * @retval None
571 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)572 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
573 {
574 __IO uint32_t tmpreg;
575 SET_BIT(RCC->AHB2ENR, Periphs);
576 /* Delay after an RCC peripheral clock enabling */
577 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
578 (void)tmpreg;
579 }
580
581 /**
582 * @brief Check if AHB2 peripheral clock is enabled or not
583 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
584 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
585 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
586 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
587 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
588 * @param Periphs This parameter can be a combination of the following values:
589 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
590 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
591 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
592 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
593 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
594 *
595 * (*) value not defined in all devices.
596 * @retval State of Periphs (1 or 0).
597 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)598 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
599 {
600 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
601 }
602
603 /**
604 * @brief Disable AHB2 peripherals clock.
605 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
606 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
607 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
608 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
609 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
610 * @param Periphs This parameter can be a combination of the following values:
611 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
612 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
613 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
614 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
615 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
616 *
617 * (*) value not defined in all devices.
618 * @retval None
619 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)620 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
621 {
622 CLEAR_BIT(RCC->AHB2ENR, Periphs);
623 }
624
625 /**
626 * @brief Force AHB2 peripherals reset.
627 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
628 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
629 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
630 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
631 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
632 * @param Periphs This parameter can be a combination of the following values:
633 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
634 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
635 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
636 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
637 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
638 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
639 *
640 * (*) value not defined in all devices.
641 * @retval None
642 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)643 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
644 {
645 SET_BIT(RCC->AHB2RSTR, Periphs);
646 }
647
648 /**
649 * @brief Release AHB2 peripherals reset.
650 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
651 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
652 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
653 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
654 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
655 * @param Periphs This parameter can be a combination of the following values:
656 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
657 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
658 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
659 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
660 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
661 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
662 *
663 * (*) value not defined in all devices.
664 * @retval None
665 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)666 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
667 {
668 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
669 }
670
671 /**
672 * @brief Enable AHB2 peripheral clocks in low-power mode
673 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
674 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
675 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
676 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
677 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
678 * @param Periphs This parameter can be a combination of the following values:
679 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
680 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
681 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
682 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
683 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
684 *
685 * (*) value not defined in all devices.
686 * @retval None
687 */
LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)688 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
689 {
690 __IO uint32_t tmpreg;
691 SET_BIT(RCC->AHB2LPENR, Periphs);
692 /* Delay after an RCC peripheral clock enabling */
693 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
694 (void)tmpreg;
695 }
696
697 /**
698 * @brief Disable AHB2 peripheral clocks in low-power mode
699 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
700 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
701 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
702 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
703 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
704 * @param Periphs This parameter can be a combination of the following values:
705 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
706 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
707 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
708 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
709 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
710 *
711 * (*) value not defined in all devices.
712 * @retval None
713 */
LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)714 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
715 {
716 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
717 }
718
719 /**
720 * @}
721 */
722
723 /** @defgroup BUS_LL_EF_AHB3 AHB3
724 * @{
725 */
726
727 /**
728 * @brief Enable AHB3 peripherals clock.
729 * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock
730 * @param Periphs This parameter can be a combination of the following values:
731 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
732 * @retval None
733 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)734 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
735 {
736 __IO uint32_t tmpreg;
737 SET_BIT(RCC->AHB3ENR, Periphs);
738 /* Delay after an RCC peripheral clock enabling */
739 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
740 (void)tmpreg;
741 }
742
743 /**
744 * @brief Check if AHB3 peripheral clock is enabled or not
745 * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock
746 * @param Periphs This parameter can be a combination of the following values:
747 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
748 * @retval State of Periphs (1 or 0).
749 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)750 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
751 {
752 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
753 }
754
755 /**
756 * @brief Disable AHB3 peripherals clock.
757 * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock
758 * @param Periphs This parameter can be a combination of the following values:
759 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
760 * @retval None
761 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)762 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
763 {
764 CLEAR_BIT(RCC->AHB3ENR, Periphs);
765 }
766
767 /**
768 * @brief Force AHB3 peripherals reset.
769 * @rmtoll AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset
770 * @param Periphs This parameter can be a combination of the following values:
771 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
772 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
773 * @retval None
774 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)775 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
776 {
777 SET_BIT(RCC->AHB3RSTR, Periphs);
778 }
779
780 /**
781 * @brief Release AHB3 peripherals reset.
782 * @rmtoll AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset
783 * @param Periphs This parameter can be a combination of the following values:
784 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
785 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
786 * @retval None
787 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)788 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
789 {
790 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
791 }
792
793 /**
794 * @brief Enable AHB3 peripheral clocks in low-power mode
795 * @rmtoll AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower
796 * @param Periphs This parameter can be a combination of the following values:
797 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
798 * @retval None
799 */
LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)800 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
801 {
802 __IO uint32_t tmpreg;
803 SET_BIT(RCC->AHB3LPENR, Periphs);
804 /* Delay after an RCC peripheral clock enabling */
805 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
806 (void)tmpreg;
807 }
808
809 /**
810 * @brief Disable AHB3 peripheral clocks in low-power mode
811 * @rmtoll AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower
812 * @param Periphs This parameter can be a combination of the following values:
813 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
814 * @retval None
815 */
LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)816 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
817 {
818 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
819 }
820
821 /**
822 * @}
823 */
824
825 /** @defgroup BUS_LL_EF_APB1 APB1
826 * @{
827 */
828
829 /**
830 * @brief Enable APB1 peripherals clock.
831 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
832 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
833 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
834 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
835 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
836 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
837 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
838 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
839 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
840 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
841 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
842 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
843 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
844 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
845 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
846 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
847 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
848 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
849 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
850 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
851 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
852 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
853 * APB1ENR DACEN LL_APB1_GRP1_EnableClock
854 * @param Periphs This parameter can be a combination of the following values:
855 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
856 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
857 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
858 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
859 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
860 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
861 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
862 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
863 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
864 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
865 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
866 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
867 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
868 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
869 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
870 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
871 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
872 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
873 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
874 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
875 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
876 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
877 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
878 * @retval None
879 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)880 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
881 {
882 __IO uint32_t tmpreg;
883 SET_BIT(RCC->APB1ENR, Periphs);
884 /* Delay after an RCC peripheral clock enabling */
885 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
886 (void)tmpreg;
887 }
888
889 /**
890 * @brief Check if APB1 peripheral clock is enabled or not
891 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
892 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
893 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
894 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
895 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
896 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
897 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
898 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
899 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
900 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
901 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
902 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
903 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
904 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
905 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
906 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
907 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
908 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
909 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
910 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
911 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
912 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
913 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock
914 * @param Periphs This parameter can be a combination of the following values:
915 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
916 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
917 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
918 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
919 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
920 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
921 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
922 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
923 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
924 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
925 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
926 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
927 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
928 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
929 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
930 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
931 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
932 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
933 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
934 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
935 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
936 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
937 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
938 * @retval State of Periphs (1 or 0).
939 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)940 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
941 {
942 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
943 }
944
945 /**
946 * @brief Disable APB1 peripherals clock.
947 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
948 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
949 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
950 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
951 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
952 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
953 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
954 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
955 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
956 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
957 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
958 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
959 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
960 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
961 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
962 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
963 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
964 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
965 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
966 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
967 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
968 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
969 * APB1ENR DACEN LL_APB1_GRP1_DisableClock
970 * @param Periphs This parameter can be a combination of the following values:
971 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
972 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
973 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
974 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
975 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
976 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
977 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
978 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
979 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
980 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
981 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
982 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
983 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
984 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
985 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
986 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
987 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
988 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
989 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
990 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
991 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
992 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
993 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
994 * @retval None
995 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)996 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
997 {
998 CLEAR_BIT(RCC->APB1ENR, Periphs);
999 }
1000
1001 /**
1002 * @brief Force APB1 peripherals reset.
1003 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1004 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1005 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1006 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1007 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1008 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1009 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1010 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1011 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1012 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
1013 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1014 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1015 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
1016 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
1017 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
1018 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
1019 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1020 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1021 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1022 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
1023 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
1024 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
1025 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset
1026 * @param Periphs This parameter can be a combination of the following values:
1027 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1028 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1029 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1030 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1031 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1033 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1034 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1035 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1036 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1037 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1038 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1039 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1040 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1041 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1042 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1043 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1044 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1045 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1046 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1047 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1048 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
1049 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1050 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1051 * @retval None
1052 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1053 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1054 {
1055 SET_BIT(RCC->APB1RSTR, Periphs);
1056 }
1057
1058 /**
1059 * @brief Release APB1 peripherals reset.
1060 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1061 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1062 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1063 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1064 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1065 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1066 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
1067 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
1068 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
1069 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
1070 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1071 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1072 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1073 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1074 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1075 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1076 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1077 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1078 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
1079 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
1080 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
1081 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
1082 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset
1083 * @param Periphs This parameter can be a combination of the following values:
1084 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1085 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1086 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1087 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1088 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1089 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1090 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1091 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1092 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1093 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1094 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1095 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1096 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1097 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1098 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1099 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1100 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1101 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1102 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1103 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1104 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1105 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
1106 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1107 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1108 * @retval None
1109 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1110 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1111 {
1112 CLEAR_BIT(RCC->APB1RSTR, Periphs);
1113 }
1114
1115 /**
1116 * @brief Enable APB1 peripheral clocks in low-power mode
1117 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1118 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1119 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1120 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1121 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
1122 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1123 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
1124 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
1125 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
1126 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
1127 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1128 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1129 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1130 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1131 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1132 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1133 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1134 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1135 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1136 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1137 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1138 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
1139 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower
1140 * @param Periphs This parameter can be a combination of the following values:
1141 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1142 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1143 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1144 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1145 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1146 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1147 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1148 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1149 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1150 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1151 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1152 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1153 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1154 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1155 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1156 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1157 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1158 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1159 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1160 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1161 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
1162 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1163 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1164 * @retval None
1165 */
LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)1166 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
1167 {
1168 __IO uint32_t tmpreg;
1169 SET_BIT(RCC->APB1LPENR, Periphs);
1170 /* Delay after an RCC peripheral clock enabling */
1171 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
1172 (void)tmpreg;
1173 }
1174
1175 /**
1176 * @brief Disable APB1 peripheral clocks in low-power mode
1177 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1178 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1179 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1180 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1181 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
1182 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1183 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
1184 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
1185 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
1186 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
1187 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1188 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1189 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1190 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1191 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1192 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1193 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1194 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1195 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1196 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1197 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1198 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
1199 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower
1200 * @param Periphs This parameter can be a combination of the following values:
1201 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1202 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1203 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1204 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1205 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1206 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1207 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1208 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1209 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1210 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1211 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1212 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1213 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1214 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1215 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1216 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1217 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1218 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1219 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1220 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1221 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
1222 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1223 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1224 * @retval None
1225 */
LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)1226 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
1227 {
1228 CLEAR_BIT(RCC->APB1LPENR, Periphs);
1229 }
1230
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup BUS_LL_EF_APB2 APB2
1236 * @{
1237 */
1238
1239 /**
1240 * @brief Enable APB2 peripherals clock.
1241 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1242 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1243 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1244 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
1245 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
1246 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
1247 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
1248 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
1249 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1250 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1251 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1252 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
1253 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock
1254 * @param Periphs This parameter can be a combination of the following values:
1255 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1256 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1257 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1258 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1259 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1260 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1261 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1262 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
1263 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1264 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1265 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1266 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1267 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1268 * @retval None
1269 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1270 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1271 {
1272 __IO uint32_t tmpreg;
1273 SET_BIT(RCC->APB2ENR, Periphs);
1274 /* Delay after an RCC peripheral clock enabling */
1275 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1276 (void)tmpreg;
1277 }
1278
1279 /**
1280 * @brief Check if APB2 peripheral clock is enabled or not
1281 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1282 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1283 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1284 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
1285 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
1286 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
1287 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
1288 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
1289 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1290 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1291 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1292 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
1293 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock
1294 * @param Periphs This parameter can be a combination of the following values:
1295 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1296 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1297 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1298 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1299 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1300 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1301 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1302 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
1303 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1304 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1305 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1306 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1307 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1308 * @retval State of Periphs (1 or 0).
1309 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1310 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1311 {
1312 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
1313 }
1314
1315 /**
1316 * @brief Disable APB2 peripherals clock.
1317 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1318 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1319 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1320 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
1321 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
1322 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
1323 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
1324 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
1325 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1326 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1327 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
1328 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
1329 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock
1330 * @param Periphs This parameter can be a combination of the following values:
1331 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1332 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1333 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1334 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1335 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1336 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1337 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1338 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
1339 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1340 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1341 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1342 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1343 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1344 * @retval None
1345 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1346 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1347 {
1348 CLEAR_BIT(RCC->APB2ENR, Periphs);
1349 }
1350
1351 /**
1352 * @brief Force APB2 peripherals reset.
1353 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1354 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1355 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1356 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
1357 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1358 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
1359 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1360 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1361 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
1362 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
1363 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset
1364 * @param Periphs This parameter can be a combination of the following values:
1365 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1366 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1367 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1368 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1369 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1370 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1371 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
1372 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1373 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1374 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1375 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1376 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1377 * @retval None
1378 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1379 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1380 {
1381 SET_BIT(RCC->APB2RSTR, Periphs);
1382 }
1383
1384 /**
1385 * @brief Release APB2 peripherals reset.
1386 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1387 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1388 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1389 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
1390 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1391 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
1392 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1393 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1394 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
1395 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
1396 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset
1397 * @param Periphs This parameter can be a combination of the following values:
1398 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1399 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1400 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1401 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1402 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1403 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1404 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
1405 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1406 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1407 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1408 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1409 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1410 * @retval None
1411 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1412 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1413 {
1414 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1415 }
1416
1417 /**
1418 * @brief Enable APB2 peripheral clocks in low-power mode
1419 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1420 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
1421 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1422 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1423 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1424 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1425 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
1426 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
1427 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1428 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
1429 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1430 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1431 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower
1432 * @param Periphs This parameter can be a combination of the following values:
1433 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1434 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1435 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1436 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1437 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1438 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1439 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1440 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1441 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
1442 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1443 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1444 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1445 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1446 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1447 * @retval None
1448 */
LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)1449 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
1450 {
1451 __IO uint32_t tmpreg;
1452 SET_BIT(RCC->APB2LPENR, Periphs);
1453 /* Delay after an RCC peripheral clock enabling */
1454 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
1455 (void)tmpreg;
1456 }
1457
1458 /**
1459 * @brief Disable APB2 peripheral clocks in low-power mode
1460 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1461 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
1462 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1463 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
1464 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1465 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1466 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
1467 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
1468 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1469 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
1470 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
1471 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
1472 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower
1473 * @param Periphs This parameter can be a combination of the following values:
1474 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1475 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1476 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1477 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1478 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1479 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1480 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1481 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
1482 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1483 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1484 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1485 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1486 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1487 * @retval None
1488 */
LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)1489 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
1490 {
1491 CLEAR_BIT(RCC->APB2LPENR, Periphs);
1492 }
1493
1494 /**
1495 * @}
1496 */
1497
1498 /**
1499 * @}
1500 */
1501
1502 /**
1503 * @}
1504 */
1505
1506 #endif /* defined(RCC) */
1507
1508 /**
1509 * @}
1510 */
1511
1512 #ifdef __cplusplus
1513 }
1514 #endif
1515
1516 #endif /* __STM32F2xx_LL_BUS_H */
1517
1518
