1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### RCC Limitations #####
20 ==============================================================================
21 [..]
22 A delay between an RCC peripheral clock enable and the effective peripheral
23 enabling should be taken into account in order to manage the peripheral read/write
24 from/to registers.
25 (+) This delay depends on the peripheral mapping.
26 (++) AHB , APB peripherals, 1 dummy read is necessary
27
28 [..]
29 Workarounds:
30 (#) For AHB , APB peripherals, a dummy read to the peripheral register has been
31 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
32
33 @endverbatim
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32WBAxx_LL_BUS_H
39 #define STM32WBAxx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32wbaxx.h"
47
48 /** @addtogroup STM32WBAxx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60 /* Private constants ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
74 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
75 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
76 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
77 #define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN
78 #if defined(GTZC_TZSC)
79 #define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN
80 #endif /* GTZC_TZSC */
81 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN
82 /**
83 * @}
84 */
85
86 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
87 * @{
88 */
89 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
90 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
91 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
92 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
93 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
94 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
95 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
96 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
97 #if defined(SAES)
98 #define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR_SAESEN
99 #endif /* SAES */
100 #define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN
101 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN
102 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR_SRAM2EN
103 /**
104 * @}
105 */
106
107 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
108 * @{
109 */
110 #define LL_AHB4_GRP1_PERIPH_ALL 0xFFFFFFFFU
111 #define LL_AHB4_GRP1_PERIPH_PWR RCC_AHB4ENR_PWREN
112 #define LL_AHB4_GRP1_PERIPH_ADC4 RCC_AHB4ENR_ADC4EN
113 /**
114 * @}
115 */
116
117 /** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH AHB5 GRP1 PERIPH
118 * @{
119 */
120 #define LL_AHB5_GRP1_PERIPH_ALL 0xFFFFFFFFU
121 #define LL_AHB5_GRP1_PERIPH_RADIO RCC_AHB5ENR_RADIOEN
122 /**
123 * @}
124 */
125
126 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
127 * @{
128 */
129 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
130 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
131 #if defined(TIM3)
132 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
133 #endif /* TIM3 */
134 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
135 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
136 #if defined(I2C1)
137 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
138 #endif /* I2C1 */
139 /**
140 * @}
141 */
142
143
144 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
145 * @{
146 */
147 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
148 #if defined(LPTIM2)
149 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
150 #endif /* LPTIM2 */
151 /**
152 * @}
153 */
154
155 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
156 * @{
157 */
158 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
159 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
160 #if defined(SPI1)
161 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
162 #endif /* SPI1 */
163 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
164 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
165 #if defined(TIM17)
166 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
167 #endif /* TIM17 */
168 #if defined(SAI1)
169 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
170 #endif /* SAI1 */
171 /**
172 * @}
173 */
174
175 /** @defgroup BUS_LL_EC_APB7_GRP1_PERIPH APB7 GRP1 PERIPH
176 * @{
177 */
178 #define LL_APB7_GRP1_PERIPH_ALL 0xFFFFFFFFU
179 #define LL_APB7_GRP1_PERIPH_SYSCFG RCC_APB7ENR_SYSCFGEN
180 #define LL_APB7_GRP1_PERIPH_SPI3 RCC_APB7ENR_SPI3EN
181 #define LL_APB7_GRP1_PERIPH_LPUART1 RCC_APB7ENR_LPUART1EN
182 #define LL_APB7_GRP1_PERIPH_I2C3 RCC_APB7ENR_I2C3EN
183 #define LL_APB7_GRP1_PERIPH_LPTIM1 RCC_APB7ENR_LPTIM1EN
184 #if defined(COMP1)
185 #define LL_APB7_GRP1_PERIPH_COMP RCC_APB7ENR_COMPEN
186 #endif /* COMP1 */
187 #define LL_APB7_GRP1_PERIPH_RTCAPB RCC_APB7ENR_RTCAPBEN
188 /**
189 * @}
190 */
191
192 /**
193 * @}
194 */
195
196 /* Exported macros -----------------------------------------------------------*/
197 /* Exported functions --------------------------------------------------------*/
198 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
199 * @{
200 */
201
202 /** @defgroup BUS_LL_EF_AHB1 AHB1
203 * @{
204 */
205 /**
206 * @brief Enable AHB1 peripherals clock.
207 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n
208 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
209 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
210 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
211 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n
212 * AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n
213 * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock
214 * @param Periphs This parameter can be a combination of the following values:
215 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
216 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
217 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
218 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
219 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
220 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
221 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
222 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
223 *
224 * (*) value not defined in all devices.
225 * @retval None
226 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)227 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
228 {
229 __IO uint32_t tmpreg;
230 SET_BIT(RCC->AHB1ENR, Periphs);
231 /* Delay after an RCC peripheral clock enabling */
232 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
233 (void)tmpreg;
234 }
235
236 /**
237 * @brief Check if AHB1 peripheral clock is enabled or not
238 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n
239 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
240 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
241 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
242 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n
243 * AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n
244 * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock
245 * @param Periphs This parameter can be a combination of the following values:
246 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
247 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
248 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
249 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
250 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
251 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
252 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
253 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
254 *
255 * (*) value not defined in all devices.
256 * @retval State of Periphs (1 or 0).
257 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)258 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
259 {
260 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
261 }
262
263 /**
264 * @brief Disable AHB1 peripherals clock.
265 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n
266 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
267 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
268 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
269 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n
270 * AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n
271 * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock
272 * @param Periphs This parameter can be a combination of the following values:
273 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
274 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
275 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
276 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
277 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
278 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
279 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
280 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
281 *
282 * (*) value not defined in all devices.
283 * @retval None
284 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)285 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
286 {
287 CLEAR_BIT(RCC->AHB1ENR, Periphs);
288 }
289
290 /**
291 * @brief Force AHB1 peripherals reset.
292 * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n
293 * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n
294 * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n
295 * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset
296 * @param Periphs This parameter can be a combination of the following values:
297 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
298 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
299 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
300 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
301 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
302 * @retval None
303 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)304 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
305 {
306 SET_BIT(RCC->AHB1RSTR, Periphs);
307 }
308
309 /**
310 * @brief Release AHB1 peripherals reset.
311 * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n
312 * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n
313 * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n
314 * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n
315 * @param Periphs This parameter can be a combination of the following values:
316 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
317 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
318 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
319 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
320 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
321 * @retval None
322 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)323 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
324 {
325 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
326 }
327
328 /**
329 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
330 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
331 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
332 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
333 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
334 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
335 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
336 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep
337 * @param Periphs This parameter can be a combination of the following values:
338 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
339 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
340 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
341 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
342 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
343 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
344 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
345 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
346 *
347 * (*) value not defined in all devices.
348 * @retval None
349 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)350 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
351 {
352 __IO uint32_t tmpreg;
353 SET_BIT(RCC->AHB1SMENR, Periphs);
354 /* Delay after an RCC peripheral clock enabling */
355 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
356 (void)tmpreg;
357 }
358
359 /**
360 * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not
361 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
362 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
363 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
364 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
365 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
366 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
367 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep
368 * @param Periphs This parameter can be a combination of the following values:
369 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
370 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
371 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
372 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
373 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
374 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
375 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
376 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
377 *
378 * (*) value not defined in all devices.
379 * @retval State of Periphs (1 or 0).
380 */
LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)381 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
382 {
383 return ((READ_BIT(RCC->AHB1SMENR, Periphs) == Periphs) ? 1UL : 0UL);
384 }
385
386 /**
387 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
388 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
389 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
390 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
391 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
392 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
393 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
394 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep
395 * @param Periphs This parameter can be a combination of the following values:
396 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
397 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
398 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
399 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
400 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
401 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
402 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
403 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
404 *
405 * (*) value not defined in all devices.
406 * @retval None
407 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)408 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
409 {
410 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
411 }
412
413 /**
414 * @}
415 */
416
417 /** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
418 * @{
419 */
420 /**
421 * @brief Enable AHB2 peripherals clock.
422 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
423 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
424 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
425 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
426 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
427 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
428 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
429 * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n
430 * AHB2ENR SAESEN LL_AHB2_GRP1_EnableClock\n
431 * AHB2ENR SRAM2EN LL_AHB2_GRP1_EnableClock
432 * @param Periphs This parameter can be a combination of the following values:
433 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
434 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
435 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
436 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
437 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
438 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
439 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
440 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
441 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
442 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
443 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
444 *
445 * (*) value not defined in all devices.
446 * @retval None
447 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)448 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
449 {
450 __IO uint32_t tmpreg;
451 SET_BIT(RCC->AHB2ENR, Periphs);
452 /* Delay after an RCC peripheral clock enabling */
453 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
454 (void)tmpreg;
455 }
456
457 /**
458 * @brief Check if AHB2 peripheral clock is enabled or not
459 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
460 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
461 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
462 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
463 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
464 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
465 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
466 * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n
467 * AHB2ENR SAESEN LL_AHB2_GRP1_IsEnabledClock\n
468 * AHB2ENR SRAM2EN LL_AHB2_GRP1_IsEnabledClock
469 * @param Periphs This parameter can be a combination of the following values:
470 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
471 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
472 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
473 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
474 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
475 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
476 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
477 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
478 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
479 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
480 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
481 *
482 * (*) value not defined in all devices.
483 * @retval State of Periphs (1 or 0).
484 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)485 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
486 {
487 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
488 }
489
490 /**
491 * @brief Disable AHB2 peripherals clock.
492 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
493 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
494 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
495 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
496 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
497 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
498 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
499 * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n
500 * AHB2ENR SAESEN LL_AHB2_GRP1_DisableClock\n
501 * AHB2ENR SRAM2EN LL_AHB2_GRP1_DisableClock
502 * @param Periphs This parameter can be a combination of the following values:
503 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
504 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
505 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
506 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
507 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
508 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
509 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
510 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
511 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
512 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
513 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
514 *
515 * (*) value not defined in all devices.
516 * @retval None
517 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)518 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
519 {
520 CLEAR_BIT(RCC->AHB2ENR, Periphs);
521 }
522
523 /**
524 * @brief Force AHB2 peripherals reset.
525 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
526 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
527 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
528 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
529 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
530 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
531 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
532 * AHB2RSTR PKARST LL_AHB2_GRP1_ForceReset\n
533 * AHB2RSTR SAESRST LL_AHB2_GRP1_ForceReset
534 * @param Periphs This parameter can be a combination of the following values:
535 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
536 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
537 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
538 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
539 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
540 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
541 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
542 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
543 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
544 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
545 *
546 * (*) value not defined in all devices.
547 * @retval None
548 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)549 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
550 {
551 SET_BIT(RCC->AHB2RSTR, Periphs);
552 }
553
554 /**
555 * @brief Release AHB2 peripherals reset.
556 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
557 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
558 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
559 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
560 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
561 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
562 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
563 * AHB2RSTR PKARST LL_AHB2_GRP1_ReleaseReset\n
564 * AHB2RSTR SAESRST LL_AHB2_GRP1_ReleaseReset
565 * @param Periphs This parameter can be a combination of the following values:
566 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
567 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
568 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
569 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
570 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
571 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
572 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
573 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
574 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
575 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
576 *
577 * (*) value not defined in all devices.
578 * @retval None
579 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)580 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
581 {
582 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
583 }
584
585 /**
586 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
587 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
588 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
589 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
590 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
591 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
592 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
593 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
594 * AHB2SMENR PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
595 * AHB2SMENR SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
596 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep
597 * @param Periphs This parameter can be a combination of the following values:
598 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
599 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
600 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
601 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
602 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
603 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
604 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
605 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
606 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
607 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
608 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
609 *
610 * (*) value not defined in all devices.
611 * @retval None
612 */
LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)613 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
614 {
615 __IO uint32_t tmpreg;
616 SET_BIT(RCC->AHB2SMENR, Periphs);
617 /* Delay after an RCC peripheral clock enabling */
618 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
619 (void)tmpreg;
620 }
621
622 /**
623 * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not
624 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
625 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
626 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
627 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
628 * AHB2SMENR AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
629 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
630 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
631 * AHB2SMENR PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
632 * AHB2SMENR SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
633 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep
634 * @param Periphs This parameter can be a combination of the following values:
635 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
636 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
637 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
638 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
639 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
640 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
641 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
642 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
643 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
644 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
645 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
646 *
647 * (*) value not defined in all devices.
648 * @retval State of Periphs (1 or 0).
649 */
LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)650 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
651 {
652 return ((READ_BIT(RCC->AHB2SMENR, Periphs) == Periphs) ? 1UL : 0UL);
653 }
654
655 /**
656 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
657 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
658 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
659 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
660 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
661 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
662 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
663 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
664 * AHB2SMENR PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
665 * AHB2SMENR SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
666 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep
667 * @param Periphs This parameter can be a combination of the following values:
668 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
669 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
670 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
671 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
672 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
673 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
674 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
675 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
676 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
677 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES
678 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
679 * @retval None
680 */
LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)681 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
682 {
683 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
684 }
685
686 /**
687 * @}
688 */
689
690 /** @defgroup BUS_LL_EF_AHB4 AHB4
691 * @{
692 */
693 /**
694 * @brief Enable AHB4 peripherals clock.
695 * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_EnableClock\n
696 * AHB4ENR ADC4EN LL_AHB4_GRP1_EnableClock
697 * @param Periphs This parameter can be a combination of the following values:
698 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
699 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
700 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
701 * @retval None
702 */
LL_AHB4_GRP1_EnableClock(uint32_t Periphs)703 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
704 {
705 __IO uint32_t tmpreg;
706 SET_BIT(RCC->AHB4ENR, Periphs);
707 /* Delay after an RCC peripheral clock enabling */
708 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
709 (void)tmpreg;
710 }
711
712 /**
713 * @brief Check if AHB4 peripheral clock is enabled or not
714 * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_IsEnabledClock\n
715 * AHB4ENR ADC4EN LL_AHB4_GRP1_IsEnabledClock
716 * @param Periphs This parameter can be a combination of the following values:
717 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
718 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
719 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
720 * @retval State of Periphs (1 or 0).
721 */
LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)722 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
723 {
724 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL);
725 }
726
727 /**
728 * @brief Disable AHB4 peripherals clock.
729 * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_DisableClock\n
730 * AHB4ENR ADC4EN LL_AHB4_GRP1_DisableClock
731 * @param Periphs This parameter can be a combination of the following values:
732 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
733 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
734 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
735 * @retval None
736 */
LL_AHB4_GRP1_DisableClock(uint32_t Periphs)737 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
738 {
739 CLEAR_BIT(RCC->AHB4ENR, Periphs);
740 }
741
742 /**
743 * @brief Force AHB4 peripherals reset.
744 * @rmtoll AHB4RSTR ADC4RST LL_AHB4_GRP1_ForceReset
745 * @param Periphs This parameter can be a combination of the following values:
746 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
747 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
748 * @retval None
749 */
LL_AHB4_GRP1_ForceReset(uint32_t Periphs)750 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
751 {
752 SET_BIT(RCC->AHB4RSTR, Periphs);
753 }
754
755 /**
756 * @brief Release AHB4 peripherals reset.
757 * @rmtoll AHB4RSTR ADC4RST LL_AHB4_GRP1_ReleaseReset
758 * @param Periphs This parameter can be a combination of the following values:
759 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
760 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
761 * @retval None
762 */
LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)763 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
764 {
765 CLEAR_BIT(RCC->AHB4RSTR, Periphs);
766 }
767
768 /**
769 * @brief Enable AHB4 peripheral clocks in Sleep and Stop modes
770 * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_EnableClockStopSleep\n
771 * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_EnableClockStopSleep
772 * @param Periphs This parameter can be a combination of the following values:
773 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
774 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
775 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
776 * @retval None
777 */
LL_AHB4_GRP1_EnableClockStopSleep(uint32_t Periphs)778 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockStopSleep(uint32_t Periphs)
779 {
780 __IO uint32_t tmpreg;
781 SET_BIT(RCC->AHB4SMENR, Periphs);
782 /* Delay after an RCC peripheral clock enabling */
783 tmpreg = READ_BIT(RCC->AHB4SMENR, Periphs);
784 (void)tmpreg;
785 }
786
787 /**
788 * @brief Check if AHB4 peripheral clocks in Sleep and Stop modes is enabled or not
789 * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_IsEnabledClockStopSleep\n
790 * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_IsEnabledClockStopSleep
791 * @param Periphs This parameter can be a combination of the following values:
792 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
793 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
794 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
795 * @retval State of Periphs (1 or 0).
796 */
LL_AHB4_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)797 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
798 {
799 return ((READ_BIT(RCC->AHB4SMENR, Periphs) == Periphs) ? 1UL : 0UL);
800 }
801
802 /**
803 * @brief Disable AHB4 peripheral clocks in Sleep and Stop modes
804 * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_DisableClockStopSleep\n
805 * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_DisableClockStopSleep
806 * @param Periphs This parameter can be a combination of the following values:
807 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
808 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
809 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
810 * @retval None
811 */
LL_AHB4_GRP1_DisableClockStopSleep(uint32_t Periphs)812 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockStopSleep(uint32_t Periphs)
813 {
814 CLEAR_BIT(RCC->AHB4SMENR, Periphs);
815 }
816
817 /**
818 * @}
819 */
820
821 /** @defgroup BUS_LL_EF_AHB5 AHB5
822 * @{
823 */
824 /**
825 * @brief Enable AHB5 peripherals clock.
826 * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_EnableClock
827 * @param Periphs This parameter can be a combination of the following values:
828 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
829 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
830 * @retval None
831 */
LL_AHB5_GRP1_EnableClock(uint32_t Periphs)832 __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs)
833 {
834 __IO uint32_t tmpreg;
835 SET_BIT(RCC->AHB5ENR, Periphs);
836 /* Delay after an RCC peripheral clock enabling */
837 tmpreg = READ_BIT(RCC->AHB5ENR, Periphs);
838 (void)tmpreg;
839 }
840
841 /**
842 * @brief Check if AHB5 peripheral clock is enabled or not
843 * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_IsEnabledClock
844 * @param Periphs This parameter can be a combination of the following values:
845 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
846 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
847 * @retval State of Periphs (1 or 0).
848 */
LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)849 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)
850 {
851 return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL);
852 }
853
854 /**
855 * @brief Disable AHB5 peripherals clock.
856 * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_DisableClock
857 * @param Periphs This parameter can be a combination of the following values:
858 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
859 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
860 * @retval None
861 */
LL_AHB5_GRP1_DisableClock(uint32_t Periphs)862 __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs)
863 {
864 CLEAR_BIT(RCC->AHB5ENR, Periphs);
865 }
866
867 /**
868 * @brief Force AHB5 peripherals reset.
869 * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ForceReset
870 * @param Periphs This parameter can be a combination of the following values:
871 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
872 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
873 * @retval None
874 */
LL_AHB5_GRP1_ForceReset(uint32_t Periphs)875 __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs)
876 {
877 SET_BIT(RCC->AHB5RSTR, Periphs);
878 }
879
880 /**
881 * @brief Release AHB5 peripherals reset.
882 * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ReleaseReset
883 * @param Periphs This parameter can be a combination of the following values:
884 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
885 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
886 * @retval None
887 */
LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)888 __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)
889 {
890 CLEAR_BIT(RCC->AHB5RSTR, Periphs);
891 }
892
893 /**
894 * @brief Enable AHB5 peripheral clocks in Sleep and Stop modes
895 * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_EnableClockStopSleep
896 * @param Periphs This parameter can be a combination of the following values:
897 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
898 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
899 * @retval None
900 */
LL_AHB5_GRP1_EnableClockStopSleep(uint32_t Periphs)901 __STATIC_INLINE void LL_AHB5_GRP1_EnableClockStopSleep(uint32_t Periphs)
902 {
903 __IO uint32_t tmpreg;
904 SET_BIT(RCC->AHB5SMENR, Periphs);
905 /* Delay after an RCC peripheral clock enabling */
906 tmpreg = READ_BIT(RCC->AHB5SMENR, Periphs);
907 (void)tmpreg;
908 }
909
910 /**
911 * @brief Check if AHB5 peripheral clocks in Sleep and Stop modes is enabled or not
912 * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_IsEnabledClockStopSleep
913 * @param Periphs This parameter can be a combination of the following values:
914 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
915 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
916 * @retval State of Periphs (1 or 0).
917 */
LL_AHB5_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)918 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
919 {
920 return ((READ_BIT(RCC->AHB5SMENR, Periphs) == Periphs) ? 1UL : 0UL);
921 }
922
923 /**
924 * @brief Disable AHB5 peripheral clocks in Sleep and Stop modes
925 * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_DisableClockStopSleep
926 * @param Periphs This parameter can be a combination of the following values:
927 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
928 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
929 * @retval None
930 */
LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs)931 __STATIC_INLINE void LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs)
932 {
933 CLEAR_BIT(RCC->AHB5SMENR, Periphs);
934 }
935
936 /**
937 * @}
938 */
939
940 /** @defgroup BUS_LL_EF_APB1 APB1
941 * @{
942 */
943
944 /**
945 * @brief Enable APB1 peripherals clock.
946 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
947 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
948 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
949 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
950 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock
951 * @param Periphs This parameter can be a combination of the following values:
952 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
953 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
954 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
955 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
956 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
957 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
958 *
959 * (*) value not defined in all devices.
960 * @retval None
961 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)962 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
963 {
964 __IO uint32_t tmpreg;
965 SET_BIT(RCC->APB1ENR1, Periphs);
966 /* Delay after an RCC peripheral clock enabling */
967 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
968 (void)tmpreg;
969 }
970
971 /**
972 * @brief Enable APB1 peripherals clock.
973 * @rmtoll APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
974 * @param Periphs This parameter can be a combination of the following values:
975 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
976 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
977 * @retval None
978 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)979 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
980 {
981 __IO uint32_t tmpreg;
982 SET_BIT(RCC->APB1ENR2, Periphs);
983 /* Delay after an RCC peripheral clock enabling */
984 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
985 (void)tmpreg;
986 }
987
988 /**
989 * @brief Check if APB1 peripheral clock is enabled or not
990 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
991 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
992 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
993 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
994 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock
995 * @param Periphs This parameter can be a combination of the following values:
996 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
997 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
998 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
999 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1000 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1001 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1002 *
1003 * (*) value not defined in all devices.
1004 * @retval State of Periphs (1 or 0).
1005 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1006 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1007 {
1008 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
1009 }
1010
1011 /**
1012 * @brief Check if APB1 peripheral clock is enabled or not
1013 * @rmtoll APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
1014 * @param Periphs This parameter can be a combination of the following values:
1015 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1016 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1017 * @retval State of Periphs (1 or 0).
1018 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1019 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1020 {
1021 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1022 }
1023
1024 /**
1025 * @brief Disable APB1 peripherals clock.
1026 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1027 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1028 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1029 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock
1030 * @param Periphs This parameter can be a combination of the following values:
1031 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1033 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1034 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1035 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1036 *
1037 * (*) value not defined in all devices.
1038 * @retval None
1039 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1040 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1041 {
1042 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1043 }
1044
1045 /**
1046 * @brief Disable APB1 peripherals clock.
1047 * @rmtoll APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
1048 * @param Periphs This parameter can be a combination of the following values:
1049 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1050 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1051 * @retval None
1052 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1053 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1054 {
1055 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1056 }
1057
1058 /**
1059 * @brief Force APB1 peripherals reset.
1060 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1061 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1062 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1063 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset
1064 * @param Periphs This parameter can be a combination of the following values:
1065 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1066 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1067 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1068 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1069 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1070 *
1071 * (*) value not defined in all devices.
1072 * @retval None
1073 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1074 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1075 {
1076 SET_BIT(RCC->APB1RSTR1, Periphs);
1077 }
1078
1079 /**
1080 * @brief Force APB1 peripherals reset.
1081 * @rmtoll APB1RSTR2 LPTIM2RST LL_APB1_GRP2_DisableClock
1082 * @param Periphs This parameter can be a combination of the following values:
1083 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1084 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1085 * @retval None
1086 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1087 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1088 {
1089 SET_BIT(RCC->APB1RSTR2, Periphs);
1090 }
1091
1092 /**
1093 * @brief Release APB1 peripherals reset.
1094 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1095 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1096 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1097 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset
1098 * @param Periphs This parameter can be a combination of the following values:
1099 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1100 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1101 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1102 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1103 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1104 *
1105 * (*) value not defined in all devices.
1106 * @retval None
1107 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1108 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1109 {
1110 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1111 }
1112
1113 /**
1114 * @brief Release APB1 peripherals reset.
1115 * @rmtoll APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
1116 * @param Periphs This parameter can be a combination of the following values:
1117 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1118 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1119 * @retval None
1120 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1121 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1122 {
1123 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1124 }
1125
1126 /**
1127 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1128 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1129 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1130 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1131 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1132 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep
1133 * @param Periphs This parameter can be a combination of the following values:
1134 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1135 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1136 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1137 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1138 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1139 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1140 *
1141 * (*) value not defined in all devices.
1142 * @retval None
1143 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)1144 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
1145 {
1146 __IO uint32_t tmpreg;
1147 SET_BIT(RCC->APB1SMENR1, Periphs);
1148 /* Delay after an RCC peripheral clock enabling */
1149 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1150 (void)tmpreg;
1151 }
1152
1153 /**
1154 * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
1155 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1156 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1157 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1158 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1159 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep
1160 * @param Periphs This parameter can be a combination of the following values:
1161 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1162 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1163 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1164 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1165 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1166 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1167 *
1168 * (*) value not defined in all devices.
1169 * @retval State of Periphs (1 or 0).
1170 */
LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)1171 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
1172 {
1173 return ((READ_BIT(RCC->APB1SMENR1, Periphs) == Periphs) ? 1UL : 0UL);
1174 }
1175
1176 /**
1177 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1178 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1179 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1180 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1181 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1182 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep
1183 * @param Periphs This parameter can be a combination of the following values:
1184 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1185 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1186 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1187 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1188 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1189 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1190 *
1191 * (*) value not defined in all devices.
1192 * @retval None
1193 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)1194 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
1195 {
1196 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1197 }
1198
1199 /**
1200 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1201 * @rmtoll APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
1202 * @param Periphs This parameter can be a combination of the following values:
1203 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1204 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1205 * @retval None
1206 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)1207 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1208 {
1209 __IO uint32_t tmpreg;
1210 SET_BIT(RCC->APB1SMENR2, Periphs);
1211 /* Delay after an RCC peripheral clock enabling */
1212 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1213 (void)tmpreg;
1214 }
1215
1216 /**
1217 * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
1218 * @rmtoll APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep
1219 * @param Periphs This parameter can be a combination of the following values:
1220 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1221 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1222 * @retval State of Periphs (1 or 0).
1223 */
LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)1224 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)
1225 {
1226 return ((READ_BIT(RCC->APB1SMENR2, Periphs) == Periphs) ? 1UL : 0UL);
1227 }
1228
1229 /**
1230 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1231 * @rmtoll APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
1232 * @param Periphs This parameter can be a combination of the following values:
1233 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1234 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1235 * @retval None
1236 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)1237 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1238 {
1239 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1240 }
1241
1242 /**
1243 * @}
1244 */
1245
1246 /** @defgroup BUS_LL_EF_APB2 APB2
1247 * @{
1248 */
1249
1250 /**
1251 * @brief Enable APB2 peripherals clock.
1252 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1253 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1254 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1255 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1256 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1257 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
1258 * @param Periphs This parameter can be a combination of the following values:
1259 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1260 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1261 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1262 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1263 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1264 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1265 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1266 *
1267 * (*) value not defined in all devices.
1268 * @retval None
1269 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1270 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1271 {
1272 __IO uint32_t tmpreg;
1273 SET_BIT(RCC->APB2ENR, Periphs);
1274 /* Delay after an RCC peripheral clock enabling */
1275 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1276 (void)tmpreg;
1277 }
1278
1279 /**
1280 * @brief Check if APB2 peripheral clock is enabled or not
1281 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1282 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1283 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1284 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1285 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1286 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
1287 * @param Periphs This parameter can be a combination of the following values:
1288 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1289 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1290 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1291 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1292 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1293 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1294 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1295 *
1296 * (*) value not defined in all devices.
1297 * @retval State of Periphs (1 or 0).
1298 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1299 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1300 {
1301 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1302 }
1303
1304 /**
1305 * @brief Disable APB2 peripherals clock.
1306 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1307 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1308 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1309 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1310 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1311 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
1312 * @param Periphs This parameter can be a combination of the following values:
1313 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1314 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1315 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1316 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1317 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1318 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1319 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1320 *
1321 * (*) value not defined in all devices.
1322 * @retval None
1323 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1324 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1325 {
1326 CLEAR_BIT(RCC->APB2ENR, Periphs);
1327 }
1328
1329 /**
1330 * @brief Force APB2 peripherals reset.
1331 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1332 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1333 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1334 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1335 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1336 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
1337 * @param Periphs This parameter can be a combination of the following values:
1338 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1339 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1340 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1341 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1342 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1343 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1344 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1345 *
1346 * (*) value not defined in all devices.
1347 * @retval None
1348 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1349 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1350 {
1351 SET_BIT(RCC->APB2RSTR, Periphs);
1352 }
1353
1354 /**
1355 * @brief Release APB2 peripherals reset.
1356 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1357 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1358 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1359 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1360 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1361 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset
1362 * @param Periphs This parameter can be a combination of the following values:
1363 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1364 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1365 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1366 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1367 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1368 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1369 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1370 *
1371 * (*) value not defined in all devices.
1372 * @retval None
1373 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1374 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1375 {
1376 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1377 }
1378
1379 /**
1380 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1381 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1382 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1383 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1384 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1385 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1386 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep
1387 * @param Periphs This parameter can be a combination of the following values:
1388 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1389 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1390 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1391 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1392 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1393 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1394 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1395 *
1396 * (*) value not defined in all devices.
1397 * @retval None
1398 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1399 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1400 {
1401 __IO uint32_t tmpreg;
1402 SET_BIT(RCC->APB2SMENR, Periphs);
1403 /* Delay after an RCC peripheral clock enabling */
1404 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1405 (void)tmpreg;
1406 }
1407
1408
1409 /**
1410 * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not
1411 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1412 * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1413 * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1414 * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1415 * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1416 * APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep
1417 * @param Periphs This parameter can be a combination of the following values:
1418 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1419 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1420 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1421 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1422 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1423 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1424 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1425 *
1426 * (*) value not defined in all devices.
1427 * @retval State of Periphs (1 or 0).
1428 */
LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)1429 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
1430 {
1431 return ((READ_BIT(RCC->APB2SMENR, Periphs) == Periphs) ? 1UL : 0UL);
1432 }
1433
1434 /**
1435 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1436 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1437 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1438 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1439 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1440 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1441 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep
1442 * @param Periphs This parameter can be a combination of the following values:
1443 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1444 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1445 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1446 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1447 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1448 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1449 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1450 *
1451 * (*) value not defined in all devices.
1452 * @retval None
1453 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1454 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1455 {
1456 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1457 }
1458
1459 /**
1460 * @}
1461 */
1462
1463
1464 /** @defgroup BUS_LL_EF_APB7 APB7
1465 * @{
1466 */
1467
1468 /**
1469 * @brief Enable APB7 peripherals clock.
1470 * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_EnableClock\n
1471 * APB7ENR SPI3EN LL_APB7_GRP1_EnableClock\n
1472 * APB7ENR LPUART1EN LL_APB7_GRP1_EnableClock\n
1473 * APB7ENR I2C3EN LL_APB7_GRP1_EnableClock\n
1474 * APB7ENR LPTIM1EN LL_APB7_GRP1_EnableClock\n
1475 * APB7ENR COMPEN LL_APB7_GRP1_EnableClock\n
1476 * APB7ENR RTCAPBEN LL_APB7_GRP1_EnableClock
1477 * @param Periphs This parameter can be a combination of the following values:
1478 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1479 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1480 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1481 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1482 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1483 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1484 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1485 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1486 *
1487 * (*) value not defined in all devices.
1488 * @retval None
1489 */
LL_APB7_GRP1_EnableClock(uint32_t Periphs)1490 __STATIC_INLINE void LL_APB7_GRP1_EnableClock(uint32_t Periphs)
1491 {
1492 __IO uint32_t tmpreg;
1493 SET_BIT(RCC->APB7ENR, Periphs);
1494 /* Delay after an RCC peripheral clock enabling */
1495 tmpreg = READ_BIT(RCC->APB7ENR, Periphs);
1496 (void)tmpreg;
1497 }
1498
1499 /**
1500 * @brief Check if APB7 peripheral clock is enabled or not
1501 * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_IsEnabledClock\n
1502 * APB7ENR SPI3EN LL_APB7_GRP1_IsEnabledClock\n
1503 * APB7ENR LPUART1EN LL_APB7_GRP1_IsEnabledClock\n
1504 * APB7ENR I2C3EN LL_APB7_GRP1_IsEnabledClock\n
1505 * APB7ENR LPTIM1EN LL_APB7_GRP1_IsEnabledClock\n
1506 * APB7ENR COMPEN LL_APB7_GRP1_IsEnabledClock\n
1507 * APB7ENR RTCAPBEN LL_APB7_GRP1_IsEnabledClock
1508 * @param Periphs This parameter can be a combination of the following values:
1509 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1510 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1511 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1512 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1513 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1514 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1515 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1516 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1517 *
1518 * (*) value not defined in all devices.
1519 * @retval State of Periphs (1 or 0).
1520 */
LL_APB7_GRP1_IsEnabledClock(uint32_t Periphs)1521 __STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClock(uint32_t Periphs)
1522 {
1523 return ((READ_BIT(RCC->APB7ENR, Periphs) == Periphs) ? 1UL : 0UL);
1524 }
1525
1526 /**
1527 * @brief Disable APB2 peripherals clock.
1528 * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_DisableClock\n
1529 * APB7ENR SPI3EN LL_APB7_GRP1_DisableClock\n
1530 * APB7ENR LPUART1EN LL_APB7_GRP1_DisableClock\n
1531 * APB7ENR I2C3EN LL_APB7_GRP1_DisableClock\n
1532 * APB7ENR LPTIM1EN LL_APB7_GRP1_DisableClock\n
1533 * APB7ENR COMPEN LL_APB7_GRP1_DisableClock\n
1534 * APB7ENR RTCAPBEN LL_APB7_GRP1_DisableClock
1535 * @param Periphs This parameter can be a combination of the following values:
1536 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1537 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1538 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1539 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1540 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1541 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1542 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1543 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1544 *
1545 * (*) value not defined in all devices.
1546 * @retval None
1547 */
LL_APB7_GRP1_DisableClock(uint32_t Periphs)1548 __STATIC_INLINE void LL_APB7_GRP1_DisableClock(uint32_t Periphs)
1549 {
1550 CLEAR_BIT(RCC->APB7ENR, Periphs);
1551 }
1552
1553 /**
1554 * @brief Force APB7 peripherals reset.
1555 * @rmtoll APB7RSTR SYSCFGRST LL_APB7_GRP1_ForceReset\n
1556 * APB7RSTR SPI3RST LL_APB7_GRP1_ForceReset\n
1557 * APB7RSTR LPUART1RST LL_APB7_GRP1_ForceReset\n
1558 * APB7RSTR I2C3RST LL_APB7_GRP1_ForceReset\n
1559 * APB7RSTR LPTIM1RST LL_APB7_GRP1_ForceReset\n
1560 * APB7RSTR COMPRST LL_APB7_GRP1_ForceReset
1561 * @param Periphs This parameter can be a combination of the following values:
1562 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1563 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1564 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1565 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1566 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1567 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1568 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1569 *
1570 * (*) value not defined in all devices.
1571 * @retval None
1572 */
LL_APB7_GRP1_ForceReset(uint32_t Periphs)1573 __STATIC_INLINE void LL_APB7_GRP1_ForceReset(uint32_t Periphs)
1574 {
1575 SET_BIT(RCC->APB7RSTR, Periphs);
1576 }
1577
1578 /**
1579 * @brief Release APB7 peripherals reset.
1580 * @rmtoll APB7RSTR SYSCFGRST LL_APB7_GRP1_ReleaseReset\n
1581 * APB7RSTR SPI3RST LL_APB7_GRP1_ReleaseReset\n
1582 * APB7RSTR LPUART1RST LL_APB7_GRP1_ReleaseReset\n
1583 * APB7RSTR I2C3RST LL_APB7_GRP1_ReleaseReset\n
1584 * APB7RSTR LPTIM1RST LL_APB7_GRP1_ReleaseReset\n
1585 * APB7RSTR COMPRST LL_APB7_GRP1_ReleaseReset
1586 * @param Periphs This parameter can be a combination of the following values:
1587 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1588 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1589 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1590 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1591 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1592 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1593 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1594 *
1595 * (*) value not defined in all devices.
1596 * @retval None
1597 */
LL_APB7_GRP1_ReleaseReset(uint32_t Periphs)1598 __STATIC_INLINE void LL_APB7_GRP1_ReleaseReset(uint32_t Periphs)
1599 {
1600 CLEAR_BIT(RCC->APB7RSTR, Periphs);
1601 }
1602
1603 /**
1604 * @brief Enable APB7 peripheral clocks in Sleep and Stop modes
1605 * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_EnableClockStopSleep\n
1606 * APB7SMENR SPI3SMEN LL_APB7_GRP1_EnableClockStopSleep\n
1607 * APB7SMENR LPUART1SMEN LL_APB7_GRP1_EnableClockStopSleep\n
1608 * APB7SMENR I2C3SMEN LL_APB7_GRP1_EnableClockStopSleep\n
1609 * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_EnableClockStopSleep\n
1610 * APB7SMENR COMPSMEN LL_APB7_GRP1_EnableClockStopSleep\n
1611 * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_EnableClockStopSleep
1612 * @param Periphs This parameter can be a combination of the following values:
1613 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1614 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1615 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1616 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1617 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1618 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1619 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1620 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1621 *
1622 * (*) value not defined in all devices.
1623 * @retval None
1624 */
LL_APB7_GRP1_EnableClockStopSleep(uint32_t Periphs)1625 __STATIC_INLINE void LL_APB7_GRP1_EnableClockStopSleep(uint32_t Periphs)
1626 {
1627 __IO uint32_t tmpreg;
1628 SET_BIT(RCC->APB7SMENR, Periphs);
1629 /* Delay after an RCC peripheral clock enabling */
1630 tmpreg = READ_BIT(RCC->APB7SMENR, Periphs);
1631 (void)tmpreg;
1632 }
1633
1634
1635 /**
1636 * @brief Check if APB7 peripheral clocks in Sleep and Stop modes is enabled or not
1637 * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1638 * APB7SMENR SPI3SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1639 * APB7SMENR LPUART1SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1640 * APB7SMENR I2C3SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1641 * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1642 * APB7SMENR COMPSMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1643 * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_IsEnabledClockStopSleep
1644 * @param Periphs This parameter can be a combination of the following values:
1645 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1646 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1647 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1648 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1649 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1650 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1651 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1652 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1653 *
1654 * (*) value not defined in all devices.
1655 * @retval State of Periphs (1 or 0).
1656 */
LL_APB7_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)1657 __STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
1658 {
1659 return ((READ_BIT(RCC->APB7SMENR, Periphs) == Periphs) ? 1UL : 0UL);
1660 }
1661
1662 /**
1663 * @brief Disable APB7 peripheral clocks in Sleep and Stop modes
1664 * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_DisableClockStopSleep\n
1665 * APB7SMENR SPI3SMEN LL_APB7_GRP1_DisableClockStopSleep\n
1666 * APB7SMENR LPUART1SMEN LL_APB7_GRP1_DisableClockStopSleep\n
1667 * APB7SMENR I2C3SMEN LL_APB7_GRP1_DisableClockStopSleep\n
1668 * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_DisableClockStopSleep\n
1669 * APB7SMENR COMPSMEN LL_APB7_GRP1_DisableClockStopSleep\n
1670 * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_DisableClockStopSleep
1671 * @param Periphs This parameter can be a combination of the following values:
1672 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1673 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1674 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1675 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1676 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1677 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1678 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1679 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1680 *
1681 * (*) value not defined in all devices.
1682 * @retval None
1683 */
LL_APB7_GRP1_DisableClockStopSleep(uint32_t Periphs)1684 __STATIC_INLINE void LL_APB7_GRP1_DisableClockStopSleep(uint32_t Periphs)
1685 {
1686 CLEAR_BIT(RCC->APB7SMENR, Periphs);
1687 }
1688
1689 /**
1690 * @}
1691 */
1692
1693 /**
1694 * @}
1695 */
1696
1697 /**
1698 * @}
1699 */
1700
1701 #endif /* defined(RCC) */
1702
1703 /**
1704 * @}
1705 */
1706
1707 #ifdef __cplusplus
1708 }
1709 #endif
1710
1711 #endif /* STM32WBAxx_LL_BUS_H */
1712
1713
