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/Zephyr-latest/dts/bindings/clock/
Dst,stm32f7-pll-clock.yaml12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
Dst,stm32f2-pll-clock.yaml12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
Dst,stm32g4-pll-clock.yaml14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
Dst,stm32f4-pll-clock.yaml14 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
Dst,stm32g0-pll-clock.yaml14 f(PLL_P) = f(VCO clock) / PLLP --> to I2S
Dst,stm32u0-pll-clock.yaml14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
Dst,stm32wba-pll-clock.yaml16 f(PLL_P) = f(VCO clock) / PLLP
Dst,stm32wb-pll-clock.yaml17 f(PLL_P) = f(VCO clock) / PLLP --> PLLPCLK
Dst,stm32l4-pll-clock.yaml17 f(PLL_P) = f(VCO clock) / PLLP --> PLLSAI3CLK
Dst,stm32u5-pll-clock.yaml16 f(PLL_P) = f(VCO clock) / PLLP
/Zephyr-latest/boards/renesas/mck_ra8t1/
Dmck_ra8t1.dts66 pllp {
80 clocks = <&pllp>;
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_common.h22 #define pllp(v) z_pllp(v) macro
Dclock_stm32f2_f4_f7.c105 pllp(STM32_PLL_P_DIVISOR)); in config_pll_sysclock()
Dclock_stm32_ll_h7.c67 /* Given source clock and dividers, computed the output frequency of PLLP */
994 uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc; local
1051 pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >>
1053 sysclk = (uint32_t)(float_t)(pllvco/(float_t)pllp);
Dclock_stm32_ll_common.c603 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR)); in set_up_plls()
/Zephyr-latest/boards/renesas/ek_ra8d1/
Dek_ra8d1.dts101 pllp {
116 clocks = <&pllp>;
/Zephyr-latest/boards/st/stm32l4r9i_disco/
Dstm32l4r9i_disco.dts77 * WORKAROUND: stm32l4-pll-clock does not allow arbitrary PLLP dividers.
78 * Disable PLLP completely since it only feeds SAI, which is not active either.
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi56 pllp: pllp { label
123 clocks = <&pllp>;
Dr7fa8t1xh.dtsi54 pllp: pllp { label
120 clocks = <&pllp>;
Dr7fa8d1xh.dtsi86 pllp: pllp { label
153 clocks = <&pllp>;
/Zephyr-latest/boards/renesas/ek_ra8m1/
Dek_ra8m1.dts138 pllp {
153 clocks = <&pllp>;