1 /*
2 *
3 * Copyright (c) 2017 Linaro Limited.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8
9 #include <soc.h>
10 #include <stm32_ll_bus.h>
11 #include <stm32_ll_pwr.h>
12 #include <stm32_ll_rcc.h>
13 #include <stm32_ll_utils.h>
14 #include <zephyr/drivers/clock_control.h>
15 #include <zephyr/sys/util.h>
16 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
17 #include "clock_stm32_ll_common.h"
18
19 #if defined(STM32_PLL_ENABLED)
20
21 /**
22 * @brief Return PLL source
23 */
24 __unused
get_pll_source(void)25 static uint32_t get_pll_source(void)
26 {
27 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
28 return LL_RCC_PLLSOURCE_HSI;
29 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
30 return LL_RCC_PLLSOURCE_HSE;
31 }
32
33 __ASSERT(0, "Invalid source");
34 return 0;
35 }
36
37 /**
38 * @brief get the pll source frequency
39 */
40 __unused
get_pllsrc_frequency(void)41 uint32_t get_pllsrc_frequency(void)
42 {
43 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
44 return STM32_HSI_FREQ;
45 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
46 return STM32_HSE_FREQ;
47 }
48
49 __ASSERT(0, "Invalid source");
50 return 0;
51 }
52
53 #if defined(STM32_CK48_ENABLED)
54 /**
55 * @brief calculate the CK48 frequency depending on its clock source
56 */
57 __unused
get_ck48_frequency(void)58 uint32_t get_ck48_frequency(void)
59 {
60 uint32_t source;
61
62 if (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE) ==
63 LL_RCC_CK48M_CLKSOURCE_PLL) {
64 /* Get the PLL48CK source : HSE or HSI */
65 source = (LL_RCC_PLL_GetMainSource() == LL_RCC_PLLSOURCE_HSE)
66 ? HSE_VALUE
67 : HSI_VALUE;
68 /* Get the PLL48CK Q freq. No HAL macro for that */
69 return __LL_RCC_CALC_PLLCLK_48M_FREQ(source,
70 LL_RCC_PLL_GetDivider(),
71 LL_RCC_PLL_GetN(),
72 LL_RCC_PLL_GetQ()
73 );
74 } else if (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE) ==
75 LL_RCC_CK48M_CLKSOURCE_PLLI2S) {
76 /* Get the PLL I2S source : HSE or HSI */
77 source = (LL_RCC_PLLI2S_GetMainSource() == LL_RCC_PLLSOURCE_HSE)
78 ? HSE_VALUE
79 : HSI_VALUE;
80 /* Get the PLL I2S Q freq. No HAL macro for that */
81 return __LL_RCC_CALC_PLLI2S_48M_FREQ(source,
82 LL_RCC_PLLI2S_GetDivider(),
83 LL_RCC_PLLI2S_GetN(),
84 LL_RCC_PLLI2S_GetQ()
85 );
86 }
87
88 __ASSERT(0, "Invalid source");
89 return 0;
90 }
91 #endif
92
93 /**
94 * @brief Set up pll configuration
95 */
96 __unused
config_pll_sysclock(void)97 void config_pll_sysclock(void)
98 {
99 #if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED && defined(RCC_PLLCFGR_PLLR)
100 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR));
101 #endif
102 LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
103 pllm(STM32_PLL_M_DIVISOR),
104 STM32_PLL_N_MULTIPLIER,
105 pllp(STM32_PLL_P_DIVISOR));
106
107 #if STM32_PLL_Q_ENABLED
108 /* There is a Q divider on the PLL to configure the PLL48CK */
109 LL_RCC_PLL_ConfigDomain_48M(get_pll_source(),
110 pllm(STM32_PLL_M_DIVISOR),
111 STM32_PLL_N_MULTIPLIER,
112 pllq(STM32_PLL_Q_DIVISOR));
113 #endif /* STM32_PLLI2S_Q_ENABLED */
114
115 #if defined(CONFIG_SOC_SERIES_STM32F7X)
116 /* Assuming we stay on Power Scale default value: Power Scale 1 */
117 if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 180000000) {
118 /* Enable the PLL (PLLON) before setting overdrive. Skipping the PLL
119 * locking phase since the system will be stalled during the switch
120 * (ODSW) but the PLL clock system will be running during the locking
121 * phase. See reference manual (RM0431) §4.1.4 Voltage regulator
122 * Sub section: Entering Over-drive mode.
123 */
124 LL_RCC_PLL_Enable();
125
126 /* Set Overdrive if needed before configuring the Flash Latency */
127 LL_PWR_EnableOverDriveMode();
128 while (LL_PWR_IsActiveFlag_OD() != 1) {
129 /* Wait for OverDrive mode ready */
130 }
131 LL_PWR_EnableOverDriveSwitching();
132 while (LL_PWR_IsActiveFlag_ODSW() != 1) {
133 /* Wait for OverDrive switch ready */
134 }
135
136 /* The PLL could still not be locked when returning to the caller
137 * function. But the caller doesn't know we've turned on the PLL
138 * for the overdrive function. The caller will try to turn on the PLL
139 * And start waiting for the PLL locking phase to complete.
140 */
141 }
142 #endif /* CONFIG_SOC_SERIES_STM32F7X */
143 }
144
145 #endif /* defined(STM32_PLL_ENABLED) */
146
147 #ifdef STM32_PLLI2S_ENABLED
148
149 /**
150 * @brief Set up PLL I2S configuration
151 */
152 __unused
config_plli2s(void)153 void config_plli2s(void)
154 {
155 LL_RCC_PLLI2S_ConfigDomain_I2S(get_pll_source(),
156 plli2sm(STM32_PLLI2S_M_DIVISOR),
157 STM32_PLLI2S_N_MULTIPLIER,
158 plli2sr(STM32_PLLI2S_R_DIVISOR));
159
160 #if STM32_PLLI2S_Q_ENABLED
161 /* There is a Q divider on the PLLI2S to configure the PLL48CK */
162 LL_RCC_PLLI2S_ConfigDomain_48M(get_pll_source(),
163 plli2sm(STM32_PLLI2S_M_DIVISOR),
164 STM32_PLLI2S_N_MULTIPLIER,
165 plli2sq(STM32_PLLI2S_Q_DIVISOR));
166 #endif /* STM32_PLLI2S_Q_ENABLED */
167 }
168
169 #endif /* STM32_PLLI2S_ENABLED */
170
171 /**
172 * @brief Activate default clocks
173 */
config_enable_default_clocks(void)174 void config_enable_default_clocks(void)
175 {
176 /* Power Interface clock enabled by default */
177 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
178 }
179
