1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/dts-v1/;
7
8#include <renesas/ra/ra8/r7fa8t1ahecbd.dtsi>
9#include <dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/adc/adc.h>
11#include "mck_ra8t1-pinctrl.dtsi"
12
13/ {
14	model = "Renesas MCK-RA8T1";
15	compatible = "renesas,ra8t1", "renesas,ra8";
16
17	chosen {
18		zephyr,sram = &sram0;
19		zephyr,flash = &flash0;
20		zephyr,console = &uart3;
21		zephyr,shell-uart = &uart3;
22		zephyr,entropy = &trng;
23		zephyr,flash-controller = &flash1;
24		zephyr,canbus = &canfd1;
25	};
26
27	leds {
28		compatible = "gpio-leds";
29		led1: led1 {
30			gpios = <&ioporta 12 GPIO_ACTIVE_HIGH>;
31			label = "LED1";
32		};
33		led2: led2 {
34			gpios = <&ioporta 14 GPIO_ACTIVE_HIGH>;
35			label = "LED2";
36		};
37		led3: led3 {
38			gpios = <&ioport6 6 GPIO_ACTIVE_HIGH>;
39			label = "LED3";
40		};
41		led4: led4 {
42			gpios = <&ioporta 6 GPIO_ACTIVE_HIGH>;
43			label = "LED4";
44		};
45	};
46
47	aliases {
48		led0 = &led1;
49		sdhc0 = &sdhc0;
50	};
51};
52
53&xtal {
54	clock-frequency = <DT_FREQ_M(24)>;
55	mosel = <0>;
56	#clock-cells = <0>;
57	status = "okay";
58};
59
60&subclk {
61	status = "okay";
62};
63
64&pll {
65	status = "okay";
66	pllp {
67		status = "okay";
68	};
69
70	pllq {
71		status = "okay";
72	};
73
74	pllr {
75		status = "okay";
76	};
77};
78
79&sciclk {
80	clocks = <&pllp>;
81	div = <4>;
82	status = "okay";
83};
84
85&canfdclk {
86	clocks = <&pll>;
87	div = <5>;
88	status = "okay";
89};
90
91&ioport3 {
92	status = "okay";
93};
94
95&ioport6 {
96	status = "okay";
97};
98
99&ioporta {
100	status = "okay";
101};
102
103&sci3 {
104	pinctrl-0 = <&sci3_default>;
105	pinctrl-names = "default";
106	status = "okay";
107	uart3: uart {
108		current-speed = <115200>;
109		status = "okay";
110	};
111};
112
113&trng {
114	status = "okay";
115};
116
117&spi0 {
118	pinctrl-0 = <&spi0_default>;
119	pinctrl-names = "default";
120	status = "okay";
121};
122
123&flash1 {
124	partitions {
125		compatible = "fixed-partitions";
126		#address-cells = <1>;
127		#size-cells = <1>;
128
129		storage_partition: partition@0 {
130			label = "storage";
131			reg = <0X0 DT_SIZE_K(12)>;
132		};
133	};
134};
135
136&pwm2 {
137	pinctrl-0 = <&pwm2_default>;
138	interrupts = <40 1>, <41 1>;
139	interrupt-names = "gtioca", "overflow";
140	pinctrl-names = "default";
141	status = "okay";
142};
143
144&canfd_global {
145	status = "okay";
146	canfd1 {
147		pinctrl-0 = <&canfd1_default>;
148		pinctrl-names = "default";
149		rx-max-filters = <16>;
150		status = "okay";
151	};
152};
153
154&iic1 {
155	#address-cells = <1>;
156	#size-cells = <0>;
157	clock-frequency = <DT_FREQ_M(1)>;
158	pinctrl-0 = <&iic1_default>;
159	pinctrl-names = "default";
160};
161
162&eth {
163	local-mac-address = [74 90 50 6D 81 75];
164	status = "okay";
165	phy-handle = <&phy>;
166};
167
168&mdio {
169	pinctrl-0 = <&ether_default>;
170	pinctrl-names = "default";
171	status = "okay";
172
173	phy: ethernet-phy@5 {
174		compatible = "ethernet-phy";
175		reg = <5>;
176		status = "okay";
177	};
178};
179
180&adc0 {
181	status = "okay";
182	pinctrl-0 = <&adc0_default>;
183	pinctrl-names = "default";
184	average-count = <4>;
185};
186
187&sdhc0 {
188	compatible = "renesas,ra-sdhc";
189	pinctrl-0 = <&sdhc0_default>;
190	enable-gpios = <&ioport3 11 GPIO_ACTIVE_HIGH>;
191	pinctrl-names = "default";
192	status = "okay";
193	sdmmc {
194		compatible = "zephyr,sdmmc-disk";
195		disk-name = "SD";
196		status = "okay";
197	};
198};
199