1 /* 2 * 3 * Copyright (c) 2017 Linaro Limited. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ 9 #define ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ 10 11 #include <stdint.h> 12 13 #include <zephyr/device.h> 14 15 #include <stm32_ll_utils.h> 16 17 /* Macros to fill up multiplication and division factors values */ 18 #define z_pllm(v) LL_RCC_PLLM_DIV_ ## v 19 #define pllm(v) z_pllm(v) 20 21 #define z_pllp(v) LL_RCC_PLLP_DIV_ ## v 22 #define pllp(v) z_pllp(v) 23 24 #define z_pllq(v) LL_RCC_PLLQ_DIV_ ## v 25 #define pllq(v) z_pllq(v) 26 27 #define z_pllr(v) LL_RCC_PLLR_DIV_ ## v 28 #define pllr(v) z_pllr(v) 29 30 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 31 /* Some stm32F4 devices have a dedicated PLL I2S with M divider */ 32 #define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v 33 #else 34 /* Some stm32F4 devices (typ. stm32F401) have a dedicated PLL I2S with PLL M divider */ 35 #define z_plli2s_m(v) LL_RCC_PLLM_DIV_ ## v 36 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 37 #define plli2sm(v) z_plli2s_m(v) 38 39 #define z_plli2s_q(v) LL_RCC_PLLI2SQ_DIV_ ## v 40 #define plli2sq(v) z_plli2s_q(v) 41 42 #define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v 43 #define plli2sr(v) z_plli2s_r(v) 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 #if defined(STM32_PLL_ENABLED) 50 void config_pll_sysclock(void); 51 uint32_t get_pllout_frequency(void); 52 uint32_t get_pllsrc_frequency(void); 53 #endif 54 #if defined(STM32_PLL2_ENABLED) 55 void config_pll2(void); 56 #endif 57 #if defined(STM32_PLLI2S_ENABLED) 58 void config_plli2s(void); 59 #endif 60 void config_enable_default_clocks(void); 61 void config_regulator_voltage(uint32_t hclk_freq); 62 int enabled_clock(uint32_t src_clk); 63 64 #if defined(STM32_CK48_ENABLED) 65 uint32_t get_ck48_frequency(void); 66 #endif 67 68 /* functions exported to the soc power.c */ 69 int stm32_clock_control_init(const struct device *dev); 70 void stm32_clock_control_standby_exit(void); 71 72 #ifdef __cplusplus 73 } 74 #endif 75 76 #endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ */ 77
