1# Copyright (c) 2021, Linaro Limited
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32U5 PLL.
6
7  It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
8
9  These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
10  an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
11  clock in this acceptable range.
12
13  Each PLL can have up to 3 output clocks and for each output clock, the
14  frequency can be computed with the following formulae:
15
16    f(PLL_P) = f(VCO clock) / PLLP
17    f(PLL_Q) = f(VCO clock) / PLLQ
18    f(PLL_R) = f(VCO clock) / PLLR
19
20      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
21
22  Note: To reduce the power consumption, it is recommended to configure the VCOx
23        clock output to the lowest frequency.
24
25  The PLL output frequency must not exceed 160 MHz.
26
27compatible: "st,stm32u5-pll-clock"
28
29include: [clock-controller.yaml, base.yaml]
30
31properties:
32
33  "#clock-cells":
34    const: 0
35
36  clocks:
37    required: true
38
39  div-m:
40    type: int
41    required: true
42    description: |
43        Prescaler for PLLx
44        input clock
45        Valid range: 1 - 16
46
47  mul-n:
48    type: int
49    required: true
50    description: |
51        PLLx multiplication factor for VCO
52        Valid range: 4 - 512
53
54  div-p:
55    type: int
56    description: |
57        PLLx DIVP division factor
58        Valid range: 1 - 128
59
60  div-q:
61    type: int
62    description: |
63        PLLx DIVQ division factor
64        Valid range: 1 - 128
65
66  div-r:
67    type: int
68    required: true
69    description: |
70        PLLx DIVR division factor
71        On PLL1, only division by 1 and even division values are allowed.
72        No restrictions for PLL2 and PLL3
73        Valid range: 1 - 128
74
75  fracn:
76    type: int
77    description: |
78        PLLx FRACN value
79        Valid range: 0 - 8191
80