1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  PLL node binding for STM32G4 devices
6
7  It can take one of clk_hse or clk_hsi as input clock, with
8  an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
9  clock in this acceptable range.
10
11  PLL can have up to 3 output clocks and for each output clock, the
12  frequency can be computed with the following formulae:
13
14    f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
15    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48MCLK (for USB, RNG)
16    f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
17
18      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
19
20  The PLL output frequency must not exceed 170 MHz.
21
22compatible: "st,stm32g4-pll-clock"
23
24include:
25  - name: st,stm32l4-pll-clock.yaml
26    property-blocklist:
27      - div-m
28      - mul-n
29      - div-p
30
31properties:
32
33  div-m:
34    type: int
35    required: true
36    description: |
37        Division factor for PLL input clock
38        Valid range: 1 - 16
39
40  mul-n:
41    type: int
42    required: true
43    description: |
44        Main PLL multiplication factor for VCO
45        Valid range: 8 - 127
46
47  div-p:
48    type: int
49    description: |
50        Main PLL division factor for ADC
51        Valid range: 2 - 31
52