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Searched refs:OCState (Results 1 – 25 of 40) sorted by relevance

12

/hal_stm32-3.5.0/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_ll_tim.c350 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
774 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
801 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
853 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
880 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
932 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
959 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1011 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1038 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1080 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_tim.c382 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
810 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
837 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
889 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
916 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
968 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
995 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1047 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1074 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1116 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_ll_tim.c338 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
763 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
790 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
842 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
869 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
921 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
948 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1000 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1027 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1069 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_tim.c355 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
779 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
806 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
858 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
885 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
937 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
964 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1016 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1043 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1094 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_tim.c342 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
766 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
793 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
845 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
872 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
924 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
951 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1003 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1030 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1072 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_tim.c406 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
828 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
855 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
907 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
934 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
986 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1013 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1065 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1092 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1134 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_tim.c379 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
801 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
828 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
880 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
907 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
959 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
986 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1038 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1065 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1107 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_tim.c373 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
798 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
825 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
877 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
904 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
956 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
983 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1035 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1062 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1104 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_tim.c392 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
816 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
843 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
895 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
922 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
974 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1001 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1053 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1080 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1131 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_tim.c427 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
851 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
878 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
930 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
957 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
1009 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1036 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1088 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1115 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1166 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_tim.c418 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
856 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
883 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
935 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
962 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
1014 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1041 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1093 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1120 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1162 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_tim.c450 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
882 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
909 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
961 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
988 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
1043 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1070 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1125 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1152 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1199 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c390 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
818 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
845 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
897 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
924 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
976 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1003 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1055 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1082 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1133 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_tim.c414 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
833 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
860 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
912 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
939 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
991 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1018 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1070 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1097 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1139 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_ll_tim.c271 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
484 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
509 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
543 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
568 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
602 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
627 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
661 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
686 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-3.5.0/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_tim.c294 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
507 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
532 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
566 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
591 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
625 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
650 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
684 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
709 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-3.5.0/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_tim.c339 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
729 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
756 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
808 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
835 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
887 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
914 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
966 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
993 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-3.5.0/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_tim.c360 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
749 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
776 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
828 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
855 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
907 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
934 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
986 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1013 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_tim.c360 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
750 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
777 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
829 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
856 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
908 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
935 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
987 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1014 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_tim.c381 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
769 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
796 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
848 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
875 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
927 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
954 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1006 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1033 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-3.5.0/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_tim.h184 uint32_t OCState; /*!< Specifies the TIM Output Compare state. member
/hal_stm32-3.5.0/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_tim.h188 uint32_t OCState; /*!< Specifies the TIM Output Compare state. member
/hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_tim.h232 uint32_t OCState; /*!< Specifies the TIM Output Compare state. member
/hal_stm32-3.5.0/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_tim.h234 uint32_t OCState; /*!< Specifies the TIM Output Compare state. member
/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_tim.h237 uint32_t OCState; /*!< Specifies the TIM Output Compare state. member

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