1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wlxx_ll_tim.h"
22 #include "stm32wlxx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
153 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
154
155 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
156 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
157
158 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
159 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
160
161 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
177
178 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
179 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
180
181 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
182 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
183 /**
184 * @}
185 */
186
187
188 /* Private function prototypes -----------------------------------------------*/
189 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
190 * @{
191 */
192 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
193 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
194 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
195 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
199 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
200 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
201 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
202 /**
203 * @}
204 */
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @addtogroup TIM_LL_Exported_Functions
208 * @{
209 */
210
211 /** @addtogroup TIM_LL_EF_Init
212 * @{
213 */
214
215 /**
216 * @brief Set TIMx registers to their reset values.
217 * @param TIMx Timer instance
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: TIMx registers are de-initialized
220 * - ERROR: invalid TIMx instance
221 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)222 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
223 {
224 ErrorStatus result = SUCCESS;
225
226 /* Check the parameters */
227 assert_param(IS_TIM_INSTANCE(TIMx));
228
229 if (TIMx == TIM1)
230 {
231 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
232 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
233 }
234 else if (TIMx == TIM2)
235 {
236 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
237 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
238 }
239 else if (TIMx == TIM16)
240 {
241 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
242 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
243 }
244 else if (TIMx == TIM17)
245 {
246 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
247 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
248 }
249 else
250 {
251 result = ERROR;
252 }
253
254 return result;
255 }
256
257 /**
258 * @brief Set the fields of the time base unit configuration data structure
259 * to their default values.
260 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
261 * @retval None
262 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)263 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
264 {
265 /* Set the default configuration */
266 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
267 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
268 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
269 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
270 TIM_InitStruct->RepetitionCounter = 0x00000000U;
271 }
272
273 /**
274 * @brief Configure the TIMx time base unit.
275 * @param TIMx Timer Instance
276 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
277 * (TIMx time base unit configuration data structure)
278 * @retval An ErrorStatus enumeration value:
279 * - SUCCESS: TIMx registers are de-initialized
280 * - ERROR: not applicable
281 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)282 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
283 {
284 uint32_t tmpcr1;
285
286 /* Check the parameters */
287 assert_param(IS_TIM_INSTANCE(TIMx));
288 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
289 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
290
291 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
292
293 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
294 {
295 /* Select the Counter Mode */
296 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
297 }
298
299 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
300 {
301 /* Set the clock division */
302 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
303 }
304
305 /* Write to TIMx CR1 */
306 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
307
308 /* Set the Autoreload value */
309 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
310
311 /* Set the Prescaler value */
312 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
313
314 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
315 {
316 /* Set the Repetition Counter value */
317 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
318 }
319
320 /* Generate an update event to reload the Prescaler
321 and the repetition counter value (if applicable) immediately */
322 LL_TIM_GenerateEvent_UPDATE(TIMx);
323
324 return SUCCESS;
325 }
326
327 /**
328 * @brief Set the fields of the TIMx output channel configuration data
329 * structure to their default values.
330 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
331 * (the output channel configuration data structure)
332 * @retval None
333 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)334 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
335 {
336 /* Set the default configuration */
337 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
338 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
339 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
340 TIM_OC_InitStruct->CompareValue = 0x00000000U;
341 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
342 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
343 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
344 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
345 }
346
347 /**
348 * @brief Configure the TIMx output channel.
349 * @param TIMx Timer Instance
350 * @param Channel This parameter can be one of the following values:
351 * @arg @ref LL_TIM_CHANNEL_CH1
352 * @arg @ref LL_TIM_CHANNEL_CH2
353 * @arg @ref LL_TIM_CHANNEL_CH3
354 * @arg @ref LL_TIM_CHANNEL_CH4
355 * @arg @ref LL_TIM_CHANNEL_CH5
356 * @arg @ref LL_TIM_CHANNEL_CH6
357 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
358 * data structure)
359 * @retval An ErrorStatus enumeration value:
360 * - SUCCESS: TIMx output channel is initialized
361 * - ERROR: TIMx output channel is not initialized
362 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)363 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
364 {
365 ErrorStatus result = ERROR;
366
367 switch (Channel)
368 {
369 case LL_TIM_CHANNEL_CH1:
370 result = OC1Config(TIMx, TIM_OC_InitStruct);
371 break;
372 case LL_TIM_CHANNEL_CH2:
373 result = OC2Config(TIMx, TIM_OC_InitStruct);
374 break;
375 case LL_TIM_CHANNEL_CH3:
376 result = OC3Config(TIMx, TIM_OC_InitStruct);
377 break;
378 case LL_TIM_CHANNEL_CH4:
379 result = OC4Config(TIMx, TIM_OC_InitStruct);
380 break;
381 case LL_TIM_CHANNEL_CH5:
382 result = OC5Config(TIMx, TIM_OC_InitStruct);
383 break;
384 case LL_TIM_CHANNEL_CH6:
385 result = OC6Config(TIMx, TIM_OC_InitStruct);
386 break;
387 default:
388 break;
389 }
390
391 return result;
392 }
393
394 /**
395 * @brief Set the fields of the TIMx input channel configuration data
396 * structure to their default values.
397 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
398 * data structure)
399 * @retval None
400 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)401 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
402 {
403 /* Set the default configuration */
404 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
405 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
406 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
407 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
408 }
409
410 /**
411 * @brief Configure the TIMx input channel.
412 * @param TIMx Timer Instance
413 * @param Channel This parameter can be one of the following values:
414 * @arg @ref LL_TIM_CHANNEL_CH1
415 * @arg @ref LL_TIM_CHANNEL_CH2
416 * @arg @ref LL_TIM_CHANNEL_CH3
417 * @arg @ref LL_TIM_CHANNEL_CH4
418 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
419 * structure)
420 * @retval An ErrorStatus enumeration value:
421 * - SUCCESS: TIMx output channel is initialized
422 * - ERROR: TIMx output channel is not initialized
423 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)424 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
425 {
426 ErrorStatus result = ERROR;
427
428 switch (Channel)
429 {
430 case LL_TIM_CHANNEL_CH1:
431 result = IC1Config(TIMx, TIM_IC_InitStruct);
432 break;
433 case LL_TIM_CHANNEL_CH2:
434 result = IC2Config(TIMx, TIM_IC_InitStruct);
435 break;
436 case LL_TIM_CHANNEL_CH3:
437 result = IC3Config(TIMx, TIM_IC_InitStruct);
438 break;
439 case LL_TIM_CHANNEL_CH4:
440 result = IC4Config(TIMx, TIM_IC_InitStruct);
441 break;
442 default:
443 break;
444 }
445
446 return result;
447 }
448
449 /**
450 * @brief Fills each TIM_EncoderInitStruct field with its default value
451 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
452 * configuration data structure)
453 * @retval None
454 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)455 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
456 {
457 /* Set the default configuration */
458 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
459 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
460 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
461 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
462 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
463 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
464 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
465 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
466 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
467 }
468
469 /**
470 * @brief Configure the encoder interface of the timer instance.
471 * @param TIMx Timer Instance
472 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
473 * configuration data structure)
474 * @retval An ErrorStatus enumeration value:
475 * - SUCCESS: TIMx registers are de-initialized
476 * - ERROR: not applicable
477 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)478 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
479 {
480 uint32_t tmpccmr1;
481 uint32_t tmpccer;
482
483 /* Check the parameters */
484 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
485 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
486 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
487 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
488 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
489 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
490 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
491 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
492 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
493 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
494
495 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
496 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
497
498 /* Get the TIMx CCMR1 register value */
499 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
500
501 /* Get the TIMx CCER register value */
502 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
503
504 /* Configure TI1 */
505 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
506 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
507 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
508 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
509
510 /* Configure TI2 */
511 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
512 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
513 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
514 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
515
516 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
517 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
518 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
519 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
520 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
521
522 /* Set encoder mode */
523 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
524
525 /* Write to TIMx CCMR1 */
526 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
527
528 /* Write to TIMx CCER */
529 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
530
531 return SUCCESS;
532 }
533
534 /**
535 * @brief Set the fields of the TIMx Hall sensor interface configuration data
536 * structure to their default values.
537 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
538 * configuration data structure)
539 * @retval None
540 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)541 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
542 {
543 /* Set the default configuration */
544 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
545 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
546 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
547 TIM_HallSensorInitStruct->CommutationDelay = 0U;
548 }
549
550 /**
551 * @brief Configure the Hall sensor interface of the timer instance.
552 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
553 * to the TI1 input channel
554 * @note TIMx slave mode controller is configured in reset mode.
555 Selected internal trigger is TI1F_ED.
556 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
557 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
558 * between 2 changes on the inputs. It gives information about motor speed.
559 * @note Channel 2 is configured in output PWM 2 mode.
560 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
561 * @note OC2REF is selected as trigger output on TRGO.
562 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
563 * when TIMx operates in Hall sensor interface mode.
564 * @param TIMx Timer Instance
565 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
566 * interface configuration data structure)
567 * @retval An ErrorStatus enumeration value:
568 * - SUCCESS: TIMx registers are de-initialized
569 * - ERROR: not applicable
570 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)571 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
572 {
573 uint32_t tmpcr2;
574 uint32_t tmpccmr1;
575 uint32_t tmpccer;
576 uint32_t tmpsmcr;
577
578 /* Check the parameters */
579 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
580 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
581 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
582 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
583
584 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
585 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
586
587 /* Get the TIMx CR2 register value */
588 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
589
590 /* Get the TIMx CCMR1 register value */
591 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
592
593 /* Get the TIMx CCER register value */
594 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
595
596 /* Get the TIMx SMCR register value */
597 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
598
599 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
600 tmpcr2 |= TIM_CR2_TI1S;
601
602 /* OC2REF signal is used as trigger output (TRGO) */
603 tmpcr2 |= LL_TIM_TRGO_OC2REF;
604
605 /* Configure the slave mode controller */
606 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
607 tmpsmcr |= LL_TIM_TS_TI1F_ED;
608 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
609
610 /* Configure input channel 1 */
611 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
612 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
613 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
614 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
615
616 /* Configure input channel 2 */
617 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
618 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
619
620 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
621 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
622 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
623 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
624
625 /* Write to TIMx CR2 */
626 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
627
628 /* Write to TIMx SMCR */
629 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
630
631 /* Write to TIMx CCMR1 */
632 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
633
634 /* Write to TIMx CCER */
635 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
636
637 /* Write to TIMx CCR2 */
638 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
639
640 return SUCCESS;
641 }
642
643 /**
644 * @brief Set the fields of the Break and Dead Time configuration data structure
645 * to their default values.
646 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
647 * data structure)
648 * @retval None
649 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)650 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
651 {
652 /* Set the default configuration */
653 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
654 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
655 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
656 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
657 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
658 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
659 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
660 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
661 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
662 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
663 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
664 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
665 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
666 }
667
668 /**
669 * @brief Configure the Break and Dead Time feature of the timer instance.
670 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
671 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
672 * can be necessary to configure all of them during the first write access to
673 * the TIMx_BDTR register.
674 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
675 * a timer instance provides a break input.
676 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
677 * a timer instance provides a second break input.
678 * @param TIMx Timer Instance
679 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
680 * data structure)
681 * @retval An ErrorStatus enumeration value:
682 * - SUCCESS: Break and Dead Time is initialized
683 * - ERROR: not applicable
684 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)685 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
686 {
687 uint32_t tmpbdtr = 0;
688
689 /* Check the parameters */
690 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
691 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
692 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
693 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
694 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
695 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
696 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
697
698 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
699 the OSSI State, the dead time value and the Automatic Output Enable Bit */
700
701 /* Set the BDTR bits */
702 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
703 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
704 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
705 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
706 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
707 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
708 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
709 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
710 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
711 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
712 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
713 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
714
715 if (IS_TIM_BKIN2_INSTANCE(TIMx))
716 {
717 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
718 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
719 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
720 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
721
722 /* Set the BREAK2 input related BDTR bit-fields */
723 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
724 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
725 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
726 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
727 }
728
729 /* Set TIMx_BDTR */
730 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
731
732 return SUCCESS;
733 }
734 /**
735 * @}
736 */
737
738 /**
739 * @}
740 */
741
742 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
743 * @brief Private functions
744 * @{
745 */
746 /**
747 * @brief Configure the TIMx output channel 1.
748 * @param TIMx Timer Instance
749 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
750 * @retval An ErrorStatus enumeration value:
751 * - SUCCESS: TIMx registers are de-initialized
752 * - ERROR: not applicable
753 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)754 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
755 {
756 uint32_t tmpccmr1;
757 uint32_t tmpccer;
758 uint32_t tmpcr2;
759
760 /* Check the parameters */
761 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
762 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
763 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
764 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
765 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
766 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
767
768 /* Disable the Channel 1: Reset the CC1E Bit */
769 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
770
771 /* Get the TIMx CCER register value */
772 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
773
774 /* Get the TIMx CR2 register value */
775 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
776
777 /* Get the TIMx CCMR1 register value */
778 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
779
780 /* Reset Capture/Compare selection Bits */
781 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
782
783 /* Set the Output Compare Mode */
784 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
785
786 /* Set the Output Compare Polarity */
787 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
788
789 /* Set the Output State */
790 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
791
792 if (IS_TIM_BREAK_INSTANCE(TIMx))
793 {
794 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
795 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
796
797 /* Set the complementary output Polarity */
798 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
799
800 /* Set the complementary output State */
801 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
802
803 /* Set the Output Idle state */
804 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
805
806 /* Set the complementary output Idle state */
807 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
808 }
809
810 /* Write to TIMx CR2 */
811 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
812
813 /* Write to TIMx CCMR1 */
814 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
815
816 /* Set the Capture Compare Register value */
817 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
818
819 /* Write to TIMx CCER */
820 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
821
822 return SUCCESS;
823 }
824
825 /**
826 * @brief Configure the TIMx output channel 2.
827 * @param TIMx Timer Instance
828 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
829 * @retval An ErrorStatus enumeration value:
830 * - SUCCESS: TIMx registers are de-initialized
831 * - ERROR: not applicable
832 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)833 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
834 {
835 uint32_t tmpccmr1;
836 uint32_t tmpccer;
837 uint32_t tmpcr2;
838
839 /* Check the parameters */
840 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
841 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
842 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
843 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
844 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
845 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
846
847 /* Disable the Channel 2: Reset the CC2E Bit */
848 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
849
850 /* Get the TIMx CCER register value */
851 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
852
853 /* Get the TIMx CR2 register value */
854 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
855
856 /* Get the TIMx CCMR1 register value */
857 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
858
859 /* Reset Capture/Compare selection Bits */
860 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
861
862 /* Select the Output Compare Mode */
863 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
864
865 /* Set the Output Compare Polarity */
866 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
867
868 /* Set the Output State */
869 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
870
871 if (IS_TIM_BREAK_INSTANCE(TIMx))
872 {
873 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
874 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
875
876 /* Set the complementary output Polarity */
877 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
878
879 /* Set the complementary output State */
880 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
881
882 /* Set the Output Idle state */
883 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
884
885 /* Set the complementary output Idle state */
886 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
887 }
888
889 /* Write to TIMx CR2 */
890 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
891
892 /* Write to TIMx CCMR1 */
893 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
894
895 /* Set the Capture Compare Register value */
896 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
897
898 /* Write to TIMx CCER */
899 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
900
901 return SUCCESS;
902 }
903
904 /**
905 * @brief Configure the TIMx output channel 3.
906 * @param TIMx Timer Instance
907 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
908 * @retval An ErrorStatus enumeration value:
909 * - SUCCESS: TIMx registers are de-initialized
910 * - ERROR: not applicable
911 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)912 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
913 {
914 uint32_t tmpccmr2;
915 uint32_t tmpccer;
916 uint32_t tmpcr2;
917
918 /* Check the parameters */
919 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
920 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
921 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
922 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
923 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
924 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
925
926 /* Disable the Channel 3: Reset the CC3E Bit */
927 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
928
929 /* Get the TIMx CCER register value */
930 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
931
932 /* Get the TIMx CR2 register value */
933 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
934
935 /* Get the TIMx CCMR2 register value */
936 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
937
938 /* Reset Capture/Compare selection Bits */
939 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
940
941 /* Select the Output Compare Mode */
942 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
943
944 /* Set the Output Compare Polarity */
945 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
946
947 /* Set the Output State */
948 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
949
950 if (IS_TIM_BREAK_INSTANCE(TIMx))
951 {
952 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
953 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
954
955 /* Set the complementary output Polarity */
956 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
957
958 /* Set the complementary output State */
959 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
960
961 /* Set the Output Idle state */
962 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
963
964 /* Set the complementary output Idle state */
965 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
966 }
967
968 /* Write to TIMx CR2 */
969 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
970
971 /* Write to TIMx CCMR2 */
972 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
973
974 /* Set the Capture Compare Register value */
975 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
976
977 /* Write to TIMx CCER */
978 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
979
980 return SUCCESS;
981 }
982
983 /**
984 * @brief Configure the TIMx output channel 4.
985 * @param TIMx Timer Instance
986 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
987 * @retval An ErrorStatus enumeration value:
988 * - SUCCESS: TIMx registers are de-initialized
989 * - ERROR: not applicable
990 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)991 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
992 {
993 uint32_t tmpccmr2;
994 uint32_t tmpccer;
995 uint32_t tmpcr2;
996
997 /* Check the parameters */
998 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
999 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1000 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1001 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1002 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1003 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1004
1005 /* Disable the Channel 4: Reset the CC4E Bit */
1006 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1007
1008 /* Get the TIMx CCER register value */
1009 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1010
1011 /* Get the TIMx CR2 register value */
1012 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1013
1014 /* Get the TIMx CCMR2 register value */
1015 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1016
1017 /* Reset Capture/Compare selection Bits */
1018 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1019
1020 /* Select the Output Compare Mode */
1021 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1022
1023 /* Set the Output Compare Polarity */
1024 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1025
1026 /* Set the Output State */
1027 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1028
1029 if (IS_TIM_BREAK_INSTANCE(TIMx))
1030 {
1031 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1032 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1033
1034 /* Set the Output Idle state */
1035 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1036 }
1037
1038 /* Write to TIMx CR2 */
1039 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1040
1041 /* Write to TIMx CCMR2 */
1042 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1043
1044 /* Set the Capture Compare Register value */
1045 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1046
1047 /* Write to TIMx CCER */
1048 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1049
1050 return SUCCESS;
1051 }
1052
1053 /**
1054 * @brief Configure the TIMx output channel 5.
1055 * @param TIMx Timer Instance
1056 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1057 * @retval An ErrorStatus enumeration value:
1058 * - SUCCESS: TIMx registers are de-initialized
1059 * - ERROR: not applicable
1060 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1061 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1062 {
1063 uint32_t tmpccmr3;
1064 uint32_t tmpccer;
1065
1066 /* Check the parameters */
1067 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1068 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1069 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1070 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1071 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1072 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1073
1074 /* Disable the Channel 5: Reset the CC5E Bit */
1075 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1076
1077 /* Get the TIMx CCER register value */
1078 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1079
1080 /* Get the TIMx CCMR3 register value */
1081 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1082
1083 /* Select the Output Compare Mode */
1084 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1085
1086 /* Set the Output Compare Polarity */
1087 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1088
1089 /* Set the Output State */
1090 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1091
1092 if (IS_TIM_BREAK_INSTANCE(TIMx))
1093 {
1094 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1095 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1096
1097 /* Set the Output Idle state */
1098 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1099
1100 }
1101
1102 /* Write to TIMx CCMR3 */
1103 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1104
1105 /* Set the Capture Compare Register value */
1106 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1107
1108 /* Write to TIMx CCER */
1109 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1110
1111 return SUCCESS;
1112 }
1113
1114 /**
1115 * @brief Configure the TIMx output channel 6.
1116 * @param TIMx Timer Instance
1117 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1118 * @retval An ErrorStatus enumeration value:
1119 * - SUCCESS: TIMx registers are de-initialized
1120 * - ERROR: not applicable
1121 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1122 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1123 {
1124 uint32_t tmpccmr3;
1125 uint32_t tmpccer;
1126
1127 /* Check the parameters */
1128 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1129 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1130 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1131 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1132 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1133 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1134
1135 /* Disable the Channel 5: Reset the CC6E Bit */
1136 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1137
1138 /* Get the TIMx CCER register value */
1139 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1140
1141 /* Get the TIMx CCMR3 register value */
1142 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1143
1144 /* Select the Output Compare Mode */
1145 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1146
1147 /* Set the Output Compare Polarity */
1148 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1149
1150 /* Set the Output State */
1151 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1152
1153 if (IS_TIM_BREAK_INSTANCE(TIMx))
1154 {
1155 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1156 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1157
1158 /* Set the Output Idle state */
1159 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1160 }
1161
1162 /* Write to TIMx CCMR3 */
1163 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1164
1165 /* Set the Capture Compare Register value */
1166 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1167
1168 /* Write to TIMx CCER */
1169 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1170
1171 return SUCCESS;
1172 }
1173
1174 /**
1175 * @brief Configure the TIMx input channel 1.
1176 * @param TIMx Timer Instance
1177 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1178 * @retval An ErrorStatus enumeration value:
1179 * - SUCCESS: TIMx registers are de-initialized
1180 * - ERROR: not applicable
1181 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1182 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1183 {
1184 /* Check the parameters */
1185 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1186 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1187 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1188 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1189 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1190
1191 /* Disable the Channel 1: Reset the CC1E Bit */
1192 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1193
1194 /* Select the Input and set the filter and the prescaler value */
1195 MODIFY_REG(TIMx->CCMR1,
1196 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1197 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1198
1199 /* Select the Polarity and set the CC1E Bit */
1200 MODIFY_REG(TIMx->CCER,
1201 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1202 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1203
1204 return SUCCESS;
1205 }
1206
1207 /**
1208 * @brief Configure the TIMx input channel 2.
1209 * @param TIMx Timer Instance
1210 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1211 * @retval An ErrorStatus enumeration value:
1212 * - SUCCESS: TIMx registers are de-initialized
1213 * - ERROR: not applicable
1214 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1215 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1216 {
1217 /* Check the parameters */
1218 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1219 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1220 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1221 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1222 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1223
1224 /* Disable the Channel 2: Reset the CC2E Bit */
1225 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1226
1227 /* Select the Input and set the filter and the prescaler value */
1228 MODIFY_REG(TIMx->CCMR1,
1229 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1230 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1231
1232 /* Select the Polarity and set the CC2E Bit */
1233 MODIFY_REG(TIMx->CCER,
1234 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1235 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1236
1237 return SUCCESS;
1238 }
1239
1240 /**
1241 * @brief Configure the TIMx input channel 3.
1242 * @param TIMx Timer Instance
1243 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1244 * @retval An ErrorStatus enumeration value:
1245 * - SUCCESS: TIMx registers are de-initialized
1246 * - ERROR: not applicable
1247 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1248 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1249 {
1250 /* Check the parameters */
1251 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1252 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1253 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1254 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1255 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1256
1257 /* Disable the Channel 3: Reset the CC3E Bit */
1258 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1259
1260 /* Select the Input and set the filter and the prescaler value */
1261 MODIFY_REG(TIMx->CCMR2,
1262 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1263 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1264
1265 /* Select the Polarity and set the CC3E Bit */
1266 MODIFY_REG(TIMx->CCER,
1267 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1268 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1269
1270 return SUCCESS;
1271 }
1272
1273 /**
1274 * @brief Configure the TIMx input channel 4.
1275 * @param TIMx Timer Instance
1276 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1277 * @retval An ErrorStatus enumeration value:
1278 * - SUCCESS: TIMx registers are de-initialized
1279 * - ERROR: not applicable
1280 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1281 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1282 {
1283 /* Check the parameters */
1284 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1285 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1286 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1287 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1288 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1289
1290 /* Disable the Channel 4: Reset the CC4E Bit */
1291 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1292
1293 /* Select the Input and set the filter and the prescaler value */
1294 MODIFY_REG(TIMx->CCMR2,
1295 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1296 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1297
1298 /* Select the Polarity and set the CC2E Bit */
1299 MODIFY_REG(TIMx->CCER,
1300 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1301 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1302
1303 return SUCCESS;
1304 }
1305
1306
1307 /**
1308 * @}
1309 */
1310
1311 /**
1312 * @}
1313 */
1314
1315 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
1316
1317 /**
1318 * @}
1319 */
1320
1321 #endif /* USE_FULL_LL_DRIVER */
1322
1323
