1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f7xx_ll_tim.h"
22 #include "stm32f7xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
153 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
154
155 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
156 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
157
158 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
159 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
160 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
161 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
174
175 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
176 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
177 /**
178 * @}
179 */
180
181
182 /* Private function prototypes -----------------------------------------------*/
183 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
184 * @{
185 */
186 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
187 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
188 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
189 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
190 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
191 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
192 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
193 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
194 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
195 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
196 /**
197 * @}
198 */
199
200 /* Exported functions --------------------------------------------------------*/
201 /** @addtogroup TIM_LL_Exported_Functions
202 * @{
203 */
204
205 /** @addtogroup TIM_LL_EF_Init
206 * @{
207 */
208
209 /**
210 * @brief Set TIMx registers to their reset values.
211 * @param TIMx Timer instance
212 * @retval An ErrorStatus enumeration value:
213 * - SUCCESS: TIMx registers are de-initialized
214 * - ERROR: invalid TIMx instance
215 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)216 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
217 {
218 ErrorStatus result = SUCCESS;
219
220 /* Check the parameters */
221 assert_param(IS_TIM_INSTANCE(TIMx));
222
223 if (TIMx == TIM1)
224 {
225 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
226 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
227 }
228 else if (TIMx == TIM2)
229 {
230 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
231 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
232 }
233 #if defined(TIM3)
234 else if (TIMx == TIM3)
235 {
236 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
237 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
238 }
239 #endif /* TIM3 */
240 #if defined(TIM4)
241 else if (TIMx == TIM4)
242 {
243 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
244 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
245 }
246 #endif /* TIM4 */
247 #if defined(TIM5)
248 else if (TIMx == TIM5)
249 {
250 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
251 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
252 }
253 #endif /* TIM5 */
254 #if defined(TIM6)
255 else if (TIMx == TIM6)
256 {
257 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
258 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
259 }
260 #endif /* TIM6 */
261 #if defined (TIM7)
262 else if (TIMx == TIM7)
263 {
264 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
265 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
266 }
267 #endif /* TIM7 */
268 #if defined(TIM8)
269 else if (TIMx == TIM8)
270 {
271 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
272 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
273 }
274 #endif /* TIM8 */
275 #if defined(TIM9)
276 else if (TIMx == TIM9)
277 {
278 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
279 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
280 }
281 #endif /* TIM9 */
282 #if defined(TIM10)
283 else if (TIMx == TIM10)
284 {
285 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
286 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
287 }
288 #endif /* TIM10 */
289 #if defined(TIM11)
290 else if (TIMx == TIM11)
291 {
292 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
293 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
294 }
295 #endif /* TIM11 */
296 #if defined(TIM12)
297 else if (TIMx == TIM12)
298 {
299 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
300 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
301 }
302 #endif /* TIM12 */
303 #if defined(TIM13)
304 else if (TIMx == TIM13)
305 {
306 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
307 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
308 }
309 #endif /* TIM13 */
310 #if defined(TIM14)
311 else if (TIMx == TIM14)
312 {
313 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
314 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
315 }
316 #endif /* TIM14 */
317 else
318 {
319 result = ERROR;
320 }
321
322 return result;
323 }
324
325 /**
326 * @brief Set the fields of the time base unit configuration data structure
327 * to their default values.
328 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
329 * @retval None
330 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)331 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
332 {
333 /* Set the default configuration */
334 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
335 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
336 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
337 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
338 TIM_InitStruct->RepetitionCounter = 0x00000000U;
339 }
340
341 /**
342 * @brief Configure the TIMx time base unit.
343 * @param TIMx Timer Instance
344 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
345 * (TIMx time base unit configuration data structure)
346 * @retval An ErrorStatus enumeration value:
347 * - SUCCESS: TIMx registers are de-initialized
348 * - ERROR: not applicable
349 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)350 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
351 {
352 uint32_t tmpcr1;
353
354 /* Check the parameters */
355 assert_param(IS_TIM_INSTANCE(TIMx));
356 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
357 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
358
359 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
360
361 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
362 {
363 /* Select the Counter Mode */
364 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
365 }
366
367 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
368 {
369 /* Set the clock division */
370 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
371 }
372
373 /* Write to TIMx CR1 */
374 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
375
376 /* Set the Autoreload value */
377 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
378
379 /* Set the Prescaler value */
380 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
381
382 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
383 {
384 /* Set the Repetition Counter value */
385 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
386 }
387
388 /* Generate an update event to reload the Prescaler
389 and the repetition counter value (if applicable) immediately */
390 LL_TIM_GenerateEvent_UPDATE(TIMx);
391
392 return SUCCESS;
393 }
394
395 /**
396 * @brief Set the fields of the TIMx output channel configuration data
397 * structure to their default values.
398 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
399 * (the output channel configuration data structure)
400 * @retval None
401 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)402 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
403 {
404 /* Set the default configuration */
405 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
406 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
407 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
408 TIM_OC_InitStruct->CompareValue = 0x00000000U;
409 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
410 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
411 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
412 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
413 }
414
415 /**
416 * @brief Configure the TIMx output channel.
417 * @param TIMx Timer Instance
418 * @param Channel This parameter can be one of the following values:
419 * @arg @ref LL_TIM_CHANNEL_CH1
420 * @arg @ref LL_TIM_CHANNEL_CH2
421 * @arg @ref LL_TIM_CHANNEL_CH3
422 * @arg @ref LL_TIM_CHANNEL_CH4
423 * @arg @ref LL_TIM_CHANNEL_CH5
424 * @arg @ref LL_TIM_CHANNEL_CH6
425 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
426 * data structure)
427 * @retval An ErrorStatus enumeration value:
428 * - SUCCESS: TIMx output channel is initialized
429 * - ERROR: TIMx output channel is not initialized
430 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)431 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
432 {
433 ErrorStatus result = ERROR;
434
435 switch (Channel)
436 {
437 case LL_TIM_CHANNEL_CH1:
438 result = OC1Config(TIMx, TIM_OC_InitStruct);
439 break;
440 case LL_TIM_CHANNEL_CH2:
441 result = OC2Config(TIMx, TIM_OC_InitStruct);
442 break;
443 case LL_TIM_CHANNEL_CH3:
444 result = OC3Config(TIMx, TIM_OC_InitStruct);
445 break;
446 case LL_TIM_CHANNEL_CH4:
447 result = OC4Config(TIMx, TIM_OC_InitStruct);
448 break;
449 case LL_TIM_CHANNEL_CH5:
450 result = OC5Config(TIMx, TIM_OC_InitStruct);
451 break;
452 case LL_TIM_CHANNEL_CH6:
453 result = OC6Config(TIMx, TIM_OC_InitStruct);
454 break;
455 default:
456 break;
457 }
458
459 return result;
460 }
461
462 /**
463 * @brief Set the fields of the TIMx input channel configuration data
464 * structure to their default values.
465 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
466 * data structure)
467 * @retval None
468 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)469 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
470 {
471 /* Set the default configuration */
472 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
473 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
474 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
475 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
476 }
477
478 /**
479 * @brief Configure the TIMx input channel.
480 * @param TIMx Timer Instance
481 * @param Channel This parameter can be one of the following values:
482 * @arg @ref LL_TIM_CHANNEL_CH1
483 * @arg @ref LL_TIM_CHANNEL_CH2
484 * @arg @ref LL_TIM_CHANNEL_CH3
485 * @arg @ref LL_TIM_CHANNEL_CH4
486 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
487 * structure)
488 * @retval An ErrorStatus enumeration value:
489 * - SUCCESS: TIMx output channel is initialized
490 * - ERROR: TIMx output channel is not initialized
491 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)492 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
493 {
494 ErrorStatus result = ERROR;
495
496 switch (Channel)
497 {
498 case LL_TIM_CHANNEL_CH1:
499 result = IC1Config(TIMx, TIM_IC_InitStruct);
500 break;
501 case LL_TIM_CHANNEL_CH2:
502 result = IC2Config(TIMx, TIM_IC_InitStruct);
503 break;
504 case LL_TIM_CHANNEL_CH3:
505 result = IC3Config(TIMx, TIM_IC_InitStruct);
506 break;
507 case LL_TIM_CHANNEL_CH4:
508 result = IC4Config(TIMx, TIM_IC_InitStruct);
509 break;
510 default:
511 break;
512 }
513
514 return result;
515 }
516
517 /**
518 * @brief Fills each TIM_EncoderInitStruct field with its default value
519 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
520 * configuration data structure)
521 * @retval None
522 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)523 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
524 {
525 /* Set the default configuration */
526 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
527 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
528 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
529 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
530 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
531 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
532 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
533 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
534 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
535 }
536
537 /**
538 * @brief Configure the encoder interface of the timer instance.
539 * @param TIMx Timer Instance
540 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
541 * configuration data structure)
542 * @retval An ErrorStatus enumeration value:
543 * - SUCCESS: TIMx registers are de-initialized
544 * - ERROR: not applicable
545 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)546 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
547 {
548 uint32_t tmpccmr1;
549 uint32_t tmpccer;
550
551 /* Check the parameters */
552 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
553 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
554 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
555 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
556 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
557 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
558 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
559 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
560 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
561 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
562
563 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
564 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
565
566 /* Get the TIMx CCMR1 register value */
567 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
568
569 /* Get the TIMx CCER register value */
570 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
571
572 /* Configure TI1 */
573 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
574 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
575 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
576 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
577
578 /* Configure TI2 */
579 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
580 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
581 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
582 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
583
584 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
585 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
586 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
587 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
588 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
589
590 /* Set encoder mode */
591 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
592
593 /* Write to TIMx CCMR1 */
594 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
595
596 /* Write to TIMx CCER */
597 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
598
599 return SUCCESS;
600 }
601
602 /**
603 * @brief Set the fields of the TIMx Hall sensor interface configuration data
604 * structure to their default values.
605 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
606 * configuration data structure)
607 * @retval None
608 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)609 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
610 {
611 /* Set the default configuration */
612 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
613 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
614 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
615 TIM_HallSensorInitStruct->CommutationDelay = 0U;
616 }
617
618 /**
619 * @brief Configure the Hall sensor interface of the timer instance.
620 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
621 * to the TI1 input channel
622 * @note TIMx slave mode controller is configured in reset mode.
623 Selected internal trigger is TI1F_ED.
624 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
625 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
626 * between 2 changes on the inputs. It gives information about motor speed.
627 * @note Channel 2 is configured in output PWM 2 mode.
628 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
629 * @note OC2REF is selected as trigger output on TRGO.
630 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
631 * when TIMx operates in Hall sensor interface mode.
632 * @param TIMx Timer Instance
633 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
634 * interface configuration data structure)
635 * @retval An ErrorStatus enumeration value:
636 * - SUCCESS: TIMx registers are de-initialized
637 * - ERROR: not applicable
638 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)639 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
640 {
641 uint32_t tmpcr2;
642 uint32_t tmpccmr1;
643 uint32_t tmpccer;
644 uint32_t tmpsmcr;
645
646 /* Check the parameters */
647 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
648 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
649 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
650 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
651
652 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
653 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
654
655 /* Get the TIMx CR2 register value */
656 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
657
658 /* Get the TIMx CCMR1 register value */
659 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
660
661 /* Get the TIMx CCER register value */
662 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
663
664 /* Get the TIMx SMCR register value */
665 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
666
667 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
668 tmpcr2 |= TIM_CR2_TI1S;
669
670 /* OC2REF signal is used as trigger output (TRGO) */
671 tmpcr2 |= LL_TIM_TRGO_OC2REF;
672
673 /* Configure the slave mode controller */
674 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
675 tmpsmcr |= LL_TIM_TS_TI1F_ED;
676 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
677
678 /* Configure input channel 1 */
679 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
680 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
681 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
682 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
683
684 /* Configure input channel 2 */
685 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
686 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
687
688 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
689 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
690 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
691 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
692
693 /* Write to TIMx CR2 */
694 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
695
696 /* Write to TIMx SMCR */
697 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
698
699 /* Write to TIMx CCMR1 */
700 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
701
702 /* Write to TIMx CCER */
703 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
704
705 /* Write to TIMx CCR2 */
706 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
707
708 return SUCCESS;
709 }
710
711 /**
712 * @brief Set the fields of the Break and Dead Time configuration data structure
713 * to their default values.
714 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
715 * data structure)
716 * @retval None
717 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)718 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
719 {
720 /* Set the default configuration */
721 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
722 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
723 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
724 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
725 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
726 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
727 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
728 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
729 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
730 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
731 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
732 }
733
734 /**
735 * @brief Configure the Break and Dead Time feature of the timer instance.
736 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
737 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
738 * can be necessary to configure all of them during the first write access to
739 * the TIMx_BDTR register.
740 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
741 * a timer instance provides a break input.
742 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
743 * a timer instance provides a second break input.
744 * @param TIMx Timer Instance
745 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
746 * data structure)
747 * @retval An ErrorStatus enumeration value:
748 * - SUCCESS: Break and Dead Time is initialized
749 * - ERROR: not applicable
750 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)751 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
752 {
753 uint32_t tmpbdtr = 0;
754
755 /* Check the parameters */
756 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
757 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
758 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
759 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
760 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
761 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
762 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
763
764 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
765 the OSSI State, the dead time value and the Automatic Output Enable Bit */
766
767 /* Set the BDTR bits */
768 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
769 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
770 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
771 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
772 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
773 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
774 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
775 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
776 if (IS_TIM_ADVANCED_INSTANCE(TIMx))
777 {
778 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
779 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
780 }
781
782 if (IS_TIM_BKIN2_INSTANCE(TIMx))
783 {
784 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
785 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
786 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
787
788 /* Set the BREAK2 input related BDTR bit-fields */
789 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
790 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
791 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
792 }
793
794 /* Set TIMx_BDTR */
795 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
796
797 return SUCCESS;
798 }
799 /**
800 * @}
801 */
802
803 /**
804 * @}
805 */
806
807 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
808 * @brief Private functions
809 * @{
810 */
811 /**
812 * @brief Configure the TIMx output channel 1.
813 * @param TIMx Timer Instance
814 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
815 * @retval An ErrorStatus enumeration value:
816 * - SUCCESS: TIMx registers are de-initialized
817 * - ERROR: not applicable
818 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)819 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
820 {
821 uint32_t tmpccmr1;
822 uint32_t tmpccer;
823 uint32_t tmpcr2;
824
825 /* Check the parameters */
826 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
827 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
828 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
829 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
830 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
831 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
832
833 /* Disable the Channel 1: Reset the CC1E Bit */
834 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
835
836 /* Get the TIMx CCER register value */
837 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
838
839 /* Get the TIMx CR2 register value */
840 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
841
842 /* Get the TIMx CCMR1 register value */
843 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
844
845 /* Reset Capture/Compare selection Bits */
846 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
847
848 /* Set the Output Compare Mode */
849 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
850
851 /* Set the Output Compare Polarity */
852 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
853
854 /* Set the Output State */
855 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
856
857 if (IS_TIM_BREAK_INSTANCE(TIMx))
858 {
859 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
860 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
861
862 /* Set the complementary output Polarity */
863 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
864
865 /* Set the complementary output State */
866 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
867
868 /* Set the Output Idle state */
869 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
870
871 /* Set the complementary output Idle state */
872 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
873 }
874
875 /* Write to TIMx CR2 */
876 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
877
878 /* Write to TIMx CCMR1 */
879 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
880
881 /* Set the Capture Compare Register value */
882 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
883
884 /* Write to TIMx CCER */
885 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
886
887 return SUCCESS;
888 }
889
890 /**
891 * @brief Configure the TIMx output channel 2.
892 * @param TIMx Timer Instance
893 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
894 * @retval An ErrorStatus enumeration value:
895 * - SUCCESS: TIMx registers are de-initialized
896 * - ERROR: not applicable
897 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)898 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
899 {
900 uint32_t tmpccmr1;
901 uint32_t tmpccer;
902 uint32_t tmpcr2;
903
904 /* Check the parameters */
905 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
906 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
907 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
908 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
909 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
910 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
911
912 /* Disable the Channel 2: Reset the CC2E Bit */
913 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
914
915 /* Get the TIMx CCER register value */
916 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
917
918 /* Get the TIMx CR2 register value */
919 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
920
921 /* Get the TIMx CCMR1 register value */
922 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
923
924 /* Reset Capture/Compare selection Bits */
925 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
926
927 /* Select the Output Compare Mode */
928 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
929
930 /* Set the Output Compare Polarity */
931 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
932
933 /* Set the Output State */
934 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
935
936 if (IS_TIM_BREAK_INSTANCE(TIMx))
937 {
938 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
939 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
940
941 /* Set the complementary output Polarity */
942 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
943
944 /* Set the complementary output State */
945 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
946
947 /* Set the Output Idle state */
948 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
949
950 /* Set the complementary output Idle state */
951 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
952 }
953
954 /* Write to TIMx CR2 */
955 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
956
957 /* Write to TIMx CCMR1 */
958 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
959
960 /* Set the Capture Compare Register value */
961 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
962
963 /* Write to TIMx CCER */
964 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
965
966 return SUCCESS;
967 }
968
969 /**
970 * @brief Configure the TIMx output channel 3.
971 * @param TIMx Timer Instance
972 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
973 * @retval An ErrorStatus enumeration value:
974 * - SUCCESS: TIMx registers are de-initialized
975 * - ERROR: not applicable
976 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)977 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
978 {
979 uint32_t tmpccmr2;
980 uint32_t tmpccer;
981 uint32_t tmpcr2;
982
983 /* Check the parameters */
984 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
985 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
986 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
987 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
988 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
989 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
990
991 /* Disable the Channel 3: Reset the CC3E Bit */
992 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
993
994 /* Get the TIMx CCER register value */
995 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
996
997 /* Get the TIMx CR2 register value */
998 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
999
1000 /* Get the TIMx CCMR2 register value */
1001 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1002
1003 /* Reset Capture/Compare selection Bits */
1004 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1005
1006 /* Select the Output Compare Mode */
1007 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1008
1009 /* Set the Output Compare Polarity */
1010 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1011
1012 /* Set the Output State */
1013 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1014
1015 if (IS_TIM_BREAK_INSTANCE(TIMx))
1016 {
1017 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1018 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1019
1020 /* Set the complementary output Polarity */
1021 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1022
1023 /* Set the complementary output State */
1024 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1025
1026 /* Set the Output Idle state */
1027 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1028
1029 /* Set the complementary output Idle state */
1030 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1031 }
1032
1033 /* Write to TIMx CR2 */
1034 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1035
1036 /* Write to TIMx CCMR2 */
1037 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1038
1039 /* Set the Capture Compare Register value */
1040 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1041
1042 /* Write to TIMx CCER */
1043 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1044
1045 return SUCCESS;
1046 }
1047
1048 /**
1049 * @brief Configure the TIMx output channel 4.
1050 * @param TIMx Timer Instance
1051 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1052 * @retval An ErrorStatus enumeration value:
1053 * - SUCCESS: TIMx registers are de-initialized
1054 * - ERROR: not applicable
1055 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1056 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1057 {
1058 uint32_t tmpccmr2;
1059 uint32_t tmpccer;
1060 uint32_t tmpcr2;
1061
1062 /* Check the parameters */
1063 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1064 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1065 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1066 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1067 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1068 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1069
1070 /* Disable the Channel 4: Reset the CC4E Bit */
1071 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1072
1073 /* Get the TIMx CCER register value */
1074 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1075
1076 /* Get the TIMx CR2 register value */
1077 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1078
1079 /* Get the TIMx CCMR2 register value */
1080 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1081
1082 /* Reset Capture/Compare selection Bits */
1083 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1084
1085 /* Select the Output Compare Mode */
1086 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1087
1088 /* Set the Output Compare Polarity */
1089 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1090
1091 /* Set the Output State */
1092 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1093
1094 if (IS_TIM_BREAK_INSTANCE(TIMx))
1095 {
1096 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1097 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1098
1099 /* Set the Output Idle state */
1100 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1101 }
1102
1103 /* Write to TIMx CR2 */
1104 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1105
1106 /* Write to TIMx CCMR2 */
1107 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1108
1109 /* Set the Capture Compare Register value */
1110 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1111
1112 /* Write to TIMx CCER */
1113 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1114
1115 return SUCCESS;
1116 }
1117
1118 /**
1119 * @brief Configure the TIMx output channel 5.
1120 * @param TIMx Timer Instance
1121 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1122 * @retval An ErrorStatus enumeration value:
1123 * - SUCCESS: TIMx registers are de-initialized
1124 * - ERROR: not applicable
1125 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1126 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1127 {
1128 uint32_t tmpccmr3;
1129 uint32_t tmpccer;
1130
1131 /* Check the parameters */
1132 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1133 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1134 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1135 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1136 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1137 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1138
1139 /* Disable the Channel 5: Reset the CC5E Bit */
1140 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1141
1142 /* Get the TIMx CCER register value */
1143 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1144
1145 /* Get the TIMx CCMR3 register value */
1146 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1147
1148 /* Select the Output Compare Mode */
1149 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1150
1151 /* Set the Output Compare Polarity */
1152 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1153
1154 /* Set the Output State */
1155 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1156
1157 if (IS_TIM_BREAK_INSTANCE(TIMx))
1158 {
1159 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1160 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1161
1162 /* Set the Output Idle state */
1163 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1164
1165 }
1166
1167 /* Write to TIMx CCMR3 */
1168 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1169
1170 /* Set the Capture Compare Register value */
1171 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1172
1173 /* Write to TIMx CCER */
1174 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1175
1176 return SUCCESS;
1177 }
1178
1179 /**
1180 * @brief Configure the TIMx output channel 6.
1181 * @param TIMx Timer Instance
1182 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1183 * @retval An ErrorStatus enumeration value:
1184 * - SUCCESS: TIMx registers are de-initialized
1185 * - ERROR: not applicable
1186 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1187 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1188 {
1189 uint32_t tmpccmr3;
1190 uint32_t tmpccer;
1191
1192 /* Check the parameters */
1193 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1194 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1195 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1196 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1197 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1198 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1199
1200 /* Disable the Channel 5: Reset the CC6E Bit */
1201 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1202
1203 /* Get the TIMx CCER register value */
1204 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1205
1206 /* Get the TIMx CCMR3 register value */
1207 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1208
1209 /* Select the Output Compare Mode */
1210 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1211
1212 /* Set the Output Compare Polarity */
1213 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1214
1215 /* Set the Output State */
1216 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1217
1218 if (IS_TIM_BREAK_INSTANCE(TIMx))
1219 {
1220 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1221 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1222
1223 /* Set the Output Idle state */
1224 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1225 }
1226
1227 /* Write to TIMx CCMR3 */
1228 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1229
1230 /* Set the Capture Compare Register value */
1231 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1232
1233 /* Write to TIMx CCER */
1234 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1235
1236 return SUCCESS;
1237 }
1238
1239 /**
1240 * @brief Configure the TIMx input channel 1.
1241 * @param TIMx Timer Instance
1242 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1243 * @retval An ErrorStatus enumeration value:
1244 * - SUCCESS: TIMx registers are de-initialized
1245 * - ERROR: not applicable
1246 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1247 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1248 {
1249 /* Check the parameters */
1250 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1251 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1252 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1253 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1254 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1255
1256 /* Disable the Channel 1: Reset the CC1E Bit */
1257 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1258
1259 /* Select the Input and set the filter and the prescaler value */
1260 MODIFY_REG(TIMx->CCMR1,
1261 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1262 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1263
1264 /* Select the Polarity and set the CC1E Bit */
1265 MODIFY_REG(TIMx->CCER,
1266 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1267 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1268
1269 return SUCCESS;
1270 }
1271
1272 /**
1273 * @brief Configure the TIMx input channel 2.
1274 * @param TIMx Timer Instance
1275 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1276 * @retval An ErrorStatus enumeration value:
1277 * - SUCCESS: TIMx registers are de-initialized
1278 * - ERROR: not applicable
1279 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1280 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1281 {
1282 /* Check the parameters */
1283 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1284 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1285 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1286 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1287 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1288
1289 /* Disable the Channel 2: Reset the CC2E Bit */
1290 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1291
1292 /* Select the Input and set the filter and the prescaler value */
1293 MODIFY_REG(TIMx->CCMR1,
1294 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1295 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1296
1297 /* Select the Polarity and set the CC2E Bit */
1298 MODIFY_REG(TIMx->CCER,
1299 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1300 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1301
1302 return SUCCESS;
1303 }
1304
1305 /**
1306 * @brief Configure the TIMx input channel 3.
1307 * @param TIMx Timer Instance
1308 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1309 * @retval An ErrorStatus enumeration value:
1310 * - SUCCESS: TIMx registers are de-initialized
1311 * - ERROR: not applicable
1312 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1313 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1314 {
1315 /* Check the parameters */
1316 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1317 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1318 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1319 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1320 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1321
1322 /* Disable the Channel 3: Reset the CC3E Bit */
1323 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1324
1325 /* Select the Input and set the filter and the prescaler value */
1326 MODIFY_REG(TIMx->CCMR2,
1327 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1328 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1329
1330 /* Select the Polarity and set the CC3E Bit */
1331 MODIFY_REG(TIMx->CCER,
1332 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1333 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1334
1335 return SUCCESS;
1336 }
1337
1338 /**
1339 * @brief Configure the TIMx input channel 4.
1340 * @param TIMx Timer Instance
1341 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1342 * @retval An ErrorStatus enumeration value:
1343 * - SUCCESS: TIMx registers are de-initialized
1344 * - ERROR: not applicable
1345 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1346 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1347 {
1348 /* Check the parameters */
1349 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1350 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1351 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1352 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1353 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1354
1355 /* Disable the Channel 4: Reset the CC4E Bit */
1356 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1357
1358 /* Select the Input and set the filter and the prescaler value */
1359 MODIFY_REG(TIMx->CCMR2,
1360 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1361 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1362
1363 /* Select the Polarity and set the CC2E Bit */
1364 MODIFY_REG(TIMx->CCER,
1365 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1366 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1367
1368 return SUCCESS;
1369 }
1370
1371
1372 /**
1373 * @}
1374 */
1375
1376 /**
1377 * @}
1378 */
1379
1380 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
1381
1382 /**
1383 * @}
1384 */
1385
1386 #endif /* USE_FULL_LL_DRIVER */
1387
1388
