1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f1xx_ll_tim.h"
23 #include "stm32f1xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32F1xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
36
37 /** @addtogroup TIM_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @addtogroup TIM_LL_Private_Macros
46 * @{
47 */
48 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
52 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
53
54 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
56 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
57
58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
66
67 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
68 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
69
70 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
71 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
72
73 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
74 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
75
76 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
77 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
78 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
79
80 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
81 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
82 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
83 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
84
85 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
86 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
87 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
88 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
89 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
90 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
101
102 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
103 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
104
105 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
106 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
107 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
108
109 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
111
112 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
113 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
114
115 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
116 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
117
118 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
119 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
120 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
121 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
122
123 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
124 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
125
126 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
127 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
128
129 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
130 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
131 /**
132 * @}
133 */
134
135
136 /* Private function prototypes -----------------------------------------------*/
137 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
138 * @{
139 */
140 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
141 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
144 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
145 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
148 /**
149 * @}
150 */
151
152 /* Exported functions --------------------------------------------------------*/
153 /** @addtogroup TIM_LL_Exported_Functions
154 * @{
155 */
156
157 /** @addtogroup TIM_LL_EF_Init
158 * @{
159 */
160
161 /**
162 * @brief Set TIMx registers to their reset values.
163 * @param TIMx Timer instance
164 * @retval An ErrorStatus enumeration value:
165 * - SUCCESS: TIMx registers are de-initialized
166 * - ERROR: invalid TIMx instance
167 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)168 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
169 {
170 ErrorStatus result = SUCCESS;
171
172 /* Check the parameters */
173 assert_param(IS_TIM_INSTANCE(TIMx));
174
175 if (TIMx == TIM2)
176 {
177 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
178 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
179 }
180 #if defined(TIM1)
181 else if (TIMx == TIM1)
182 {
183 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
184 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
185 }
186 #endif
187 #if defined(TIM3)
188 else if (TIMx == TIM3)
189 {
190 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
191 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
192 }
193 #endif
194 #if defined(TIM4)
195 else if (TIMx == TIM4)
196 {
197 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
198 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
199 }
200 #endif
201 #if defined(TIM5)
202 else if (TIMx == TIM5)
203 {
204 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
205 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
206 }
207 #endif
208 #if defined(TIM6)
209 else if (TIMx == TIM6)
210 {
211 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
212 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
213 }
214 #endif
215 #if defined (TIM7)
216 else if (TIMx == TIM7)
217 {
218 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
219 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
220 }
221 #endif
222 #if defined(TIM8)
223 else if (TIMx == TIM8)
224 {
225 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
226 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
227 }
228 #endif
229 #if defined(TIM9)
230 else if (TIMx == TIM9)
231 {
232 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
233 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
234 }
235 #endif
236 #if defined(TIM10)
237 else if (TIMx == TIM10)
238 {
239 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
240 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
241 }
242 #endif
243 #if defined(TIM11)
244 else if (TIMx == TIM11)
245 {
246 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
247 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
248 }
249 #endif
250 #if defined(TIM12)
251 else if (TIMx == TIM12)
252 {
253 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
254 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
255 }
256 #endif
257 #if defined(TIM13)
258 else if (TIMx == TIM13)
259 {
260 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
261 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
262 }
263 #endif
264 #if defined(TIM14)
265 else if (TIMx == TIM14)
266 {
267 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
268 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
269 }
270 #endif
271 #if defined(TIM15)
272 else if (TIMx == TIM15)
273 {
274 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
275 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
276 }
277 #endif
278 #if defined(TIM16)
279 else if (TIMx == TIM16)
280 {
281 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
282 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
283 }
284 #endif
285 #if defined(TIM17)
286 else if (TIMx == TIM17)
287 {
288 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
289 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
290 }
291 #endif
292 else
293 {
294 result = ERROR;
295 }
296
297 return result;
298 }
299
300 /**
301 * @brief Set the fields of the time base unit configuration data structure
302 * to their default values.
303 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
304 * @retval None
305 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)306 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
307 {
308 /* Set the default configuration */
309 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
310 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
311 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
312 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
313 TIM_InitStruct->RepetitionCounter = 0x00000000U;
314 }
315
316 /**
317 * @brief Configure the TIMx time base unit.
318 * @param TIMx Timer Instance
319 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
320 * (TIMx time base unit configuration data structure)
321 * @retval An ErrorStatus enumeration value:
322 * - SUCCESS: TIMx registers are de-initialized
323 * - ERROR: not applicable
324 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)325 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
326 {
327 uint32_t tmpcr1;
328
329 /* Check the parameters */
330 assert_param(IS_TIM_INSTANCE(TIMx));
331 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
332 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
333
334 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
335
336 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
337 {
338 /* Select the Counter Mode */
339 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
340 }
341
342 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
343 {
344 /* Set the clock division */
345 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
346 }
347
348 /* Write to TIMx CR1 */
349 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
350
351 /* Set the Autoreload value */
352 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
353
354 /* Set the Prescaler value */
355 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
356
357 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
358 {
359 /* Set the Repetition Counter value */
360 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
361 }
362
363 /* Generate an update event to reload the Prescaler
364 and the repetition counter value (if applicable) immediately */
365 LL_TIM_GenerateEvent_UPDATE(TIMx);
366
367 return SUCCESS;
368 }
369
370 /**
371 * @brief Set the fields of the TIMx output channel configuration data
372 * structure to their default values.
373 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
374 * (the output channel configuration data structure)
375 * @retval None
376 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)377 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
378 {
379 /* Set the default configuration */
380 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
381 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
382 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
383 TIM_OC_InitStruct->CompareValue = 0x00000000U;
384 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
385 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
386 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
387 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
388 }
389
390 /**
391 * @brief Configure the TIMx output channel.
392 * @param TIMx Timer Instance
393 * @param Channel This parameter can be one of the following values:
394 * @arg @ref LL_TIM_CHANNEL_CH1
395 * @arg @ref LL_TIM_CHANNEL_CH2
396 * @arg @ref LL_TIM_CHANNEL_CH3
397 * @arg @ref LL_TIM_CHANNEL_CH4
398 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
399 * data structure)
400 * @retval An ErrorStatus enumeration value:
401 * - SUCCESS: TIMx output channel is initialized
402 * - ERROR: TIMx output channel is not initialized
403 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)404 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
405 {
406 ErrorStatus result = ERROR;
407
408 switch (Channel)
409 {
410 case LL_TIM_CHANNEL_CH1:
411 result = OC1Config(TIMx, TIM_OC_InitStruct);
412 break;
413 case LL_TIM_CHANNEL_CH2:
414 result = OC2Config(TIMx, TIM_OC_InitStruct);
415 break;
416 case LL_TIM_CHANNEL_CH3:
417 result = OC3Config(TIMx, TIM_OC_InitStruct);
418 break;
419 case LL_TIM_CHANNEL_CH4:
420 result = OC4Config(TIMx, TIM_OC_InitStruct);
421 break;
422 default:
423 break;
424 }
425
426 return result;
427 }
428
429 /**
430 * @brief Set the fields of the TIMx input channel configuration data
431 * structure to their default values.
432 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
433 * data structure)
434 * @retval None
435 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)436 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
437 {
438 /* Set the default configuration */
439 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
440 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
441 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
442 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
443 }
444
445 /**
446 * @brief Configure the TIMx input channel.
447 * @param TIMx Timer Instance
448 * @param Channel This parameter can be one of the following values:
449 * @arg @ref LL_TIM_CHANNEL_CH1
450 * @arg @ref LL_TIM_CHANNEL_CH2
451 * @arg @ref LL_TIM_CHANNEL_CH3
452 * @arg @ref LL_TIM_CHANNEL_CH4
453 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
454 * structure)
455 * @retval An ErrorStatus enumeration value:
456 * - SUCCESS: TIMx output channel is initialized
457 * - ERROR: TIMx output channel is not initialized
458 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)459 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
460 {
461 ErrorStatus result = ERROR;
462
463 switch (Channel)
464 {
465 case LL_TIM_CHANNEL_CH1:
466 result = IC1Config(TIMx, TIM_IC_InitStruct);
467 break;
468 case LL_TIM_CHANNEL_CH2:
469 result = IC2Config(TIMx, TIM_IC_InitStruct);
470 break;
471 case LL_TIM_CHANNEL_CH3:
472 result = IC3Config(TIMx, TIM_IC_InitStruct);
473 break;
474 case LL_TIM_CHANNEL_CH4:
475 result = IC4Config(TIMx, TIM_IC_InitStruct);
476 break;
477 default:
478 break;
479 }
480
481 return result;
482 }
483
484 /**
485 * @brief Fills each TIM_EncoderInitStruct field with its default value
486 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
487 * configuration data structure)
488 * @retval None
489 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)490 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
491 {
492 /* Set the default configuration */
493 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
494 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
495 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
496 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
497 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
498 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
499 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
500 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
501 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
502 }
503
504 /**
505 * @brief Configure the encoder interface of the timer instance.
506 * @param TIMx Timer Instance
507 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
508 * configuration data structure)
509 * @retval An ErrorStatus enumeration value:
510 * - SUCCESS: TIMx registers are de-initialized
511 * - ERROR: not applicable
512 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)513 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
514 {
515 uint32_t tmpccmr1;
516 uint32_t tmpccer;
517
518 /* Check the parameters */
519 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
520 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
521 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
522 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
523 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
524 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
525 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
526 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
527 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
528 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
529
530 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
531 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
532
533 /* Get the TIMx CCMR1 register value */
534 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
535
536 /* Get the TIMx CCER register value */
537 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
538
539 /* Configure TI1 */
540 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
541 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
542 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
543 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
544
545 /* Configure TI2 */
546 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
547 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
548 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
549 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
550
551 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
552 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
553 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
554 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
555 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
556
557 /* Set encoder mode */
558 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
559
560 /* Write to TIMx CCMR1 */
561 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
562
563 /* Write to TIMx CCER */
564 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
565
566 return SUCCESS;
567 }
568
569 /**
570 * @brief Set the fields of the TIMx Hall sensor interface configuration data
571 * structure to their default values.
572 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
573 * configuration data structure)
574 * @retval None
575 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)576 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
577 {
578 /* Set the default configuration */
579 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
580 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
581 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
582 TIM_HallSensorInitStruct->CommutationDelay = 0U;
583 }
584
585 /**
586 * @brief Configure the Hall sensor interface of the timer instance.
587 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
588 * to the TI1 input channel
589 * @note TIMx slave mode controller is configured in reset mode.
590 Selected internal trigger is TI1F_ED.
591 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
592 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
593 * between 2 changes on the inputs. It gives information about motor speed.
594 * @note Channel 2 is configured in output PWM 2 mode.
595 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
596 * @note OC2REF is selected as trigger output on TRGO.
597 * @param TIMx Timer Instance
598 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
599 * interface configuration data structure)
600 * @retval An ErrorStatus enumeration value:
601 * - SUCCESS: TIMx registers are de-initialized
602 * - ERROR: not applicable
603 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)604 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
605 {
606 uint32_t tmpcr2;
607 uint32_t tmpccmr1;
608 uint32_t tmpccer;
609 uint32_t tmpsmcr;
610
611 /* Check the parameters */
612 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
613 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
614 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
615 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
616
617 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
618 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
619
620 /* Get the TIMx CR2 register value */
621 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
622
623 /* Get the TIMx CCMR1 register value */
624 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
625
626 /* Get the TIMx CCER register value */
627 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
628
629 /* Get the TIMx SMCR register value */
630 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
631
632 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
633 tmpcr2 |= TIM_CR2_TI1S;
634
635 /* OC2REF signal is used as trigger output (TRGO) */
636 tmpcr2 |= LL_TIM_TRGO_OC2REF;
637
638 /* Configure the slave mode controller */
639 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
640 tmpsmcr |= LL_TIM_TS_TI1F_ED;
641 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
642
643 /* Configure input channel 1 */
644 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
645 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
646 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
647 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
648
649 /* Configure input channel 2 */
650 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
651 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
652
653 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
654 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
655 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
656 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
657
658 /* Write to TIMx CR2 */
659 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
660
661 /* Write to TIMx SMCR */
662 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
663
664 /* Write to TIMx CCMR1 */
665 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
666
667 /* Write to TIMx CCER */
668 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
669
670 /* Write to TIMx CCR2 */
671 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
672
673 return SUCCESS;
674 }
675
676 /**
677 * @brief Set the fields of the Break and Dead Time configuration data structure
678 * to their default values.
679 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
680 * data structure)
681 * @retval None
682 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)683 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
684 {
685 /* Set the default configuration */
686 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
687 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
688 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
689 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
690 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
691 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
692 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
693 }
694
695 /**
696 * @brief Configure the Break and Dead Time feature of the timer instance.
697 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
698 * depending on the LOCK configuration, it can be necessary to configure all of
699 * them during the first write access to the TIMx_BDTR register.
700 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
701 * a timer instance provides a break input.
702 * @param TIMx Timer Instance
703 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
704 * data structure)
705 * @retval An ErrorStatus enumeration value:
706 * - SUCCESS: Break and Dead Time is initialized
707 * - ERROR: not applicable
708 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)709 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
710 {
711 uint32_t tmpbdtr = 0;
712
713 /* Check the parameters */
714 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
715 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
716 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
717 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
718 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
719 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
720 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
721
722 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
723 the OSSI State, the dead time value and the Automatic Output Enable Bit */
724
725 /* Set the BDTR bits */
726 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
727 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
728 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
729 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
730 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
731 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
732 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
733 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
734
735 /* Set TIMx_BDTR */
736 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
737
738 return SUCCESS;
739 }
740 /**
741 * @}
742 */
743
744 /**
745 * @}
746 */
747
748 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
749 * @brief Private functions
750 * @{
751 */
752 /**
753 * @brief Configure the TIMx output channel 1.
754 * @param TIMx Timer Instance
755 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
756 * @retval An ErrorStatus enumeration value:
757 * - SUCCESS: TIMx registers are de-initialized
758 * - ERROR: not applicable
759 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)760 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
761 {
762 uint32_t tmpccmr1;
763 uint32_t tmpccer;
764 uint32_t tmpcr2;
765
766 /* Check the parameters */
767 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
768 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
769 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
770 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
771 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
772 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
773
774 /* Disable the Channel 1: Reset the CC1E Bit */
775 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
776
777 /* Get the TIMx CCER register value */
778 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
779
780 /* Get the TIMx CR2 register value */
781 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
782
783 /* Get the TIMx CCMR1 register value */
784 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
785
786 /* Reset Capture/Compare selection Bits */
787 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
788
789 /* Set the Output Compare Mode */
790 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
791
792 /* Set the Output Compare Polarity */
793 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
794
795 /* Set the Output State */
796 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
797
798 if (IS_TIM_BREAK_INSTANCE(TIMx))
799 {
800 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
801 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
802
803 /* Set the complementary output Polarity */
804 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
805
806 /* Set the complementary output State */
807 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
808
809 /* Set the Output Idle state */
810 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
811
812 /* Set the complementary output Idle state */
813 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
814 }
815
816 /* Write to TIMx CR2 */
817 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
818
819 /* Write to TIMx CCMR1 */
820 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
821
822 /* Set the Capture Compare Register value */
823 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
824
825 /* Write to TIMx CCER */
826 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
827
828 return SUCCESS;
829 }
830
831 /**
832 * @brief Configure the TIMx output channel 2.
833 * @param TIMx Timer Instance
834 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
835 * @retval An ErrorStatus enumeration value:
836 * - SUCCESS: TIMx registers are de-initialized
837 * - ERROR: not applicable
838 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)839 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
840 {
841 uint32_t tmpccmr1;
842 uint32_t tmpccer;
843 uint32_t tmpcr2;
844
845 /* Check the parameters */
846 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
847 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
848 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
849 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
850 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
851 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
852
853 /* Disable the Channel 2: Reset the CC2E Bit */
854 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
855
856 /* Get the TIMx CCER register value */
857 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
858
859 /* Get the TIMx CR2 register value */
860 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
861
862 /* Get the TIMx CCMR1 register value */
863 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
864
865 /* Reset Capture/Compare selection Bits */
866 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
867
868 /* Select the Output Compare Mode */
869 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
870
871 /* Set the Output Compare Polarity */
872 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
873
874 /* Set the Output State */
875 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
876
877 if (IS_TIM_BREAK_INSTANCE(TIMx))
878 {
879 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
880 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
881
882 /* Set the complementary output Polarity */
883 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
884
885 /* Set the complementary output State */
886 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
887
888 /* Set the Output Idle state */
889 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
890
891 /* Set the complementary output Idle state */
892 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
893 }
894
895 /* Write to TIMx CR2 */
896 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
897
898 /* Write to TIMx CCMR1 */
899 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
900
901 /* Set the Capture Compare Register value */
902 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
903
904 /* Write to TIMx CCER */
905 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
906
907 return SUCCESS;
908 }
909
910 /**
911 * @brief Configure the TIMx output channel 3.
912 * @param TIMx Timer Instance
913 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
914 * @retval An ErrorStatus enumeration value:
915 * - SUCCESS: TIMx registers are de-initialized
916 * - ERROR: not applicable
917 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)918 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
919 {
920 uint32_t tmpccmr2;
921 uint32_t tmpccer;
922 uint32_t tmpcr2;
923
924 /* Check the parameters */
925 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
926 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
927 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
928 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
929 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
930 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
931
932 /* Disable the Channel 3: Reset the CC3E Bit */
933 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
934
935 /* Get the TIMx CCER register value */
936 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
937
938 /* Get the TIMx CR2 register value */
939 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
940
941 /* Get the TIMx CCMR2 register value */
942 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
943
944 /* Reset Capture/Compare selection Bits */
945 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
946
947 /* Select the Output Compare Mode */
948 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
949
950 /* Set the Output Compare Polarity */
951 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
952
953 /* Set the Output State */
954 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
955
956 if (IS_TIM_BREAK_INSTANCE(TIMx))
957 {
958 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
959 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
960
961 /* Set the complementary output Polarity */
962 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
963
964 /* Set the complementary output State */
965 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
966
967 /* Set the Output Idle state */
968 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
969
970 /* Set the complementary output Idle state */
971 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
972 }
973
974 /* Write to TIMx CR2 */
975 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
976
977 /* Write to TIMx CCMR2 */
978 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
979
980 /* Set the Capture Compare Register value */
981 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
982
983 /* Write to TIMx CCER */
984 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
985
986 return SUCCESS;
987 }
988
989 /**
990 * @brief Configure the TIMx output channel 4.
991 * @param TIMx Timer Instance
992 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
993 * @retval An ErrorStatus enumeration value:
994 * - SUCCESS: TIMx registers are de-initialized
995 * - ERROR: not applicable
996 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)997 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
998 {
999 uint32_t tmpccmr2;
1000 uint32_t tmpccer;
1001 uint32_t tmpcr2;
1002
1003 /* Check the parameters */
1004 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1005 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1006 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1007 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1008 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1009 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1010
1011 /* Disable the Channel 4: Reset the CC4E Bit */
1012 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1013
1014 /* Get the TIMx CCER register value */
1015 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1016
1017 /* Get the TIMx CR2 register value */
1018 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1019
1020 /* Get the TIMx CCMR2 register value */
1021 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1022
1023 /* Reset Capture/Compare selection Bits */
1024 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1025
1026 /* Select the Output Compare Mode */
1027 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1028
1029 /* Set the Output Compare Polarity */
1030 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1031
1032 /* Set the Output State */
1033 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1034
1035 if (IS_TIM_BREAK_INSTANCE(TIMx))
1036 {
1037 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1038 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1039
1040 /* Set the Output Idle state */
1041 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1042 }
1043
1044 /* Write to TIMx CR2 */
1045 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1046
1047 /* Write to TIMx CCMR2 */
1048 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1049
1050 /* Set the Capture Compare Register value */
1051 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1052
1053 /* Write to TIMx CCER */
1054 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1055
1056 return SUCCESS;
1057 }
1058
1059
1060 /**
1061 * @brief Configure the TIMx input channel 1.
1062 * @param TIMx Timer Instance
1063 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1064 * @retval An ErrorStatus enumeration value:
1065 * - SUCCESS: TIMx registers are de-initialized
1066 * - ERROR: not applicable
1067 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1068 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1069 {
1070 /* Check the parameters */
1071 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1072 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1073 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1074 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1075 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1076
1077 /* Disable the Channel 1: Reset the CC1E Bit */
1078 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1079
1080 /* Select the Input and set the filter and the prescaler value */
1081 MODIFY_REG(TIMx->CCMR1,
1082 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1083 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1084
1085 /* Select the Polarity and set the CC1E Bit */
1086 MODIFY_REG(TIMx->CCER,
1087 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1088 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1089
1090 return SUCCESS;
1091 }
1092
1093 /**
1094 * @brief Configure the TIMx input channel 2.
1095 * @param TIMx Timer Instance
1096 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1097 * @retval An ErrorStatus enumeration value:
1098 * - SUCCESS: TIMx registers are de-initialized
1099 * - ERROR: not applicable
1100 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1101 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1102 {
1103 /* Check the parameters */
1104 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1105 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1106 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1107 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1108 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1109
1110 /* Disable the Channel 2: Reset the CC2E Bit */
1111 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1112
1113 /* Select the Input and set the filter and the prescaler value */
1114 MODIFY_REG(TIMx->CCMR1,
1115 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1116 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1117
1118 /* Select the Polarity and set the CC2E Bit */
1119 MODIFY_REG(TIMx->CCER,
1120 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1121 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1122
1123 return SUCCESS;
1124 }
1125
1126 /**
1127 * @brief Configure the TIMx input channel 3.
1128 * @param TIMx Timer Instance
1129 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1130 * @retval An ErrorStatus enumeration value:
1131 * - SUCCESS: TIMx registers are de-initialized
1132 * - ERROR: not applicable
1133 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1134 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1135 {
1136 /* Check the parameters */
1137 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1138 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1139 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1140 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1141 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1142
1143 /* Disable the Channel 3: Reset the CC3E Bit */
1144 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1145
1146 /* Select the Input and set the filter and the prescaler value */
1147 MODIFY_REG(TIMx->CCMR2,
1148 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1149 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1150
1151 /* Select the Polarity and set the CC3E Bit */
1152 MODIFY_REG(TIMx->CCER,
1153 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1154 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1155
1156 return SUCCESS;
1157 }
1158
1159 /**
1160 * @brief Configure the TIMx input channel 4.
1161 * @param TIMx Timer Instance
1162 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1163 * @retval An ErrorStatus enumeration value:
1164 * - SUCCESS: TIMx registers are de-initialized
1165 * - ERROR: not applicable
1166 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1167 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1168 {
1169 /* Check the parameters */
1170 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1171 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1172 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1173 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1174 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1175
1176 /* Disable the Channel 4: Reset the CC4E Bit */
1177 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1178
1179 /* Select the Input and set the filter and the prescaler value */
1180 MODIFY_REG(TIMx->CCMR2,
1181 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1182 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1183
1184 /* Select the Polarity and set the CC4E Bit */
1185 MODIFY_REG(TIMx->CCER,
1186 TIM_CCER_CC4P,
1187 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1188
1189 return SUCCESS;
1190 }
1191
1192
1193 /**
1194 * @}
1195 */
1196
1197 /**
1198 * @}
1199 */
1200
1201 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
1202
1203 /**
1204 * @}
1205 */
1206
1207 #endif /* USE_FULL_LL_DRIVER */
1208
1209 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1210
