1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f4xx_ll_tim.h"
22 #include "stm32f4xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
65
66 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
67 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
68
69 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
70 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
71
72 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
73 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
74
75 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
76 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
77 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
78
79 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
80 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
81 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
82 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
83
84 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
85 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
86 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
87 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
88 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
89 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
90 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
100
101 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
102 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
103 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
104
105 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
106 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
107 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
108
109 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
111
112 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
113 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
114
115 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
116 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
117
118 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
119 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
120 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
121 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
122
123 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
124 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
125
126 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
127 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
128
129 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
130 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
131 /**
132 * @}
133 */
134
135
136 /* Private function prototypes -----------------------------------------------*/
137 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
138 * @{
139 */
140 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
141 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
144 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
145 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
148 /**
149 * @}
150 */
151
152 /* Exported functions --------------------------------------------------------*/
153 /** @addtogroup TIM_LL_Exported_Functions
154 * @{
155 */
156
157 /** @addtogroup TIM_LL_EF_Init
158 * @{
159 */
160
161 /**
162 * @brief Set TIMx registers to their reset values.
163 * @param TIMx Timer instance
164 * @retval An ErrorStatus enumeration value:
165 * - SUCCESS: TIMx registers are de-initialized
166 * - ERROR: invalid TIMx instance
167 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)168 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
169 {
170 ErrorStatus result = SUCCESS;
171
172 /* Check the parameters */
173 assert_param(IS_TIM_INSTANCE(TIMx));
174
175 if (TIMx == TIM1)
176 {
177 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
178 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
179 }
180 #if defined(TIM2)
181 else if (TIMx == TIM2)
182 {
183 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
184 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
185 }
186 #endif /* TIM2 */
187 #if defined(TIM3)
188 else if (TIMx == TIM3)
189 {
190 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
191 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
192 }
193 #endif /* TIM3 */
194 #if defined(TIM4)
195 else if (TIMx == TIM4)
196 {
197 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
198 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
199 }
200 #endif /* TIM4 */
201 #if defined(TIM5)
202 else if (TIMx == TIM5)
203 {
204 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
205 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
206 }
207 #endif /* TIM5 */
208 #if defined(TIM6)
209 else if (TIMx == TIM6)
210 {
211 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
212 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
213 }
214 #endif /* TIM6 */
215 #if defined (TIM7)
216 else if (TIMx == TIM7)
217 {
218 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
219 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
220 }
221 #endif /* TIM7 */
222 #if defined(TIM8)
223 else if (TIMx == TIM8)
224 {
225 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
226 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
227 }
228 #endif /* TIM8 */
229 #if defined(TIM9)
230 else if (TIMx == TIM9)
231 {
232 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
233 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
234 }
235 #endif /* TIM9 */
236 #if defined(TIM10)
237 else if (TIMx == TIM10)
238 {
239 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
240 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
241 }
242 #endif /* TIM10 */
243 #if defined(TIM11)
244 else if (TIMx == TIM11)
245 {
246 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
247 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
248 }
249 #endif /* TIM11 */
250 #if defined(TIM12)
251 else if (TIMx == TIM12)
252 {
253 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
254 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
255 }
256 #endif /* TIM12 */
257 #if defined(TIM13)
258 else if (TIMx == TIM13)
259 {
260 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
261 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
262 }
263 #endif /* TIM13 */
264 #if defined(TIM14)
265 else if (TIMx == TIM14)
266 {
267 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
268 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
269 }
270 #endif /* TIM14 */
271 else
272 {
273 result = ERROR;
274 }
275
276 return result;
277 }
278
279 /**
280 * @brief Set the fields of the time base unit configuration data structure
281 * to their default values.
282 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
283 * @retval None
284 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)285 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
286 {
287 /* Set the default configuration */
288 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
289 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
290 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
291 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
292 TIM_InitStruct->RepetitionCounter = 0x00000000U;
293 }
294
295 /**
296 * @brief Configure the TIMx time base unit.
297 * @param TIMx Timer Instance
298 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
299 * (TIMx time base unit configuration data structure)
300 * @retval An ErrorStatus enumeration value:
301 * - SUCCESS: TIMx registers are de-initialized
302 * - ERROR: not applicable
303 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)304 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
305 {
306 uint32_t tmpcr1;
307
308 /* Check the parameters */
309 assert_param(IS_TIM_INSTANCE(TIMx));
310 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
311 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
312
313 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
314
315 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
316 {
317 /* Select the Counter Mode */
318 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
319 }
320
321 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
322 {
323 /* Set the clock division */
324 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
325 }
326
327 /* Write to TIMx CR1 */
328 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
329
330 /* Set the Autoreload value */
331 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
332
333 /* Set the Prescaler value */
334 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
335
336 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
337 {
338 /* Set the Repetition Counter value */
339 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
340 }
341
342 /* Generate an update event to reload the Prescaler
343 and the repetition counter value (if applicable) immediately */
344 LL_TIM_GenerateEvent_UPDATE(TIMx);
345
346 return SUCCESS;
347 }
348
349 /**
350 * @brief Set the fields of the TIMx output channel configuration data
351 * structure to their default values.
352 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
353 * (the output channel configuration data structure)
354 * @retval None
355 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)356 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
357 {
358 /* Set the default configuration */
359 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
360 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
361 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
362 TIM_OC_InitStruct->CompareValue = 0x00000000U;
363 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
364 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
365 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
366 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
367 }
368
369 /**
370 * @brief Configure the TIMx output channel.
371 * @param TIMx Timer Instance
372 * @param Channel This parameter can be one of the following values:
373 * @arg @ref LL_TIM_CHANNEL_CH1
374 * @arg @ref LL_TIM_CHANNEL_CH2
375 * @arg @ref LL_TIM_CHANNEL_CH3
376 * @arg @ref LL_TIM_CHANNEL_CH4
377 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
378 * data structure)
379 * @retval An ErrorStatus enumeration value:
380 * - SUCCESS: TIMx output channel is initialized
381 * - ERROR: TIMx output channel is not initialized
382 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)383 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
384 {
385 ErrorStatus result = ERROR;
386
387 switch (Channel)
388 {
389 case LL_TIM_CHANNEL_CH1:
390 result = OC1Config(TIMx, TIM_OC_InitStruct);
391 break;
392 case LL_TIM_CHANNEL_CH2:
393 result = OC2Config(TIMx, TIM_OC_InitStruct);
394 break;
395 case LL_TIM_CHANNEL_CH3:
396 result = OC3Config(TIMx, TIM_OC_InitStruct);
397 break;
398 case LL_TIM_CHANNEL_CH4:
399 result = OC4Config(TIMx, TIM_OC_InitStruct);
400 break;
401 default:
402 break;
403 }
404
405 return result;
406 }
407
408 /**
409 * @brief Set the fields of the TIMx input channel configuration data
410 * structure to their default values.
411 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
412 * data structure)
413 * @retval None
414 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)415 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
416 {
417 /* Set the default configuration */
418 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
419 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
420 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
421 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
422 }
423
424 /**
425 * @brief Configure the TIMx input channel.
426 * @param TIMx Timer Instance
427 * @param Channel This parameter can be one of the following values:
428 * @arg @ref LL_TIM_CHANNEL_CH1
429 * @arg @ref LL_TIM_CHANNEL_CH2
430 * @arg @ref LL_TIM_CHANNEL_CH3
431 * @arg @ref LL_TIM_CHANNEL_CH4
432 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
433 * structure)
434 * @retval An ErrorStatus enumeration value:
435 * - SUCCESS: TIMx output channel is initialized
436 * - ERROR: TIMx output channel is not initialized
437 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)438 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
439 {
440 ErrorStatus result = ERROR;
441
442 switch (Channel)
443 {
444 case LL_TIM_CHANNEL_CH1:
445 result = IC1Config(TIMx, TIM_IC_InitStruct);
446 break;
447 case LL_TIM_CHANNEL_CH2:
448 result = IC2Config(TIMx, TIM_IC_InitStruct);
449 break;
450 case LL_TIM_CHANNEL_CH3:
451 result = IC3Config(TIMx, TIM_IC_InitStruct);
452 break;
453 case LL_TIM_CHANNEL_CH4:
454 result = IC4Config(TIMx, TIM_IC_InitStruct);
455 break;
456 default:
457 break;
458 }
459
460 return result;
461 }
462
463 /**
464 * @brief Fills each TIM_EncoderInitStruct field with its default value
465 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
466 * configuration data structure)
467 * @retval None
468 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)469 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
470 {
471 /* Set the default configuration */
472 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
473 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
474 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
475 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
476 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
477 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
478 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
479 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
480 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
481 }
482
483 /**
484 * @brief Configure the encoder interface of the timer instance.
485 * @param TIMx Timer Instance
486 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
487 * configuration data structure)
488 * @retval An ErrorStatus enumeration value:
489 * - SUCCESS: TIMx registers are de-initialized
490 * - ERROR: not applicable
491 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)492 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
493 {
494 uint32_t tmpccmr1;
495 uint32_t tmpccer;
496
497 /* Check the parameters */
498 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
499 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
500 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
501 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
502 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
503 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
504 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
505 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
506 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
507 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
508
509 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
510 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
511
512 /* Get the TIMx CCMR1 register value */
513 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
514
515 /* Get the TIMx CCER register value */
516 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
517
518 /* Configure TI1 */
519 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
520 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
521 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
522 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
523
524 /* Configure TI2 */
525 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
526 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
527 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
528 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
529
530 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
531 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
532 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
533 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
534 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
535
536 /* Set encoder mode */
537 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
538
539 /* Write to TIMx CCMR1 */
540 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
541
542 /* Write to TIMx CCER */
543 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
544
545 return SUCCESS;
546 }
547
548 /**
549 * @brief Set the fields of the TIMx Hall sensor interface configuration data
550 * structure to their default values.
551 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
552 * configuration data structure)
553 * @retval None
554 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)555 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
556 {
557 /* Set the default configuration */
558 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
559 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
560 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
561 TIM_HallSensorInitStruct->CommutationDelay = 0U;
562 }
563
564 /**
565 * @brief Configure the Hall sensor interface of the timer instance.
566 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
567 * to the TI1 input channel
568 * @note TIMx slave mode controller is configured in reset mode.
569 Selected internal trigger is TI1F_ED.
570 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
571 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
572 * between 2 changes on the inputs. It gives information about motor speed.
573 * @note Channel 2 is configured in output PWM 2 mode.
574 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
575 * @note OC2REF is selected as trigger output on TRGO.
576 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
577 * when TIMx operates in Hall sensor interface mode.
578 * @param TIMx Timer Instance
579 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
580 * interface configuration data structure)
581 * @retval An ErrorStatus enumeration value:
582 * - SUCCESS: TIMx registers are de-initialized
583 * - ERROR: not applicable
584 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)585 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
586 {
587 uint32_t tmpcr2;
588 uint32_t tmpccmr1;
589 uint32_t tmpccer;
590 uint32_t tmpsmcr;
591
592 /* Check the parameters */
593 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
594 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
595 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
596 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
597
598 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
599 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
600
601 /* Get the TIMx CR2 register value */
602 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
603
604 /* Get the TIMx CCMR1 register value */
605 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
606
607 /* Get the TIMx CCER register value */
608 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
609
610 /* Get the TIMx SMCR register value */
611 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
612
613 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
614 tmpcr2 |= TIM_CR2_TI1S;
615
616 /* OC2REF signal is used as trigger output (TRGO) */
617 tmpcr2 |= LL_TIM_TRGO_OC2REF;
618
619 /* Configure the slave mode controller */
620 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
621 tmpsmcr |= LL_TIM_TS_TI1F_ED;
622 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
623
624 /* Configure input channel 1 */
625 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
626 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
627 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
628 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
629
630 /* Configure input channel 2 */
631 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
632 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
633
634 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
635 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
636 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
637 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
638
639 /* Write to TIMx CR2 */
640 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
641
642 /* Write to TIMx SMCR */
643 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
644
645 /* Write to TIMx CCMR1 */
646 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
647
648 /* Write to TIMx CCER */
649 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
650
651 /* Write to TIMx CCR2 */
652 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
653
654 return SUCCESS;
655 }
656
657 /**
658 * @brief Set the fields of the Break and Dead Time configuration data structure
659 * to their default values.
660 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
661 * data structure)
662 * @retval None
663 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)664 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
665 {
666 /* Set the default configuration */
667 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
668 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
669 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
670 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
671 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
672 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
673 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
674 }
675
676 /**
677 * @brief Configure the Break and Dead Time feature of the timer instance.
678 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
679 * depending on the LOCK configuration, it can be necessary to configure all of
680 * them during the first write access to the TIMx_BDTR register.
681 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
682 * a timer instance provides a break input.
683 * @param TIMx Timer Instance
684 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
685 * data structure)
686 * @retval An ErrorStatus enumeration value:
687 * - SUCCESS: Break and Dead Time is initialized
688 * - ERROR: not applicable
689 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)690 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
691 {
692 uint32_t tmpbdtr = 0;
693
694 /* Check the parameters */
695 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
696 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
697 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
698 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
699 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
700 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
701 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
702
703 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
704 the OSSI State, the dead time value and the Automatic Output Enable Bit */
705
706 /* Set the BDTR bits */
707 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
708 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
709 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
710 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
711 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
712 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
713 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
714 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
715
716 /* Set TIMx_BDTR */
717 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
718
719 return SUCCESS;
720 }
721 /**
722 * @}
723 */
724
725 /**
726 * @}
727 */
728
729 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
730 * @brief Private functions
731 * @{
732 */
733 /**
734 * @brief Configure the TIMx output channel 1.
735 * @param TIMx Timer Instance
736 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
737 * @retval An ErrorStatus enumeration value:
738 * - SUCCESS: TIMx registers are de-initialized
739 * - ERROR: not applicable
740 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)741 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
742 {
743 uint32_t tmpccmr1;
744 uint32_t tmpccer;
745 uint32_t tmpcr2;
746
747 /* Check the parameters */
748 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
749 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
750 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
751 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
752 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
753 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
754
755 /* Disable the Channel 1: Reset the CC1E Bit */
756 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
757
758 /* Get the TIMx CCER register value */
759 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
760
761 /* Get the TIMx CR2 register value */
762 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
763
764 /* Get the TIMx CCMR1 register value */
765 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
766
767 /* Reset Capture/Compare selection Bits */
768 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
769
770 /* Set the Output Compare Mode */
771 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
772
773 /* Set the Output Compare Polarity */
774 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
775
776 /* Set the Output State */
777 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
778
779 if (IS_TIM_BREAK_INSTANCE(TIMx))
780 {
781 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
782 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
783
784 /* Set the complementary output Polarity */
785 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
786
787 /* Set the complementary output State */
788 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
789
790 /* Set the Output Idle state */
791 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
792
793 /* Set the complementary output Idle state */
794 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
795 }
796
797 /* Write to TIMx CR2 */
798 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
799
800 /* Write to TIMx CCMR1 */
801 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
802
803 /* Set the Capture Compare Register value */
804 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
805
806 /* Write to TIMx CCER */
807 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
808
809 return SUCCESS;
810 }
811
812 /**
813 * @brief Configure the TIMx output channel 2.
814 * @param TIMx Timer Instance
815 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
816 * @retval An ErrorStatus enumeration value:
817 * - SUCCESS: TIMx registers are de-initialized
818 * - ERROR: not applicable
819 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)820 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
821 {
822 uint32_t tmpccmr1;
823 uint32_t tmpccer;
824 uint32_t tmpcr2;
825
826 /* Check the parameters */
827 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
828 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
829 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
830 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
831 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
832 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
833
834 /* Disable the Channel 2: Reset the CC2E Bit */
835 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
836
837 /* Get the TIMx CCER register value */
838 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
839
840 /* Get the TIMx CR2 register value */
841 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
842
843 /* Get the TIMx CCMR1 register value */
844 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
845
846 /* Reset Capture/Compare selection Bits */
847 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
848
849 /* Select the Output Compare Mode */
850 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
851
852 /* Set the Output Compare Polarity */
853 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
854
855 /* Set the Output State */
856 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
857
858 if (IS_TIM_BREAK_INSTANCE(TIMx))
859 {
860 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
861 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
862
863 /* Set the complementary output Polarity */
864 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
865
866 /* Set the complementary output State */
867 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
868
869 /* Set the Output Idle state */
870 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
871
872 /* Set the complementary output Idle state */
873 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
874 }
875
876 /* Write to TIMx CR2 */
877 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
878
879 /* Write to TIMx CCMR1 */
880 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
881
882 /* Set the Capture Compare Register value */
883 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
884
885 /* Write to TIMx CCER */
886 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
887
888 return SUCCESS;
889 }
890
891 /**
892 * @brief Configure the TIMx output channel 3.
893 * @param TIMx Timer Instance
894 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
895 * @retval An ErrorStatus enumeration value:
896 * - SUCCESS: TIMx registers are de-initialized
897 * - ERROR: not applicable
898 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)899 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
900 {
901 uint32_t tmpccmr2;
902 uint32_t tmpccer;
903 uint32_t tmpcr2;
904
905 /* Check the parameters */
906 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
907 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
908 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
909 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
910 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
911 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
912
913 /* Disable the Channel 3: Reset the CC3E Bit */
914 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
915
916 /* Get the TIMx CCER register value */
917 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
918
919 /* Get the TIMx CR2 register value */
920 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
921
922 /* Get the TIMx CCMR2 register value */
923 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
924
925 /* Reset Capture/Compare selection Bits */
926 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
927
928 /* Select the Output Compare Mode */
929 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
930
931 /* Set the Output Compare Polarity */
932 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
933
934 /* Set the Output State */
935 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
936
937 if (IS_TIM_BREAK_INSTANCE(TIMx))
938 {
939 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
940 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
941
942 /* Set the complementary output Polarity */
943 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
944
945 /* Set the complementary output State */
946 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
947
948 /* Set the Output Idle state */
949 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
950
951 /* Set the complementary output Idle state */
952 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
953 }
954
955 /* Write to TIMx CR2 */
956 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
957
958 /* Write to TIMx CCMR2 */
959 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
960
961 /* Set the Capture Compare Register value */
962 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
963
964 /* Write to TIMx CCER */
965 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
966
967 return SUCCESS;
968 }
969
970 /**
971 * @brief Configure the TIMx output channel 4.
972 * @param TIMx Timer Instance
973 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
974 * @retval An ErrorStatus enumeration value:
975 * - SUCCESS: TIMx registers are de-initialized
976 * - ERROR: not applicable
977 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)978 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
979 {
980 uint32_t tmpccmr2;
981 uint32_t tmpccer;
982 uint32_t tmpcr2;
983
984 /* Check the parameters */
985 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
986 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
987 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
988 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
989 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
990 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
991
992 /* Disable the Channel 4: Reset the CC4E Bit */
993 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
994
995 /* Get the TIMx CCER register value */
996 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
997
998 /* Get the TIMx CR2 register value */
999 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1000
1001 /* Get the TIMx CCMR2 register value */
1002 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1003
1004 /* Reset Capture/Compare selection Bits */
1005 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1006
1007 /* Select the Output Compare Mode */
1008 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1009
1010 /* Set the Output Compare Polarity */
1011 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1012
1013 /* Set the Output State */
1014 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1015
1016 if (IS_TIM_BREAK_INSTANCE(TIMx))
1017 {
1018 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1019 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1020
1021 /* Set the Output Idle state */
1022 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1023 }
1024
1025 /* Write to TIMx CR2 */
1026 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1027
1028 /* Write to TIMx CCMR2 */
1029 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1030
1031 /* Set the Capture Compare Register value */
1032 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1033
1034 /* Write to TIMx CCER */
1035 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1036
1037 return SUCCESS;
1038 }
1039
1040
1041 /**
1042 * @brief Configure the TIMx input channel 1.
1043 * @param TIMx Timer Instance
1044 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1045 * @retval An ErrorStatus enumeration value:
1046 * - SUCCESS: TIMx registers are de-initialized
1047 * - ERROR: not applicable
1048 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1049 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1050 {
1051 /* Check the parameters */
1052 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1053 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1054 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1055 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1056 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1057
1058 /* Disable the Channel 1: Reset the CC1E Bit */
1059 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1060
1061 /* Select the Input and set the filter and the prescaler value */
1062 MODIFY_REG(TIMx->CCMR1,
1063 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1064 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1065
1066 /* Select the Polarity and set the CC1E Bit */
1067 MODIFY_REG(TIMx->CCER,
1068 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1069 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1070
1071 return SUCCESS;
1072 }
1073
1074 /**
1075 * @brief Configure the TIMx input channel 2.
1076 * @param TIMx Timer Instance
1077 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1078 * @retval An ErrorStatus enumeration value:
1079 * - SUCCESS: TIMx registers are de-initialized
1080 * - ERROR: not applicable
1081 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1082 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1083 {
1084 /* Check the parameters */
1085 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1086 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1087 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1088 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1089 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1090
1091 /* Disable the Channel 2: Reset the CC2E Bit */
1092 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1093
1094 /* Select the Input and set the filter and the prescaler value */
1095 MODIFY_REG(TIMx->CCMR1,
1096 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1097 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1098
1099 /* Select the Polarity and set the CC2E Bit */
1100 MODIFY_REG(TIMx->CCER,
1101 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1102 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1103
1104 return SUCCESS;
1105 }
1106
1107 /**
1108 * @brief Configure the TIMx input channel 3.
1109 * @param TIMx Timer Instance
1110 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1111 * @retval An ErrorStatus enumeration value:
1112 * - SUCCESS: TIMx registers are de-initialized
1113 * - ERROR: not applicable
1114 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1115 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1116 {
1117 /* Check the parameters */
1118 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1119 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1120 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1121 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1122 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1123
1124 /* Disable the Channel 3: Reset the CC3E Bit */
1125 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1126
1127 /* Select the Input and set the filter and the prescaler value */
1128 MODIFY_REG(TIMx->CCMR2,
1129 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1130 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1131
1132 /* Select the Polarity and set the CC3E Bit */
1133 MODIFY_REG(TIMx->CCER,
1134 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1135 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1136
1137 return SUCCESS;
1138 }
1139
1140 /**
1141 * @brief Configure the TIMx input channel 4.
1142 * @param TIMx Timer Instance
1143 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1144 * @retval An ErrorStatus enumeration value:
1145 * - SUCCESS: TIMx registers are de-initialized
1146 * - ERROR: not applicable
1147 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1148 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1149 {
1150 /* Check the parameters */
1151 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1152 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1153 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1154 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1155 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1156
1157 /* Disable the Channel 4: Reset the CC4E Bit */
1158 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1159
1160 /* Select the Input and set the filter and the prescaler value */
1161 MODIFY_REG(TIMx->CCMR2,
1162 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1163 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1164
1165 /* Select the Polarity and set the CC2E Bit */
1166 MODIFY_REG(TIMx->CCER,
1167 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1168 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1169
1170 return SUCCESS;
1171 }
1172
1173
1174 /**
1175 * @}
1176 */
1177
1178 /**
1179 * @}
1180 */
1181
1182 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
1183
1184 /**
1185 * @}
1186 */
1187
1188 #endif /* USE_FULL_LL_DRIVER */
1189
1190
