1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L0xx_LL_TIM_H
21 #define __STM32L0xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l0xx.h"
29
30 /** @addtogroup STM32L0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: NA */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: NA */
51 0x04U, /* 4: TIMx_CH3 */
52 0x00U, /* 5: NA */
53 0x04U /* 6: TIMx_CH4 */
54 };
55
56 static const uint8_t SHIFT_TAB_OCxx[] =
57 {
58 0U, /* 0: OC1M, OC1FE, OC1PE */
59 0U, /* 1: - NA */
60 8U, /* 2: OC2M, OC2FE, OC2PE */
61 0U, /* 3: - NA */
62 0U, /* 4: OC3M, OC3FE, OC3PE */
63 0U, /* 5: - NA */
64 8U /* 6: OC4M, OC4FE, OC4PE */
65 };
66
67 static const uint8_t SHIFT_TAB_ICxx[] =
68 {
69 0U, /* 0: CC1S, IC1PSC, IC1F */
70 0U, /* 1: - NA */
71 8U, /* 2: CC2S, IC2PSC, IC2F */
72 0U, /* 3: - NA */
73 0U, /* 4: CC3S, IC3PSC, IC3F */
74 0U, /* 5: - NA */
75 8U /* 6: CC4S, IC4PSC, IC4F */
76 };
77
78 static const uint8_t SHIFT_TAB_CCxP[] =
79 {
80 0U, /* 0: CC1P */
81 0U, /* 1: NA */
82 4U, /* 2: CC2P */
83 0U, /* 3: NA */
84 8U, /* 4: CC3P */
85 0U, /* 5: NA */
86 12U /* 6: CC4P */
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
95 * @{
96 */
97
98
99 /* Remap mask definitions */
100 #define TIMx_OR_RMP_SHIFT 16U
101 #define TIMx_OR_RMP_MASK 0x0000FFFFU
102 #define TIM2_OR_RMP_MASK ((TIM2_OR_ETR_RMP | TIM2_OR_TI4_RMP ) << TIMx_OR_RMP_SHIFT)
103 #define TIM21_OR_RMP_MASK ((TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP) << TIMx_OR_RMP_SHIFT)
104 #define TIM22_OR_RMP_MASK ((TIM22_OR_ETR_RMP | TIM22_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
105 #if defined(TIM3)
106 #define TIM3_OR_RMP_MASK ((TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | \
107 TIM3_OR_TI4_RMP) << TIMx_OR_RMP_SHIFT)
108 #endif /* TIM3 */
109
110
111
112 /**
113 * @}
114 */
115
116 /* Private macros ------------------------------------------------------------*/
117 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
118 * @{
119 */
120 /** @brief Convert channel id into channel index.
121 * @param __CHANNEL__ This parameter can be one of the following values:
122 * @arg @ref LL_TIM_CHANNEL_CH1
123 * @arg @ref LL_TIM_CHANNEL_CH2
124 * @arg @ref LL_TIM_CHANNEL_CH3
125 * @arg @ref LL_TIM_CHANNEL_CH4
126 * @retval none
127 */
128 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
129 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
130 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
131 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
132
133 /**
134 * @}
135 */
136
137
138 /* Exported types ------------------------------------------------------------*/
139 #if defined(USE_FULL_LL_DRIVER)
140 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
141 * @{
142 */
143
144 /**
145 * @brief TIM Time Base configuration structure definition.
146 */
147 typedef struct
148 {
149 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
150 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
151
152 This feature can be modified afterwards using unitary function
153 @ref LL_TIM_SetPrescaler().*/
154
155 uint32_t CounterMode; /*!< Specifies the counter mode.
156 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
157
158 This feature can be modified afterwards using unitary function
159 @ref LL_TIM_SetCounterMode().*/
160
161 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
162 Auto-Reload Register at the next update event.
163 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
164 Some timer instances may support 32 bits counters. In that case this parameter must
165 be a number between 0x0000 and 0xFFFFFFFF.
166
167 This feature can be modified afterwards using unitary function
168 @ref LL_TIM_SetAutoReload().*/
169
170 uint32_t ClockDivision; /*!< Specifies the clock division.
171 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
172
173 This feature can be modified afterwards using unitary function
174 @ref LL_TIM_SetClockDivision().*/
175 } LL_TIM_InitTypeDef;
176
177 /**
178 * @brief TIM Output Compare configuration structure definition.
179 */
180 typedef struct
181 {
182 uint32_t OCMode; /*!< Specifies the output mode.
183 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
184
185 This feature can be modified afterwards using unitary function
186 @ref LL_TIM_OC_SetMode().*/
187
188 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
189 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
190
191 This feature can be modified afterwards using unitary functions
192 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
193
194 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
195 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
196
197 This feature can be modified afterwards using unitary function
198 LL_TIM_OC_SetCompareCHx (x=1..6).*/
199
200 uint32_t OCPolarity; /*!< Specifies the output polarity.
201 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
202
203 This feature can be modified afterwards using unitary function
204 @ref LL_TIM_OC_SetPolarity().*/
205
206
207 } LL_TIM_OC_InitTypeDef;
208
209 /**
210 * @brief TIM Input Capture configuration structure definition.
211 */
212
213 typedef struct
214 {
215
216 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
217 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
218
219 This feature can be modified afterwards using unitary function
220 @ref LL_TIM_IC_SetPolarity().*/
221
222 uint32_t ICActiveInput; /*!< Specifies the input.
223 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
224
225 This feature can be modified afterwards using unitary function
226 @ref LL_TIM_IC_SetActiveInput().*/
227
228 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
229 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
230
231 This feature can be modified afterwards using unitary function
232 @ref LL_TIM_IC_SetPrescaler().*/
233
234 uint32_t ICFilter; /*!< Specifies the input capture filter.
235 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
236
237 This feature can be modified afterwards using unitary function
238 @ref LL_TIM_IC_SetFilter().*/
239 } LL_TIM_IC_InitTypeDef;
240
241
242 /**
243 * @brief TIM Encoder interface configuration structure definition.
244 */
245 typedef struct
246 {
247 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
248 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
249
250 This feature can be modified afterwards using unitary function
251 @ref LL_TIM_SetEncoderMode().*/
252
253 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
254 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
255
256 This feature can be modified afterwards using unitary function
257 @ref LL_TIM_IC_SetPolarity().*/
258
259 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
260 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
261
262 This feature can be modified afterwards using unitary function
263 @ref LL_TIM_IC_SetActiveInput().*/
264
265 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
266 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
267
268 This feature can be modified afterwards using unitary function
269 @ref LL_TIM_IC_SetPrescaler().*/
270
271 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
272 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
273
274 This feature can be modified afterwards using unitary function
275 @ref LL_TIM_IC_SetFilter().*/
276
277 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
278 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
279
280 This feature can be modified afterwards using unitary function
281 @ref LL_TIM_IC_SetPolarity().*/
282
283 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
284 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
285
286 This feature can be modified afterwards using unitary function
287 @ref LL_TIM_IC_SetActiveInput().*/
288
289 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
290 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
291
292 This feature can be modified afterwards using unitary function
293 @ref LL_TIM_IC_SetPrescaler().*/
294
295 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
296 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
297
298 This feature can be modified afterwards using unitary function
299 @ref LL_TIM_IC_SetFilter().*/
300
301 } LL_TIM_ENCODER_InitTypeDef;
302
303
304 /**
305 * @}
306 */
307 #endif /* USE_FULL_LL_DRIVER */
308
309 /* Exported constants --------------------------------------------------------*/
310 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
311 * @{
312 */
313
314 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
315 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
316 * @{
317 */
318 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
319 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
320 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
321 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
322 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
323 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
324 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
325 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
326 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
327 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
328 /**
329 * @}
330 */
331
332 /** @defgroup TIM_LL_EC_IT IT Defines
333 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
334 * @{
335 */
336 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
337 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
338 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
339 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
340 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
341 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
342 /**
343 * @}
344 */
345
346 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
347 * @{
348 */
349 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
350 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
351 /**
352 * @}
353 */
354
355 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
356 * @{
357 */
358 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
359 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
360 /**
361 * @}
362 */
363
364 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
365 * @{
366 */
367 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
368 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
369 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
370 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
371 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
372 /**
373 * @}
374 */
375
376 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
377 * @{
378 */
379 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
380 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
381 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
382 /**
383 * @}
384 */
385
386 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
387 * @{
388 */
389 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
390 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
391 /**
392 * @}
393 */
394
395
396 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
397 * @{
398 */
399 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
400 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
401 /**
402 * @}
403 */
404
405
406 /** @defgroup TIM_LL_EC_CHANNEL Channel
407 * @{
408 */
409 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
410 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
411 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
412 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
413 /**
414 * @}
415 */
416
417 #if defined(USE_FULL_LL_DRIVER)
418 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
419 * @{
420 */
421 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
422 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
423 /**
424 * @}
425 */
426 #endif /* USE_FULL_LL_DRIVER */
427
428 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
429 * @{
430 */
431 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
432 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
433 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
434 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
435 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
436 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
437 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
438 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
439 /**
440 * @}
441 */
442
443 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
444 * @{
445 */
446 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
447 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
448 /**
449 * @}
450 */
451
452
453
454 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
455 * @{
456 */
457 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
458 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
459 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
460 /**
461 * @}
462 */
463
464 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
465 * @{
466 */
467 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
468 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
469 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
470 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
471 /**
472 * @}
473 */
474
475 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
476 * @{
477 */
478 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
479 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
480 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
481 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
482 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
483 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
484 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
485 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
486 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
487 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
488 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
489 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
490 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
491 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
492 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
493 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
494 /**
495 * @}
496 */
497
498 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
499 * @{
500 */
501 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
502 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
503 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
504 /**
505 * @}
506 */
507
508 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
509 * @{
510 */
511 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
512 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
513 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
514 /**
515 * @}
516 */
517
518 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
519 * @{
520 */
521 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
522 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
523 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
524 /**
525 * @}
526 */
527
528 /** @defgroup TIM_LL_EC_TRGO Trigger Output
529 * @{
530 */
531 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
532 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
533 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
534 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
535 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
536 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
537 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
538 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
539 /**
540 * @}
541 */
542
543
544 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
545 * @{
546 */
547 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
548 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
549 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
550 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
551 /**
552 * @}
553 */
554
555 /** @defgroup TIM_LL_EC_TS Trigger Selection
556 * @{
557 */
558 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
559 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
560 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
561 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
562 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
563 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
564 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
565 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
566 /**
567 * @}
568 */
569
570 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
571 * @{
572 */
573 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
574 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
575 /**
576 * @}
577 */
578
579 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
580 * @{
581 */
582 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
583 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
584 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
585 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
586 /**
587 * @}
588 */
589
590 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
591 * @{
592 */
593 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
594 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
595 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
596 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
597 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
598 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
599 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
600 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
601 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
602 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
603 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
604 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
605 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
606 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
607 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
608 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
609 /**
610 * @}
611 */
612
613
614
615
616
617
618
619 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
620 * @{
621 */
622 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
623 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
624 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
625 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
626 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
627 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
628 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
629 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
630 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
631 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
632 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
633 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
634 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
635 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
636 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
637 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
638 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */
639 /**
640 * @}
641 */
642
643 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
644 * @{
645 */
646 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
647 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
648 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
649 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
650 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
651 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
652 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
653 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
654 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
655 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
656 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
657 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
658 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
659 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
660 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
661 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
662 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
663 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
664 /**
665 * @}
666 */
667
668
669 /** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap
670 * @{
671 */
672 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to Ored GPIO */
673 #if defined(TIM_TIM2_REMAP_HSI_SUPPORT)
674 #define LL_TIM_TIM2_ETR_RMP_HSI (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to HSI */
675 #endif /* defined(TIM_TIM2_REMAP_HSI_SUPPORT) */
676 #if defined(TIM_TIM2_REMAP_HSI48_SUPPORT)
677 #define LL_TIM_TIM2_ETR_RMP_HSI48 (TIM2_OR_ETR_RMP_2 | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to HSI48 */
678 #endif /* defined(TIM_TIM2_REMAP_HSI48_SUPPORT) */
679 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
680 #define LL_TIM_TIM2_ETR_RMP_COMP2 (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to COMP2_OUT */
681 #define LL_TIM_TIM2_ETR_RMP_COMP1 (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to COMP1_OUT */
682
683 /**
684 * @}
685 */
686
687 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
688 * @{
689 */
690 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
691 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
692 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
693 /**
694 * @}
695 */
696
697 #if defined(TIM3_OR_ETR_RMP)
698 /** @defgroup TIM_LL_EC_TIM3_ETR_RMP TIM3 External Trigger Remap
699 * @{
700 */
701 #define LL_TIM_TIM3_ETR_RMP_GPIO TIM3_OR_RMP_MASK /*!< TIM3_ETR is connected to GPIO */
702 #define LL_TIM_TIM3_ETR_RMP_HSI48DIV6 (TIM3_OR_ETR_RMP_1 | TIM3_OR_RMP_MASK) /*!< TIM3_ETR is connected to HSI48 divided by 6 */
703 /**
704 * @}
705 */
706 #endif /* defined(TIM3_OR_ETR_RMP) */
707
708 #if defined(TIM3_OR_TI1_RMP) || defined(TIM3_OR_TI2_RMP) || defined(TIM3_OR_TI4_RMP)
709 /** @defgroup TIM_LL_EC_TIM3_TI_RMP TIM3 External Inputs Remap
710 * @{
711 */
712 #define LL_TIM_TIM3_TI_RMP_TI1_USB_SOF TIM3_OR_RMP_MASK /*!< TIM3_TI1 input is connected to USB_SOF */
713 #define LL_TIM_TIM3_TI_RMP_TI1_GPIO (TIM3_OR_TI1_RMP | TIM3_OR_RMP_MASK) /*!< TIM3_TI1 input is connected to PE3, PA6, PC6 or PB4 */
714
715 #define LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF TIM3_OR_RMP_MASK /*!< Mapping PB5 to TIM22_CH2 */
716 #define LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4 (TIM3_OR_TI2_RMP | TIM3_OR_RMP_MASK) /*!< Mapping PB5 to TIM3_CH2 */
717
718 #define LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF (0x00000000U | TIM3_OR_RMP_MASK) /*!< Mapping PC9 to USB_OE */
719 #define LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2 (TIM3_OR_TI4_RMP | TIM3_OR_RMP_MASK) /*!< Mapping PC9 to TIM3_CH4 */
720 /**
721 * @}
722 */
723 #endif /*defined(TIM3_OR_TI1_RMP) or defined(TIM3_OR_TI2_RMP) or defined(TIM3_OR_TI4_RMP)*/
724
725 /** @defgroup TIM_LL_EC_TIM21_ETR_RMP TIM21 External Trigger Remap
726 * @{
727 */
728 #define LL_TIM_TIM21_ETR_RMP_GPIO TIM21_OR_RMP_MASK /*!< TIM21_ETR is connected to Ored GPIO1 */
729 #define LL_TIM_TIM21_ETR_RMP_COMP2 (TIM21_OR_ETR_RMP_0 | TIM21_OR_RMP_MASK) /*!< TIM21_ETR is connected to COMP2_OUT */
730 #define LL_TIM_TIM21_ETR_RMP_COMP1 (TIM21_OR_ETR_RMP_1 | TIM21_OR_RMP_MASK) /*!< TIM21_ETR is connected to COMP1_OUT */
731 #define LL_TIM_TIM21_ETR_RMP_LSE (TIM21_OR_ETR_RMP | TIM21_OR_RMP_MASK) /*!< TIM21_ETR is connected to LSE */
732 /**
733 * @}
734 */
735
736 /** @defgroup TIM_LL_EC_TIM21_TI1_RMP TIM21 External Input Ch1 Remap
737 * @{
738 */
739 #define LL_TIM_TIM21_TI1_RMP_GPIO TIM21_OR_RMP_MASK /*!< TIM21_TI1 is connected to Ored GPIO1 */
740 #define LL_TIM_TIM21_TI1_RMP_RTC_WK (TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to RTC_WAKEUP */
741 #define LL_TIM_TIM21_TI1_RMP_HSE_RTC (TIM21_OR_TI1_RMP_1 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to HSE_RTC */
742 #define LL_TIM_TIM21_TI1_RMP_MSI (TIM21_OR_TI1_RMP_1 | TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to MSI */
743 #define LL_TIM_TIM21_TI1_RMP_LSE (TIM21_OR_TI1_RMP_2 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to LSE */
744 #define LL_TIM_TIM21_TI1_RMP_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to LSI */
745 #define LL_TIM_TIM21_TI1_RMP_COMP1 (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to COMP1_OUT */
746 #define LL_TIM_TIM21_TI1_RMP_MCO (TIM21_OR_TI1_RMP | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to MCO */
747 /**
748 * @}
749 */
750
751 /** @defgroup TIM_LL_EC_TIM21_TI2_RMP TIM21 External Input Ch2 Remap
752 * @{
753 */
754 #define LL_TIM_TIM21_TI2_RMP_GPIO TIM21_OR_RMP_MASK /*!< TIM21_TI2 is connected to Ored GPIO1 */
755 #define LL_TIM_TIM21_TI2_RMP_COMP2 (TIM21_OR_TI2_RMP | TIM21_OR_RMP_MASK) /*!< TIM21_TI2 is connected to COMP2_OUT */
756 /**
757 * @}
758 */
759
760 #if defined(TIM22_OR_ETR_RMP)
761
762 /** @defgroup TIM_LL_EC_TIM22_ETR_RMP TIM22 External Trigger Remap
763 * @{
764 */
765 #define LL_TIM_TIM22_ETR_RMP_GPIO TIM22_OR_RMP_MASK /*!< TIM22_ETR is connected to GPIO */
766 #define LL_TIM_TIM22_ETR_RMP_COMP2 (TIM22_OR_ETR_RMP_0 | TIM22_OR_RMP_MASK) /*!< TIM22_ETR is connected to COMP2_OUT */
767 #define LL_TIM_TIM22_ETR_RMP_COMP1 (TIM22_OR_ETR_RMP_1 | TIM22_OR_RMP_MASK) /*!< TIM22_ETR is connected to COMP1_OUT */
768 #define LL_TIM_TIM22_ETR_RMP_LSE (TIM22_OR_ETR_RMP | TIM22_OR_RMP_MASK) /*!< TIM22_ETR is connected to LSE */
769 /**
770 * @}
771 */
772 #endif /* defined(TIM22_OR_ETR_RMP) */
773
774 #if defined(TIM22_OR_TI1_RMP)
775 /** @defgroup TIM_LL_EC_TIM22_TI1_RMP TIM22 External Input Ch1 Remap
776 * @{
777 */
778 #define LL_TIM_TIM22_TI1_RMP_GPIO1 TIM22_OR_RMP_MASK /*!< TIM22_TI1 is connected to GPIO1 */
779 #define LL_TIM_TIM22_TI1_RMP_COMP2 (TIM22_OR_TI1_RMP_0 | TIM22_OR_RMP_MASK) /*!< TIM22_TI1 is connected to COMP2_OUT */
780 #define LL_TIM_TIM22_TI1_RMP_COMP1 (TIM22_OR_TI1_RMP_1 | TIM22_OR_RMP_MASK) /*!< TIM22_TI1 is connected to COMP1_OUT */
781 #define LL_TIM_TIM22_TI1_RMP_GPIO2 (TIM22_OR_TI1_RMP | TIM22_OR_RMP_MASK) /*!< TIM22_TI1 is connected to GPIO2 */
782 /**
783 * @}
784 */
785 #endif /* defined(TIM22_OR_TI1_RMP) */
786
787
788
789 /**
790 * @}
791 */
792
793 /* Exported macro ------------------------------------------------------------*/
794 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
795 * @{
796 */
797
798 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
799 * @{
800 */
801 /**
802 * @brief Write a value in TIM register.
803 * @param __INSTANCE__ TIM Instance
804 * @param __REG__ Register to be written
805 * @param __VALUE__ Value to be written in the register
806 * @retval None
807 */
808 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
809
810 /**
811 * @brief Read a value in TIM register.
812 * @param __INSTANCE__ TIM Instance
813 * @param __REG__ Register to be read
814 * @retval Register value
815 */
816 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
817 /**
818 * @}
819 */
820
821 /**
822 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
823 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
824 * @param __TIMCLK__ timer input clock frequency (in Hz)
825 * @param __CNTCLK__ counter clock frequency (in Hz)
826 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
827 */
828 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
829 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
830
831 /**
832 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
833 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
834 * @param __TIMCLK__ timer input clock frequency (in Hz)
835 * @param __PSC__ prescaler
836 * @param __FREQ__ output signal frequency (in Hz)
837 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
838 */
839 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
840 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
841
842 /**
843 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
844 * active/inactive delay.
845 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
846 * @param __TIMCLK__ timer input clock frequency (in Hz)
847 * @param __PSC__ prescaler
848 * @param __DELAY__ timer output compare active/inactive delay (in us)
849 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
850 */
851 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
852 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
853 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
854
855 /**
856 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
857 * (when the timer operates in one pulse mode).
858 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
859 * @param __TIMCLK__ timer input clock frequency (in Hz)
860 * @param __PSC__ prescaler
861 * @param __DELAY__ timer output compare active/inactive delay (in us)
862 * @param __PULSE__ pulse duration (in us)
863 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
864 */
865 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
866 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
867 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
868
869 /**
870 * @brief HELPER macro retrieving the ratio of the input capture prescaler
871 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
872 * @param __ICPSC__ This parameter can be one of the following values:
873 * @arg @ref LL_TIM_ICPSC_DIV1
874 * @arg @ref LL_TIM_ICPSC_DIV2
875 * @arg @ref LL_TIM_ICPSC_DIV4
876 * @arg @ref LL_TIM_ICPSC_DIV8
877 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
878 */
879 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
880 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
881
882
883 /**
884 * @}
885 */
886
887 /* Exported functions --------------------------------------------------------*/
888 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
889 * @{
890 */
891
892 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
893 * @{
894 */
895 /**
896 * @brief Enable timer counter.
897 * @rmtoll CR1 CEN LL_TIM_EnableCounter
898 * @param TIMx Timer instance
899 * @retval None
900 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)901 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
902 {
903 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
904 }
905
906 /**
907 * @brief Disable timer counter.
908 * @rmtoll CR1 CEN LL_TIM_DisableCounter
909 * @param TIMx Timer instance
910 * @retval None
911 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)912 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
913 {
914 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
915 }
916
917 /**
918 * @brief Indicates whether the timer counter is enabled.
919 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
920 * @param TIMx Timer instance
921 * @retval State of bit (1 or 0).
922 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)923 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
924 {
925 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
926 }
927
928 /**
929 * @brief Enable update event generation.
930 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
931 * @param TIMx Timer instance
932 * @retval None
933 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)934 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
935 {
936 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
937 }
938
939 /**
940 * @brief Disable update event generation.
941 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
942 * @param TIMx Timer instance
943 * @retval None
944 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)945 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
946 {
947 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
948 }
949
950 /**
951 * @brief Indicates whether update event generation is enabled.
952 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
953 * @param TIMx Timer instance
954 * @retval Inverted state of bit (0 or 1).
955 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)956 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
957 {
958 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
959 }
960
961 /**
962 * @brief Set update event source
963 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
964 * generate an update interrupt or DMA request if enabled:
965 * - Counter overflow/underflow
966 * - Setting the UG bit
967 * - Update generation through the slave mode controller
968 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
969 * overflow/underflow generates an update interrupt or DMA request if enabled.
970 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
971 * @param TIMx Timer instance
972 * @param UpdateSource This parameter can be one of the following values:
973 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
974 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
975 * @retval None
976 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)977 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
978 {
979 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
980 }
981
982 /**
983 * @brief Get actual event update source
984 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
985 * @param TIMx Timer instance
986 * @retval Returned value can be one of the following values:
987 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
988 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
989 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)990 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
991 {
992 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
993 }
994
995 /**
996 * @brief Set one pulse mode (one shot v.s. repetitive).
997 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
998 * @param TIMx Timer instance
999 * @param OnePulseMode This parameter can be one of the following values:
1000 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1001 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1002 * @retval None
1003 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1004 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1005 {
1006 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1007 }
1008
1009 /**
1010 * @brief Get actual one pulse mode.
1011 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1012 * @param TIMx Timer instance
1013 * @retval Returned value can be one of the following values:
1014 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1015 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1016 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1017 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1018 {
1019 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1020 }
1021
1022 /**
1023 * @brief Set the timer counter counting mode.
1024 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1025 * check whether or not the counter mode selection feature is supported
1026 * by a timer instance.
1027 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1028 * requires a timer reset to avoid unexpected direction
1029 * due to DIR bit readonly in center aligned mode.
1030 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1031 * CR1 CMS LL_TIM_SetCounterMode
1032 * @param TIMx Timer instance
1033 * @param CounterMode This parameter can be one of the following values:
1034 * @arg @ref LL_TIM_COUNTERMODE_UP
1035 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1036 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1037 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1038 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1039 * @retval None
1040 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1041 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1042 {
1043 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1044 }
1045
1046 /**
1047 * @brief Get actual counter mode.
1048 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1049 * check whether or not the counter mode selection feature is supported
1050 * by a timer instance.
1051 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1052 * CR1 CMS LL_TIM_GetCounterMode
1053 * @param TIMx Timer instance
1054 * @retval Returned value can be one of the following values:
1055 * @arg @ref LL_TIM_COUNTERMODE_UP
1056 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1057 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1058 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1059 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1060 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1061 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1062 {
1063 uint32_t counter_mode;
1064
1065 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1066
1067 if (counter_mode == 0U)
1068 {
1069 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1070 }
1071
1072 return counter_mode;
1073 }
1074
1075 /**
1076 * @brief Enable auto-reload (ARR) preload.
1077 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1078 * @param TIMx Timer instance
1079 * @retval None
1080 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1081 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1082 {
1083 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1084 }
1085
1086 /**
1087 * @brief Disable auto-reload (ARR) preload.
1088 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1089 * @param TIMx Timer instance
1090 * @retval None
1091 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1092 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1093 {
1094 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1095 }
1096
1097 /**
1098 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1099 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1100 * @param TIMx Timer instance
1101 * @retval State of bit (1 or 0).
1102 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1103 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1104 {
1105 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1106 }
1107
1108 /**
1109 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1110 * (when supported) and the digital filters.
1111 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1112 * whether or not the clock division feature is supported by the timer
1113 * instance.
1114 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1115 * @param TIMx Timer instance
1116 * @param ClockDivision This parameter can be one of the following values:
1117 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1118 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1119 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1120 * @retval None
1121 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1122 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1123 {
1124 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1125 }
1126
1127 /**
1128 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1129 * generators (when supported) and the digital filters.
1130 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1131 * whether or not the clock division feature is supported by the timer
1132 * instance.
1133 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1134 * @param TIMx Timer instance
1135 * @retval Returned value can be one of the following values:
1136 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1137 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1138 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1139 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1140 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1141 {
1142 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1143 }
1144
1145 /**
1146 * @brief Set the counter value.
1147 * @rmtoll CNT CNT LL_TIM_SetCounter
1148 * @param TIMx Timer instance
1149 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
1150 * @retval None
1151 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1152 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1153 {
1154 WRITE_REG(TIMx->CNT, Counter);
1155 }
1156
1157 /**
1158 * @brief Get the counter value.
1159 * @rmtoll CNT CNT LL_TIM_GetCounter
1160 * @param TIMx Timer instance
1161 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
1162 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1163 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1164 {
1165 return (uint32_t)(READ_REG(TIMx->CNT));
1166 }
1167
1168 /**
1169 * @brief Get the current direction of the counter
1170 * @rmtoll CR1 DIR LL_TIM_GetDirection
1171 * @param TIMx Timer instance
1172 * @retval Returned value can be one of the following values:
1173 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1174 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1175 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1176 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1177 {
1178 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1179 }
1180
1181 /**
1182 * @brief Set the prescaler value.
1183 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1184 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1185 * prescaler ratio is taken into account at the next update event.
1186 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1187 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1188 * @param TIMx Timer instance
1189 * @param Prescaler between Min_Data=0 and Max_Data=65535
1190 * @retval None
1191 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1192 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1193 {
1194 WRITE_REG(TIMx->PSC, Prescaler);
1195 }
1196
1197 /**
1198 * @brief Get the prescaler value.
1199 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1200 * @param TIMx Timer instance
1201 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1202 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1203 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1204 {
1205 return (uint32_t)(READ_REG(TIMx->PSC));
1206 }
1207
1208 /**
1209 * @brief Set the auto-reload value.
1210 * @note The counter is blocked while the auto-reload value is null.
1211 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1212 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1213 * @param TIMx Timer instance
1214 * @param AutoReload between Min_Data=0 and Max_Data=65535
1215 * @retval None
1216 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1217 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1218 {
1219 WRITE_REG(TIMx->ARR, AutoReload);
1220 }
1221
1222 /**
1223 * @brief Get the auto-reload value.
1224 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1225 * @param TIMx Timer instance
1226 * @retval Auto-reload value
1227 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1228 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1229 {
1230 return (uint32_t)(READ_REG(TIMx->ARR));
1231 }
1232
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1238 * @{
1239 */
1240 /**
1241 * @brief Set the trigger of the capture/compare DMA request.
1242 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1243 * @param TIMx Timer instance
1244 * @param DMAReqTrigger This parameter can be one of the following values:
1245 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1246 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1247 * @retval None
1248 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1249 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1250 {
1251 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1252 }
1253
1254 /**
1255 * @brief Get actual trigger of the capture/compare DMA request.
1256 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1257 * @param TIMx Timer instance
1258 * @retval Returned value can be one of the following values:
1259 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1260 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1261 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1262 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1263 {
1264 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1265 }
1266
1267 /**
1268 * @brief Enable capture/compare channels.
1269 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1270 * CCER CC2E LL_TIM_CC_EnableChannel\n
1271 * CCER CC3E LL_TIM_CC_EnableChannel\n
1272 * CCER CC4E LL_TIM_CC_EnableChannel
1273 * @param TIMx Timer instance
1274 * @param Channels This parameter can be a combination of the following values:
1275 * @arg @ref LL_TIM_CHANNEL_CH1
1276 * @arg @ref LL_TIM_CHANNEL_CH2
1277 * @arg @ref LL_TIM_CHANNEL_CH3
1278 * @arg @ref LL_TIM_CHANNEL_CH4
1279 * @retval None
1280 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1281 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1282 {
1283 SET_BIT(TIMx->CCER, Channels);
1284 }
1285
1286 /**
1287 * @brief Disable capture/compare channels.
1288 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1289 * CCER CC2E LL_TIM_CC_DisableChannel\n
1290 * CCER CC3E LL_TIM_CC_DisableChannel\n
1291 * CCER CC4E LL_TIM_CC_DisableChannel
1292 * @param TIMx Timer instance
1293 * @param Channels This parameter can be a combination of the following values:
1294 * @arg @ref LL_TIM_CHANNEL_CH1
1295 * @arg @ref LL_TIM_CHANNEL_CH2
1296 * @arg @ref LL_TIM_CHANNEL_CH3
1297 * @arg @ref LL_TIM_CHANNEL_CH4
1298 * @retval None
1299 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1300 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1301 {
1302 CLEAR_BIT(TIMx->CCER, Channels);
1303 }
1304
1305 /**
1306 * @brief Indicate whether channel(s) is(are) enabled.
1307 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1308 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1309 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1310 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1311 * @param TIMx Timer instance
1312 * @param Channels This parameter can be a combination of the following values:
1313 * @arg @ref LL_TIM_CHANNEL_CH1
1314 * @arg @ref LL_TIM_CHANNEL_CH2
1315 * @arg @ref LL_TIM_CHANNEL_CH3
1316 * @arg @ref LL_TIM_CHANNEL_CH4
1317 * @retval State of bit (1 or 0).
1318 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1319 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1320 {
1321 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1322 }
1323
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1329 * @{
1330 */
1331 /**
1332 * @brief Configure an output channel.
1333 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1334 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1335 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1336 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1337 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1338 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1339 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1340 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1341 * @param TIMx Timer instance
1342 * @param Channel This parameter can be one of the following values:
1343 * @arg @ref LL_TIM_CHANNEL_CH1
1344 * @arg @ref LL_TIM_CHANNEL_CH2
1345 * @arg @ref LL_TIM_CHANNEL_CH3
1346 * @arg @ref LL_TIM_CHANNEL_CH4
1347 * @param Configuration This parameter must be a combination of all the following values:
1348 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1349 * @retval None
1350 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1351 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1352 {
1353 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1354 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1355 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1356 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1357 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1358 }
1359
1360 /**
1361 * @brief Define the behavior of the output reference signal OCxREF from which
1362 * OCx and OCxN (when relevant) are derived.
1363 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1364 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1365 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1366 * CCMR2 OC4M LL_TIM_OC_SetMode
1367 * @param TIMx Timer instance
1368 * @param Channel This parameter can be one of the following values:
1369 * @arg @ref LL_TIM_CHANNEL_CH1
1370 * @arg @ref LL_TIM_CHANNEL_CH2
1371 * @arg @ref LL_TIM_CHANNEL_CH3
1372 * @arg @ref LL_TIM_CHANNEL_CH4
1373 * @param Mode This parameter can be one of the following values:
1374 * @arg @ref LL_TIM_OCMODE_FROZEN
1375 * @arg @ref LL_TIM_OCMODE_ACTIVE
1376 * @arg @ref LL_TIM_OCMODE_INACTIVE
1377 * @arg @ref LL_TIM_OCMODE_TOGGLE
1378 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1379 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1380 * @arg @ref LL_TIM_OCMODE_PWM1
1381 * @arg @ref LL_TIM_OCMODE_PWM2
1382 * @retval None
1383 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1384 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1385 {
1386 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1387 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1388 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1389 }
1390
1391 /**
1392 * @brief Get the output compare mode of an output channel.
1393 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1394 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1395 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1396 * CCMR2 OC4M LL_TIM_OC_GetMode
1397 * @param TIMx Timer instance
1398 * @param Channel This parameter can be one of the following values:
1399 * @arg @ref LL_TIM_CHANNEL_CH1
1400 * @arg @ref LL_TIM_CHANNEL_CH2
1401 * @arg @ref LL_TIM_CHANNEL_CH3
1402 * @arg @ref LL_TIM_CHANNEL_CH4
1403 * @retval Returned value can be one of the following values:
1404 * @arg @ref LL_TIM_OCMODE_FROZEN
1405 * @arg @ref LL_TIM_OCMODE_ACTIVE
1406 * @arg @ref LL_TIM_OCMODE_INACTIVE
1407 * @arg @ref LL_TIM_OCMODE_TOGGLE
1408 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1409 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1410 * @arg @ref LL_TIM_OCMODE_PWM1
1411 * @arg @ref LL_TIM_OCMODE_PWM2
1412 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)1413 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
1414 {
1415 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1416 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1417 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1418 }
1419
1420 /**
1421 * @brief Set the polarity of an output channel.
1422 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1423 * CCER CC2P LL_TIM_OC_SetPolarity\n
1424 * CCER CC3P LL_TIM_OC_SetPolarity\n
1425 * CCER CC4P LL_TIM_OC_SetPolarity
1426 * @param TIMx Timer instance
1427 * @param Channel This parameter can be one of the following values:
1428 * @arg @ref LL_TIM_CHANNEL_CH1
1429 * @arg @ref LL_TIM_CHANNEL_CH2
1430 * @arg @ref LL_TIM_CHANNEL_CH3
1431 * @arg @ref LL_TIM_CHANNEL_CH4
1432 * @param Polarity This parameter can be one of the following values:
1433 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1434 * @arg @ref LL_TIM_OCPOLARITY_LOW
1435 * @retval None
1436 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1437 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1438 {
1439 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1440 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1441 }
1442
1443 /**
1444 * @brief Get the polarity of an output channel.
1445 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1446 * CCER CC2P LL_TIM_OC_GetPolarity\n
1447 * CCER CC3P LL_TIM_OC_GetPolarity\n
1448 * CCER CC4P LL_TIM_OC_GetPolarity
1449 * @param TIMx Timer instance
1450 * @param Channel This parameter can be one of the following values:
1451 * @arg @ref LL_TIM_CHANNEL_CH1
1452 * @arg @ref LL_TIM_CHANNEL_CH2
1453 * @arg @ref LL_TIM_CHANNEL_CH3
1454 * @arg @ref LL_TIM_CHANNEL_CH4
1455 * @retval Returned value can be one of the following values:
1456 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1457 * @arg @ref LL_TIM_OCPOLARITY_LOW
1458 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)1459 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
1460 {
1461 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1462 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1463 }
1464
1465 /**
1466 * @brief Enable fast mode for the output channel.
1467 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1468 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1469 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1470 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1471 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1472 * @param TIMx Timer instance
1473 * @param Channel This parameter can be one of the following values:
1474 * @arg @ref LL_TIM_CHANNEL_CH1
1475 * @arg @ref LL_TIM_CHANNEL_CH2
1476 * @arg @ref LL_TIM_CHANNEL_CH3
1477 * @arg @ref LL_TIM_CHANNEL_CH4
1478 * @retval None
1479 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1480 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1481 {
1482 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1483 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1484 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1485
1486 }
1487
1488 /**
1489 * @brief Disable fast mode for the output channel.
1490 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1491 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1492 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1493 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1494 * @param TIMx Timer instance
1495 * @param Channel This parameter can be one of the following values:
1496 * @arg @ref LL_TIM_CHANNEL_CH1
1497 * @arg @ref LL_TIM_CHANNEL_CH2
1498 * @arg @ref LL_TIM_CHANNEL_CH3
1499 * @arg @ref LL_TIM_CHANNEL_CH4
1500 * @retval None
1501 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1502 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1503 {
1504 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1505 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1506 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1507
1508 }
1509
1510 /**
1511 * @brief Indicates whether fast mode is enabled for the output channel.
1512 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1513 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1514 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1515 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1516 * @param TIMx Timer instance
1517 * @param Channel This parameter can be one of the following values:
1518 * @arg @ref LL_TIM_CHANNEL_CH1
1519 * @arg @ref LL_TIM_CHANNEL_CH2
1520 * @arg @ref LL_TIM_CHANNEL_CH3
1521 * @arg @ref LL_TIM_CHANNEL_CH4
1522 * @retval State of bit (1 or 0).
1523 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)1524 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
1525 {
1526 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1527 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1528 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1529 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1530 }
1531
1532 /**
1533 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1534 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1535 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1536 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1537 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1538 * @param TIMx Timer instance
1539 * @param Channel This parameter can be one of the following values:
1540 * @arg @ref LL_TIM_CHANNEL_CH1
1541 * @arg @ref LL_TIM_CHANNEL_CH2
1542 * @arg @ref LL_TIM_CHANNEL_CH3
1543 * @arg @ref LL_TIM_CHANNEL_CH4
1544 * @retval None
1545 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1546 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1547 {
1548 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1549 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1550 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1551 }
1552
1553 /**
1554 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1555 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1556 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1557 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1558 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1559 * @param TIMx Timer instance
1560 * @param Channel This parameter can be one of the following values:
1561 * @arg @ref LL_TIM_CHANNEL_CH1
1562 * @arg @ref LL_TIM_CHANNEL_CH2
1563 * @arg @ref LL_TIM_CHANNEL_CH3
1564 * @arg @ref LL_TIM_CHANNEL_CH4
1565 * @retval None
1566 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1567 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1568 {
1569 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1570 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1571 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1572 }
1573
1574 /**
1575 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1576 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1577 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1578 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1579 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
1580 * @param TIMx Timer instance
1581 * @param Channel This parameter can be one of the following values:
1582 * @arg @ref LL_TIM_CHANNEL_CH1
1583 * @arg @ref LL_TIM_CHANNEL_CH2
1584 * @arg @ref LL_TIM_CHANNEL_CH3
1585 * @arg @ref LL_TIM_CHANNEL_CH4
1586 * @retval State of bit (1 or 0).
1587 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)1588 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
1589 {
1590 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1591 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1592 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
1593 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1594 }
1595
1596 /**
1597 * @brief Enable clearing the output channel on an external event.
1598 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1599 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1600 * or not a timer instance can clear the OCxREF signal on an external event.
1601 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
1602 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
1603 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
1604 * CCMR2 OC4CE LL_TIM_OC_EnableClear
1605 * @param TIMx Timer instance
1606 * @param Channel This parameter can be one of the following values:
1607 * @arg @ref LL_TIM_CHANNEL_CH1
1608 * @arg @ref LL_TIM_CHANNEL_CH2
1609 * @arg @ref LL_TIM_CHANNEL_CH3
1610 * @arg @ref LL_TIM_CHANNEL_CH4
1611 * @retval None
1612 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)1613 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1614 {
1615 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1616 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1617 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1618 }
1619
1620 /**
1621 * @brief Disable clearing the output channel on an external event.
1622 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1623 * or not a timer instance can clear the OCxREF signal on an external event.
1624 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
1625 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
1626 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
1627 * CCMR2 OC4CE LL_TIM_OC_DisableClear
1628 * @param TIMx Timer instance
1629 * @param Channel This parameter can be one of the following values:
1630 * @arg @ref LL_TIM_CHANNEL_CH1
1631 * @arg @ref LL_TIM_CHANNEL_CH2
1632 * @arg @ref LL_TIM_CHANNEL_CH3
1633 * @arg @ref LL_TIM_CHANNEL_CH4
1634 * @retval None
1635 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)1636 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1637 {
1638 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1639 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1640 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1641 }
1642
1643 /**
1644 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
1645 * @note This function enables clearing the output channel on an external event.
1646 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1647 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1648 * or not a timer instance can clear the OCxREF signal on an external event.
1649 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
1650 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
1651 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
1652 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
1653 * @param TIMx Timer instance
1654 * @param Channel This parameter can be one of the following values:
1655 * @arg @ref LL_TIM_CHANNEL_CH1
1656 * @arg @ref LL_TIM_CHANNEL_CH2
1657 * @arg @ref LL_TIM_CHANNEL_CH3
1658 * @arg @ref LL_TIM_CHANNEL_CH4
1659 * @retval State of bit (1 or 0).
1660 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)1661 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
1662 {
1663 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1664 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1665 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
1666 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1667 }
1668
1669 /**
1670 * @brief Set compare value for output channel 1 (TIMx_CCR1).
1671 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
1672 * output channel 1 is supported by a timer instance.
1673 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
1674 * @param TIMx Timer instance
1675 * @param CompareValue between Min_Data=0 and Max_Data=65535
1676 * @retval None
1677 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)1678 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
1679 {
1680 WRITE_REG(TIMx->CCR1, CompareValue);
1681 }
1682
1683 /**
1684 * @brief Set compare value for output channel 2 (TIMx_CCR2).
1685 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
1686 * output channel 2 is supported by a timer instance.
1687 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
1688 * @param TIMx Timer instance
1689 * @param CompareValue between Min_Data=0 and Max_Data=65535
1690 * @retval None
1691 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)1692 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
1693 {
1694 WRITE_REG(TIMx->CCR2, CompareValue);
1695 }
1696
1697 /**
1698 * @brief Set compare value for output channel 3 (TIMx_CCR3).
1699 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
1700 * output channel is supported by a timer instance.
1701 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
1702 * @param TIMx Timer instance
1703 * @param CompareValue between Min_Data=0 and Max_Data=65535
1704 * @retval None
1705 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)1706 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
1707 {
1708 WRITE_REG(TIMx->CCR3, CompareValue);
1709 }
1710
1711 /**
1712 * @brief Set compare value for output channel 4 (TIMx_CCR4).
1713 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
1714 * output channel 4 is supported by a timer instance.
1715 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
1716 * @param TIMx Timer instance
1717 * @param CompareValue between Min_Data=0 and Max_Data=65535
1718 * @retval None
1719 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)1720 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
1721 {
1722 WRITE_REG(TIMx->CCR4, CompareValue);
1723 }
1724
1725 /**
1726 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
1727 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
1728 * output channel 1 is supported by a timer instance.
1729 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
1730 * @param TIMx Timer instance
1731 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
1732 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)1733 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
1734 {
1735 return (uint32_t)(READ_REG(TIMx->CCR1));
1736 }
1737
1738 /**
1739 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
1740 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
1741 * output channel 2 is supported by a timer instance.
1742 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
1743 * @param TIMx Timer instance
1744 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
1745 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)1746 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
1747 {
1748 return (uint32_t)(READ_REG(TIMx->CCR2));
1749 }
1750
1751 /**
1752 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
1753 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
1754 * output channel 3 is supported by a timer instance.
1755 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
1756 * @param TIMx Timer instance
1757 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
1758 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)1759 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
1760 {
1761 return (uint32_t)(READ_REG(TIMx->CCR3));
1762 }
1763
1764 /**
1765 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
1766 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
1767 * output channel 4 is supported by a timer instance.
1768 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
1769 * @param TIMx Timer instance
1770 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
1771 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)1772 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
1773 {
1774 return (uint32_t)(READ_REG(TIMx->CCR4));
1775 }
1776
1777 /**
1778 * @}
1779 */
1780
1781 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
1782 * @{
1783 */
1784 /**
1785 * @brief Configure input channel.
1786 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
1787 * CCMR1 IC1PSC LL_TIM_IC_Config\n
1788 * CCMR1 IC1F LL_TIM_IC_Config\n
1789 * CCMR1 CC2S LL_TIM_IC_Config\n
1790 * CCMR1 IC2PSC LL_TIM_IC_Config\n
1791 * CCMR1 IC2F LL_TIM_IC_Config\n
1792 * CCMR2 CC3S LL_TIM_IC_Config\n
1793 * CCMR2 IC3PSC LL_TIM_IC_Config\n
1794 * CCMR2 IC3F LL_TIM_IC_Config\n
1795 * CCMR2 CC4S LL_TIM_IC_Config\n
1796 * CCMR2 IC4PSC LL_TIM_IC_Config\n
1797 * CCMR2 IC4F LL_TIM_IC_Config\n
1798 * CCER CC1P LL_TIM_IC_Config\n
1799 * CCER CC1NP LL_TIM_IC_Config\n
1800 * CCER CC2P LL_TIM_IC_Config\n
1801 * CCER CC2NP LL_TIM_IC_Config\n
1802 * CCER CC3P LL_TIM_IC_Config\n
1803 * CCER CC3NP LL_TIM_IC_Config\n
1804 * CCER CC4P LL_TIM_IC_Config\n
1805 * CCER CC4NP LL_TIM_IC_Config
1806 * @param TIMx Timer instance
1807 * @param Channel This parameter can be one of the following values:
1808 * @arg @ref LL_TIM_CHANNEL_CH1
1809 * @arg @ref LL_TIM_CHANNEL_CH2
1810 * @arg @ref LL_TIM_CHANNEL_CH3
1811 * @arg @ref LL_TIM_CHANNEL_CH4
1812 * @param Configuration This parameter must be a combination of all the following values:
1813 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
1814 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
1815 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
1816 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
1817 * @retval None
1818 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1819 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1820 {
1821 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1822 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1823 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
1824 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
1825 << SHIFT_TAB_ICxx[iChannel]);
1826 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
1827 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
1828 }
1829
1830 /**
1831 * @brief Set the active input.
1832 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
1833 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
1834 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
1835 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
1836 * @param TIMx Timer instance
1837 * @param Channel This parameter can be one of the following values:
1838 * @arg @ref LL_TIM_CHANNEL_CH1
1839 * @arg @ref LL_TIM_CHANNEL_CH2
1840 * @arg @ref LL_TIM_CHANNEL_CH3
1841 * @arg @ref LL_TIM_CHANNEL_CH4
1842 * @param ICActiveInput This parameter can be one of the following values:
1843 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
1844 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
1845 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
1846 * @retval None
1847 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)1848 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
1849 {
1850 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1851 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1852 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
1853 }
1854
1855 /**
1856 * @brief Get the current active input.
1857 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
1858 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
1859 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
1860 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
1861 * @param TIMx Timer instance
1862 * @param Channel This parameter can be one of the following values:
1863 * @arg @ref LL_TIM_CHANNEL_CH1
1864 * @arg @ref LL_TIM_CHANNEL_CH2
1865 * @arg @ref LL_TIM_CHANNEL_CH3
1866 * @arg @ref LL_TIM_CHANNEL_CH4
1867 * @retval Returned value can be one of the following values:
1868 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
1869 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
1870 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
1871 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)1872 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
1873 {
1874 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1875 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1876 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
1877 }
1878
1879 /**
1880 * @brief Set the prescaler of input channel.
1881 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
1882 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
1883 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
1884 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
1885 * @param TIMx Timer instance
1886 * @param Channel This parameter can be one of the following values:
1887 * @arg @ref LL_TIM_CHANNEL_CH1
1888 * @arg @ref LL_TIM_CHANNEL_CH2
1889 * @arg @ref LL_TIM_CHANNEL_CH3
1890 * @arg @ref LL_TIM_CHANNEL_CH4
1891 * @param ICPrescaler This parameter can be one of the following values:
1892 * @arg @ref LL_TIM_ICPSC_DIV1
1893 * @arg @ref LL_TIM_ICPSC_DIV2
1894 * @arg @ref LL_TIM_ICPSC_DIV4
1895 * @arg @ref LL_TIM_ICPSC_DIV8
1896 * @retval None
1897 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)1898 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
1899 {
1900 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1901 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1902 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
1903 }
1904
1905 /**
1906 * @brief Get the current prescaler value acting on an input channel.
1907 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
1908 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
1909 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
1910 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
1911 * @param TIMx Timer instance
1912 * @param Channel This parameter can be one of the following values:
1913 * @arg @ref LL_TIM_CHANNEL_CH1
1914 * @arg @ref LL_TIM_CHANNEL_CH2
1915 * @arg @ref LL_TIM_CHANNEL_CH3
1916 * @arg @ref LL_TIM_CHANNEL_CH4
1917 * @retval Returned value can be one of the following values:
1918 * @arg @ref LL_TIM_ICPSC_DIV1
1919 * @arg @ref LL_TIM_ICPSC_DIV2
1920 * @arg @ref LL_TIM_ICPSC_DIV4
1921 * @arg @ref LL_TIM_ICPSC_DIV8
1922 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)1923 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
1924 {
1925 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1926 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1927 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
1928 }
1929
1930 /**
1931 * @brief Set the input filter duration.
1932 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
1933 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
1934 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
1935 * CCMR2 IC4F LL_TIM_IC_SetFilter
1936 * @param TIMx Timer instance
1937 * @param Channel This parameter can be one of the following values:
1938 * @arg @ref LL_TIM_CHANNEL_CH1
1939 * @arg @ref LL_TIM_CHANNEL_CH2
1940 * @arg @ref LL_TIM_CHANNEL_CH3
1941 * @arg @ref LL_TIM_CHANNEL_CH4
1942 * @param ICFilter This parameter can be one of the following values:
1943 * @arg @ref LL_TIM_IC_FILTER_FDIV1
1944 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
1945 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
1946 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
1947 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
1948 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
1949 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
1950 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
1951 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
1952 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
1953 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
1954 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
1955 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
1956 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
1957 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
1958 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
1959 * @retval None
1960 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)1961 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
1962 {
1963 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1964 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1965 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
1966 }
1967
1968 /**
1969 * @brief Get the input filter duration.
1970 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
1971 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
1972 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
1973 * CCMR2 IC4F LL_TIM_IC_GetFilter
1974 * @param TIMx Timer instance
1975 * @param Channel This parameter can be one of the following values:
1976 * @arg @ref LL_TIM_CHANNEL_CH1
1977 * @arg @ref LL_TIM_CHANNEL_CH2
1978 * @arg @ref LL_TIM_CHANNEL_CH3
1979 * @arg @ref LL_TIM_CHANNEL_CH4
1980 * @retval Returned value can be one of the following values:
1981 * @arg @ref LL_TIM_IC_FILTER_FDIV1
1982 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
1983 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
1984 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
1985 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
1986 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
1987 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
1988 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
1989 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
1990 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
1991 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
1992 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
1993 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
1994 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
1995 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
1996 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
1997 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)1998 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
1999 {
2000 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2001 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2002 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2003 }
2004
2005 /**
2006 * @brief Set the input channel polarity.
2007 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2008 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2009 * CCER CC2P LL_TIM_IC_SetPolarity\n
2010 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2011 * CCER CC3P LL_TIM_IC_SetPolarity\n
2012 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2013 * CCER CC4P LL_TIM_IC_SetPolarity\n
2014 * CCER CC4NP LL_TIM_IC_SetPolarity
2015 * @param TIMx Timer instance
2016 * @param Channel This parameter can be one of the following values:
2017 * @arg @ref LL_TIM_CHANNEL_CH1
2018 * @arg @ref LL_TIM_CHANNEL_CH2
2019 * @arg @ref LL_TIM_CHANNEL_CH3
2020 * @arg @ref LL_TIM_CHANNEL_CH4
2021 * @param ICPolarity This parameter can be one of the following values:
2022 * @arg @ref LL_TIM_IC_POLARITY_RISING
2023 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2024 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2025 * @retval None
2026 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2027 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2028 {
2029 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2030 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2031 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2032 }
2033
2034 /**
2035 * @brief Get the current input channel polarity.
2036 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2037 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2038 * CCER CC2P LL_TIM_IC_GetPolarity\n
2039 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2040 * CCER CC3P LL_TIM_IC_GetPolarity\n
2041 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2042 * CCER CC4P LL_TIM_IC_GetPolarity\n
2043 * CCER CC4NP LL_TIM_IC_GetPolarity
2044 * @param TIMx Timer instance
2045 * @param Channel This parameter can be one of the following values:
2046 * @arg @ref LL_TIM_CHANNEL_CH1
2047 * @arg @ref LL_TIM_CHANNEL_CH2
2048 * @arg @ref LL_TIM_CHANNEL_CH3
2049 * @arg @ref LL_TIM_CHANNEL_CH4
2050 * @retval Returned value can be one of the following values:
2051 * @arg @ref LL_TIM_IC_POLARITY_RISING
2052 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2053 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2054 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2055 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2056 {
2057 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2058 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2059 SHIFT_TAB_CCxP[iChannel]);
2060 }
2061
2062 /**
2063 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2064 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2065 * a timer instance provides an XOR input.
2066 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2067 * @param TIMx Timer instance
2068 * @retval None
2069 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2070 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2071 {
2072 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2073 }
2074
2075 /**
2076 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2077 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2078 * a timer instance provides an XOR input.
2079 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2080 * @param TIMx Timer instance
2081 * @retval None
2082 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2083 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2084 {
2085 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2086 }
2087
2088 /**
2089 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2090 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2091 * a timer instance provides an XOR input.
2092 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2093 * @param TIMx Timer instance
2094 * @retval State of bit (1 or 0).
2095 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)2096 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
2097 {
2098 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2099 }
2100
2101 /**
2102 * @brief Get captured value for input channel 1.
2103 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2104 * input channel 1 is supported by a timer instance.
2105 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2106 * @param TIMx Timer instance
2107 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2108 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)2109 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
2110 {
2111 return (uint32_t)(READ_REG(TIMx->CCR1));
2112 }
2113
2114 /**
2115 * @brief Get captured value for input channel 2.
2116 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2117 * input channel 2 is supported by a timer instance.
2118 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2119 * @param TIMx Timer instance
2120 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2121 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)2122 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
2123 {
2124 return (uint32_t)(READ_REG(TIMx->CCR2));
2125 }
2126
2127 /**
2128 * @brief Get captured value for input channel 3.
2129 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2130 * input channel 3 is supported by a timer instance.
2131 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2132 * @param TIMx Timer instance
2133 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2134 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)2135 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
2136 {
2137 return (uint32_t)(READ_REG(TIMx->CCR3));
2138 }
2139
2140 /**
2141 * @brief Get captured value for input channel 4.
2142 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2143 * input channel 4 is supported by a timer instance.
2144 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2145 * @param TIMx Timer instance
2146 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2147 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)2148 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
2149 {
2150 return (uint32_t)(READ_REG(TIMx->CCR4));
2151 }
2152
2153 /**
2154 * @}
2155 */
2156
2157 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2158 * @{
2159 */
2160 /**
2161 * @brief Enable external clock mode 2.
2162 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2163 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2164 * whether or not a timer instance supports external clock mode2.
2165 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2166 * @param TIMx Timer instance
2167 * @retval None
2168 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2169 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2170 {
2171 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2172 }
2173
2174 /**
2175 * @brief Disable external clock mode 2.
2176 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2177 * whether or not a timer instance supports external clock mode2.
2178 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2179 * @param TIMx Timer instance
2180 * @retval None
2181 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2182 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2183 {
2184 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2185 }
2186
2187 /**
2188 * @brief Indicate whether external clock mode 2 is enabled.
2189 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2190 * whether or not a timer instance supports external clock mode2.
2191 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2192 * @param TIMx Timer instance
2193 * @retval State of bit (1 or 0).
2194 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)2195 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
2196 {
2197 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2198 }
2199
2200 /**
2201 * @brief Set the clock source of the counter clock.
2202 * @note when selected clock source is external clock mode 1, the timer input
2203 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2204 * function. This timer input must be configured by calling
2205 * the @ref LL_TIM_IC_Config() function.
2206 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2207 * whether or not a timer instance supports external clock mode1.
2208 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2209 * whether or not a timer instance supports external clock mode2.
2210 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2211 * SMCR ECE LL_TIM_SetClockSource
2212 * @param TIMx Timer instance
2213 * @param ClockSource This parameter can be one of the following values:
2214 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2215 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2216 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2217 * @retval None
2218 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2219 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2220 {
2221 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2222 }
2223
2224 /**
2225 * @brief Set the encoder interface mode.
2226 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2227 * whether or not a timer instance supports the encoder mode.
2228 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2229 * @param TIMx Timer instance
2230 * @param EncoderMode This parameter can be one of the following values:
2231 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2232 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2233 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2234 * @retval None
2235 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2236 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2237 {
2238 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2239 }
2240
2241 /**
2242 * @}
2243 */
2244
2245 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2246 * @{
2247 */
2248 /**
2249 * @brief Set the trigger output (TRGO) used for timer synchronization .
2250 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2251 * whether or not a timer instance can operate as a master timer.
2252 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2253 * @param TIMx Timer instance
2254 * @param TimerSynchronization This parameter can be one of the following values:
2255 * @arg @ref LL_TIM_TRGO_RESET
2256 * @arg @ref LL_TIM_TRGO_ENABLE
2257 * @arg @ref LL_TIM_TRGO_UPDATE
2258 * @arg @ref LL_TIM_TRGO_CC1IF
2259 * @arg @ref LL_TIM_TRGO_OC1REF
2260 * @arg @ref LL_TIM_TRGO_OC2REF
2261 * @arg @ref LL_TIM_TRGO_OC3REF
2262 * @arg @ref LL_TIM_TRGO_OC4REF
2263 * @retval None
2264 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2265 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2266 {
2267 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2268 }
2269
2270 /**
2271 * @brief Set the synchronization mode of a slave timer.
2272 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2273 * a timer instance can operate as a slave timer.
2274 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2275 * @param TIMx Timer instance
2276 * @param SlaveMode This parameter can be one of the following values:
2277 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2278 * @arg @ref LL_TIM_SLAVEMODE_RESET
2279 * @arg @ref LL_TIM_SLAVEMODE_GATED
2280 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2281 * @retval None
2282 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2283 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2284 {
2285 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2286 }
2287
2288 /**
2289 * @brief Set the selects the trigger input to be used to synchronize the counter.
2290 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2291 * a timer instance can operate as a slave timer.
2292 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2293 * @param TIMx Timer instance
2294 * @param TriggerInput This parameter can be one of the following values:
2295 * @arg @ref LL_TIM_TS_ITR0
2296 * @arg @ref LL_TIM_TS_ITR1
2297 * @arg @ref LL_TIM_TS_ITR2
2298 * @arg @ref LL_TIM_TS_ITR3
2299 * @arg @ref LL_TIM_TS_TI1F_ED
2300 * @arg @ref LL_TIM_TS_TI1FP1
2301 * @arg @ref LL_TIM_TS_TI2FP2
2302 * @arg @ref LL_TIM_TS_ETRF
2303 * @retval None
2304 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2305 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2306 {
2307 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2308 }
2309
2310 /**
2311 * @brief Enable the Master/Slave mode.
2312 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2313 * a timer instance can operate as a slave timer.
2314 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2315 * @param TIMx Timer instance
2316 * @retval None
2317 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2318 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2319 {
2320 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2321 }
2322
2323 /**
2324 * @brief Disable the Master/Slave mode.
2325 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2326 * a timer instance can operate as a slave timer.
2327 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2328 * @param TIMx Timer instance
2329 * @retval None
2330 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2331 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2332 {
2333 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2334 }
2335
2336 /**
2337 * @brief Indicates whether the Master/Slave mode is enabled.
2338 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2339 * a timer instance can operate as a slave timer.
2340 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2341 * @param TIMx Timer instance
2342 * @retval State of bit (1 or 0).
2343 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)2344 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
2345 {
2346 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2347 }
2348
2349 /**
2350 * @brief Configure the external trigger (ETR) input.
2351 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2352 * a timer instance provides an external trigger input.
2353 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2354 * SMCR ETPS LL_TIM_ConfigETR\n
2355 * SMCR ETF LL_TIM_ConfigETR
2356 * @param TIMx Timer instance
2357 * @param ETRPolarity This parameter can be one of the following values:
2358 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2359 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2360 * @param ETRPrescaler This parameter can be one of the following values:
2361 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2362 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2363 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2364 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2365 * @param ETRFilter This parameter can be one of the following values:
2366 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2367 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2368 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2369 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2370 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2371 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2372 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2373 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2374 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2375 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2376 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2377 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2378 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2379 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2380 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2381 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2382 * @retval None
2383 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2384 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2385 uint32_t ETRFilter)
2386 {
2387 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2388 }
2389
2390 /**
2391 * @}
2392 */
2393
2394 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
2395 * @{
2396 */
2397 /**
2398 * @brief Configures the timer DMA burst feature.
2399 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
2400 * not a timer instance supports the DMA burst mode.
2401 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
2402 * DCR DBA LL_TIM_ConfigDMABurst
2403 * @param TIMx Timer instance
2404 * @param DMABurstBaseAddress This parameter can be one of the following values:
2405 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
2406 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
2407 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
2408 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
2409 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
2410 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
2411 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
2412 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
2413 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
2414 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
2415 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
2416 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
2417 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
2418 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
2419 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
2420 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
2421 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
2422 * @param DMABurstLength This parameter can be one of the following values:
2423 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
2424 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
2425 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
2426 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
2427 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
2428 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
2429 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
2430 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
2431 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
2432 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
2433 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
2434 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
2435 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
2436 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
2437 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
2438 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
2439 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
2440 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
2441 * @retval None
2442 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)2443 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
2444 {
2445 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
2446 }
2447
2448 /**
2449 * @}
2450 */
2451
2452 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
2453 * @{
2454 */
2455 /**
2456 * @brief Remap TIM inputs (input channel, internal/external triggers).
2457 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
2458 * a some timer inputs can be remapped.
2459 * @rmtoll TIM2_OR ETR_RMP LL_TIM_SetRemap\n
2460 * TIM2_OR TI4_RMP LL_TIM_SetRemap\n
2461 * TIM21_OR ETR_RMP LL_TIM_SetRemap\n
2462 * TIM21_OR TI1_RMP LL_TIM_SetRemap\n
2463 * TIM21_OR TI2_RMP LL_TIM_SetRemap\n
2464 * TIM22_OR ETR_RMP LL_TIM_SetRemap\n
2465 * TIM22_OR TI1_RMP LL_TIM_SetRemap\n
2466 * TIM3_OR ETR_RMP LL_TIM_SetRemap\n
2467 * TIM3_OR TI1_RMP LL_TIM_SetRemap\n
2468 * TIM3_OR TI2_RMP LL_TIM_SetRemap\n
2469 * TIM3_OR TI4_RMP LL_TIM_SetRemap
2470 * @param TIMx Timer instance
2471 * @param Remap Remap params depends on the TIMx. Description available only
2472 * in CHM version of the User Manual (not in .pdf).
2473 * Otherwise see Reference Manual description of OR registers.
2474 *
2475 * Below description summarizes "Timer Instance" and "Remap" param combinations:
2476 *
2477 * TIM2: any combination of ETR_RMP, TI4_RMP where
2478 *
2479 * . . ETR_RMP can be one of the following values
2480 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
2481 * @arg @ref LL_TIM_TIM2_ETR_RMP_HSI (*)
2482 * @arg @ref LL_TIM_TIM2_ETR_RMP_HSI48 (*)
2483 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
2484 * @arg @ref LL_TIM_TIM2_ETR_RMP_COMP2
2485 * @arg @ref LL_TIM_TIM2_ETR_RMP_COMP1
2486 *
2487 * . . TI4_RMP can be one of the following values
2488 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
2489 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
2490 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
2491 *
2492 * TIM3: any combination of the following values (**)
2493 *
2494 * . . ETR_RMP can be one of the following values (**)
2495 * @arg @ref LL_TIM_TIM3_ETR_RMP_GPIO
2496 * @arg @ref LL_TIM_TIM3_ETR_RMP_HSI48DIV6
2497 *
2498 * . . TI_RMP_TI1 can be one of the following values (**)
2499 * @arg @ref LL_TIM_TIM3_TI_RMP_TI1_USB_SOF
2500 * @arg @ref LL_TIM_TIM3_TI_RMP_TI1_GPIO
2501 *
2502 * . . TI_RMP_TI2 can be one of the following values (**)
2503 * @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF
2504 * @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4
2505 *
2506 * . . TI_RMP_TI4 can be one of the following values (**)
2507 * @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF
2508 * @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2
2509 *
2510 * TIM21: any combination of ETR_RMP, TI1_RMP, TI2_RMP where
2511 *
2512 * . . ETR_RMP can be one of the following values
2513 * @arg @ref LL_TIM_TIM21_ETR_RMP_GPIO
2514 * @arg @ref LL_TIM_TIM21_ETR_RMP_COMP2
2515 * @arg @ref LL_TIM_TIM21_ETR_RMP_COMP1
2516 * @arg @ref LL_TIM_TIM21_ETR_RMP_LSE
2517 *
2518 * . . TI1_RMP can be one of the following values
2519 * @arg @ref LL_TIM_TIM21_TI1_RMP_GPIO
2520 * @arg @ref LL_TIM_TIM21_TI1_RMP_RTC_WK
2521 * @arg @ref LL_TIM_TIM21_TI1_RMP_HSE_RTC
2522 * @arg @ref LL_TIM_TIM21_TI1_RMP_MSI
2523 * @arg @ref LL_TIM_TIM21_TI1_RMP_LSE
2524 * @arg @ref LL_TIM_TIM21_TI1_RMP_LSI
2525 * @arg @ref LL_TIM_TIM21_TI1_RMP_COMP1
2526 * @arg @ref LL_TIM_TIM21_TI1_RMP_MCO
2527 *
2528 * . . TI2_RMP can be one of the following values
2529 * @arg @ref LL_TIM_TIM21_TI2_RMP_GPIO
2530 * @arg @ref LL_TIM_TIM21_TI2_RMP_COMP2
2531 *
2532 * TIM22: any combination of ETR_RMP, TI1_RMP where (**)
2533 *
2534 * . . ETR_RMP can be one of the following values (**)
2535 * @arg @ref LL_TIM_TIM22_ETR_RMP_GPIO
2536 * @arg @ref LL_TIM_TIM22_ETR_RMP_COMP2
2537 * @arg @ref LL_TIM_TIM22_ETR_RMP_COMP1
2538 * @arg @ref LL_TIM_TIM22_ETR_RMP_LSE
2539 *
2540 * . . TI1_RMP can be one of the following values (**)
2541 * @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO1
2542 * @arg @ref LL_TIM_TIM22_TI1_RMP_COMP2
2543 * @arg @ref LL_TIM_TIM22_TI1_RMP_COMP1
2544 * @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO2
2545 *
2546 * (*) Value not defined in all devices. \n
2547 * (*) Register not available in all devices.
2548 * @retval None
2549 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)2550 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
2551 {
2552 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
2553 }
2554
2555 /**
2556 * @}
2557 */
2558
2559 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
2560 * @{
2561 */
2562 /**
2563 * @brief Clear the update interrupt flag (UIF).
2564 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
2565 * @param TIMx Timer instance
2566 * @retval None
2567 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)2568 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
2569 {
2570 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
2571 }
2572
2573 /**
2574 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
2575 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
2576 * @param TIMx Timer instance
2577 * @retval State of bit (1 or 0).
2578 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)2579 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
2580 {
2581 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
2582 }
2583
2584 /**
2585 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
2586 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
2587 * @param TIMx Timer instance
2588 * @retval None
2589 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)2590 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
2591 {
2592 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
2593 }
2594
2595 /**
2596 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
2597 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
2598 * @param TIMx Timer instance
2599 * @retval State of bit (1 or 0).
2600 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)2601 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
2602 {
2603 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
2604 }
2605
2606 /**
2607 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
2608 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
2609 * @param TIMx Timer instance
2610 * @retval None
2611 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)2612 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
2613 {
2614 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
2615 }
2616
2617 /**
2618 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
2619 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
2620 * @param TIMx Timer instance
2621 * @retval State of bit (1 or 0).
2622 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)2623 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
2624 {
2625 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
2626 }
2627
2628 /**
2629 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
2630 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
2631 * @param TIMx Timer instance
2632 * @retval None
2633 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)2634 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
2635 {
2636 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
2637 }
2638
2639 /**
2640 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
2641 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
2642 * @param TIMx Timer instance
2643 * @retval State of bit (1 or 0).
2644 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)2645 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
2646 {
2647 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
2648 }
2649
2650 /**
2651 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
2652 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
2653 * @param TIMx Timer instance
2654 * @retval None
2655 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)2656 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
2657 {
2658 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
2659 }
2660
2661 /**
2662 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
2663 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
2664 * @param TIMx Timer instance
2665 * @retval State of bit (1 or 0).
2666 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)2667 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
2668 {
2669 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
2670 }
2671
2672 /**
2673 * @brief Clear the trigger interrupt flag (TIF).
2674 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
2675 * @param TIMx Timer instance
2676 * @retval None
2677 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)2678 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
2679 {
2680 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
2681 }
2682
2683 /**
2684 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
2685 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
2686 * @param TIMx Timer instance
2687 * @retval State of bit (1 or 0).
2688 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)2689 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
2690 {
2691 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
2692 }
2693
2694 /**
2695 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
2696 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
2697 * @param TIMx Timer instance
2698 * @retval None
2699 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)2700 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
2701 {
2702 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
2703 }
2704
2705 /**
2706 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
2707 * (Capture/Compare 1 interrupt is pending).
2708 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
2709 * @param TIMx Timer instance
2710 * @retval State of bit (1 or 0).
2711 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)2712 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
2713 {
2714 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
2715 }
2716
2717 /**
2718 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
2719 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
2720 * @param TIMx Timer instance
2721 * @retval None
2722 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)2723 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
2724 {
2725 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
2726 }
2727
2728 /**
2729 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
2730 * (Capture/Compare 2 over-capture interrupt is pending).
2731 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
2732 * @param TIMx Timer instance
2733 * @retval State of bit (1 or 0).
2734 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)2735 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
2736 {
2737 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
2738 }
2739
2740 /**
2741 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
2742 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
2743 * @param TIMx Timer instance
2744 * @retval None
2745 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)2746 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
2747 {
2748 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
2749 }
2750
2751 /**
2752 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
2753 * (Capture/Compare 3 over-capture interrupt is pending).
2754 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
2755 * @param TIMx Timer instance
2756 * @retval State of bit (1 or 0).
2757 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)2758 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
2759 {
2760 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
2761 }
2762
2763 /**
2764 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
2765 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
2766 * @param TIMx Timer instance
2767 * @retval None
2768 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)2769 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
2770 {
2771 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
2772 }
2773
2774 /**
2775 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
2776 * (Capture/Compare 4 over-capture interrupt is pending).
2777 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
2778 * @param TIMx Timer instance
2779 * @retval State of bit (1 or 0).
2780 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)2781 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
2782 {
2783 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
2784 }
2785
2786 /**
2787 * @}
2788 */
2789
2790 /** @defgroup TIM_LL_EF_IT_Management IT-Management
2791 * @{
2792 */
2793 /**
2794 * @brief Enable update interrupt (UIE).
2795 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
2796 * @param TIMx Timer instance
2797 * @retval None
2798 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)2799 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
2800 {
2801 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
2802 }
2803
2804 /**
2805 * @brief Disable update interrupt (UIE).
2806 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
2807 * @param TIMx Timer instance
2808 * @retval None
2809 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)2810 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
2811 {
2812 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
2813 }
2814
2815 /**
2816 * @brief Indicates whether the update interrupt (UIE) is enabled.
2817 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
2818 * @param TIMx Timer instance
2819 * @retval State of bit (1 or 0).
2820 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)2821 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
2822 {
2823 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
2824 }
2825
2826 /**
2827 * @brief Enable capture/compare 1 interrupt (CC1IE).
2828 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
2829 * @param TIMx Timer instance
2830 * @retval None
2831 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)2832 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
2833 {
2834 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
2835 }
2836
2837 /**
2838 * @brief Disable capture/compare 1 interrupt (CC1IE).
2839 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
2840 * @param TIMx Timer instance
2841 * @retval None
2842 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)2843 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
2844 {
2845 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
2846 }
2847
2848 /**
2849 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
2850 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
2851 * @param TIMx Timer instance
2852 * @retval State of bit (1 or 0).
2853 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)2854 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
2855 {
2856 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
2857 }
2858
2859 /**
2860 * @brief Enable capture/compare 2 interrupt (CC2IE).
2861 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
2862 * @param TIMx Timer instance
2863 * @retval None
2864 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)2865 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
2866 {
2867 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
2868 }
2869
2870 /**
2871 * @brief Disable capture/compare 2 interrupt (CC2IE).
2872 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
2873 * @param TIMx Timer instance
2874 * @retval None
2875 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)2876 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
2877 {
2878 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
2879 }
2880
2881 /**
2882 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
2883 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
2884 * @param TIMx Timer instance
2885 * @retval State of bit (1 or 0).
2886 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)2887 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
2888 {
2889 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
2890 }
2891
2892 /**
2893 * @brief Enable capture/compare 3 interrupt (CC3IE).
2894 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
2895 * @param TIMx Timer instance
2896 * @retval None
2897 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)2898 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
2899 {
2900 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
2901 }
2902
2903 /**
2904 * @brief Disable capture/compare 3 interrupt (CC3IE).
2905 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
2906 * @param TIMx Timer instance
2907 * @retval None
2908 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)2909 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
2910 {
2911 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
2912 }
2913
2914 /**
2915 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
2916 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
2917 * @param TIMx Timer instance
2918 * @retval State of bit (1 or 0).
2919 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)2920 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
2921 {
2922 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
2923 }
2924
2925 /**
2926 * @brief Enable capture/compare 4 interrupt (CC4IE).
2927 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
2928 * @param TIMx Timer instance
2929 * @retval None
2930 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)2931 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
2932 {
2933 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
2934 }
2935
2936 /**
2937 * @brief Disable capture/compare 4 interrupt (CC4IE).
2938 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
2939 * @param TIMx Timer instance
2940 * @retval None
2941 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)2942 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
2943 {
2944 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
2945 }
2946
2947 /**
2948 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
2949 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
2950 * @param TIMx Timer instance
2951 * @retval State of bit (1 or 0).
2952 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)2953 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
2954 {
2955 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
2956 }
2957
2958 /**
2959 * @brief Enable trigger interrupt (TIE).
2960 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
2961 * @param TIMx Timer instance
2962 * @retval None
2963 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)2964 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
2965 {
2966 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
2967 }
2968
2969 /**
2970 * @brief Disable trigger interrupt (TIE).
2971 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
2972 * @param TIMx Timer instance
2973 * @retval None
2974 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)2975 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
2976 {
2977 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
2978 }
2979
2980 /**
2981 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
2982 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
2983 * @param TIMx Timer instance
2984 * @retval State of bit (1 or 0).
2985 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)2986 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
2987 {
2988 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
2989 }
2990
2991 /**
2992 * @}
2993 */
2994
2995 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2996 * @{
2997 */
2998 /**
2999 * @brief Enable update DMA request (UDE).
3000 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3001 * @param TIMx Timer instance
3002 * @retval None
3003 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3004 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3005 {
3006 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3007 }
3008
3009 /**
3010 * @brief Disable update DMA request (UDE).
3011 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3012 * @param TIMx Timer instance
3013 * @retval None
3014 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3015 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3016 {
3017 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3018 }
3019
3020 /**
3021 * @brief Indicates whether the update DMA request (UDE) is enabled.
3022 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3023 * @param TIMx Timer instance
3024 * @retval State of bit (1 or 0).
3025 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)3026 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
3027 {
3028 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3029 }
3030
3031 /**
3032 * @brief Enable capture/compare 1 DMA request (CC1DE).
3033 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3034 * @param TIMx Timer instance
3035 * @retval None
3036 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3037 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3038 {
3039 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3040 }
3041
3042 /**
3043 * @brief Disable capture/compare 1 DMA request (CC1DE).
3044 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3045 * @param TIMx Timer instance
3046 * @retval None
3047 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3048 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3049 {
3050 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3051 }
3052
3053 /**
3054 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3055 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3056 * @param TIMx Timer instance
3057 * @retval State of bit (1 or 0).
3058 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)3059 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
3060 {
3061 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3062 }
3063
3064 /**
3065 * @brief Enable capture/compare 2 DMA request (CC2DE).
3066 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3067 * @param TIMx Timer instance
3068 * @retval None
3069 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3070 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3071 {
3072 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3073 }
3074
3075 /**
3076 * @brief Disable capture/compare 2 DMA request (CC2DE).
3077 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3078 * @param TIMx Timer instance
3079 * @retval None
3080 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3081 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3082 {
3083 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3084 }
3085
3086 /**
3087 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3088 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3089 * @param TIMx Timer instance
3090 * @retval State of bit (1 or 0).
3091 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)3092 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
3093 {
3094 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3095 }
3096
3097 /**
3098 * @brief Enable capture/compare 3 DMA request (CC3DE).
3099 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3100 * @param TIMx Timer instance
3101 * @retval None
3102 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3103 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3104 {
3105 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3106 }
3107
3108 /**
3109 * @brief Disable capture/compare 3 DMA request (CC3DE).
3110 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3111 * @param TIMx Timer instance
3112 * @retval None
3113 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3114 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3115 {
3116 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3117 }
3118
3119 /**
3120 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3121 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3122 * @param TIMx Timer instance
3123 * @retval State of bit (1 or 0).
3124 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)3125 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
3126 {
3127 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3128 }
3129
3130 /**
3131 * @brief Enable capture/compare 4 DMA request (CC4DE).
3132 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3133 * @param TIMx Timer instance
3134 * @retval None
3135 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3136 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3137 {
3138 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3139 }
3140
3141 /**
3142 * @brief Disable capture/compare 4 DMA request (CC4DE).
3143 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3144 * @param TIMx Timer instance
3145 * @retval None
3146 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3147 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3148 {
3149 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3150 }
3151
3152 /**
3153 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3154 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3155 * @param TIMx Timer instance
3156 * @retval State of bit (1 or 0).
3157 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)3158 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
3159 {
3160 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3161 }
3162
3163 /**
3164 * @brief Enable trigger interrupt (TDE).
3165 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3166 * @param TIMx Timer instance
3167 * @retval None
3168 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3169 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3170 {
3171 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3172 }
3173
3174 /**
3175 * @brief Disable trigger interrupt (TDE).
3176 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3177 * @param TIMx Timer instance
3178 * @retval None
3179 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3180 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3181 {
3182 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3183 }
3184
3185 /**
3186 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3187 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3188 * @param TIMx Timer instance
3189 * @retval State of bit (1 or 0).
3190 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)3191 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
3192 {
3193 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3194 }
3195
3196 /**
3197 * @}
3198 */
3199
3200 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3201 * @{
3202 */
3203 /**
3204 * @brief Generate an update event.
3205 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3206 * @param TIMx Timer instance
3207 * @retval None
3208 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3209 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3210 {
3211 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3212 }
3213
3214 /**
3215 * @brief Generate Capture/Compare 1 event.
3216 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3217 * @param TIMx Timer instance
3218 * @retval None
3219 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3220 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3221 {
3222 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3223 }
3224
3225 /**
3226 * @brief Generate Capture/Compare 2 event.
3227 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3228 * @param TIMx Timer instance
3229 * @retval None
3230 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3231 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3232 {
3233 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3234 }
3235
3236 /**
3237 * @brief Generate Capture/Compare 3 event.
3238 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3239 * @param TIMx Timer instance
3240 * @retval None
3241 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)3242 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
3243 {
3244 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
3245 }
3246
3247 /**
3248 * @brief Generate Capture/Compare 4 event.
3249 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
3250 * @param TIMx Timer instance
3251 * @retval None
3252 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)3253 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
3254 {
3255 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
3256 }
3257
3258 /**
3259 * @brief Generate trigger event.
3260 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
3261 * @param TIMx Timer instance
3262 * @retval None
3263 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)3264 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
3265 {
3266 SET_BIT(TIMx->EGR, TIM_EGR_TG);
3267 }
3268
3269 /**
3270 * @}
3271 */
3272
3273 #if defined(USE_FULL_LL_DRIVER)
3274 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
3275 * @{
3276 */
3277
3278 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
3279 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
3280 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
3281 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3282 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3283 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
3284 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
3285 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3286 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3287 /**
3288 * @}
3289 */
3290 #endif /* USE_FULL_LL_DRIVER */
3291
3292 /**
3293 * @}
3294 */
3295
3296 /**
3297 * @}
3298 */
3299
3300 #endif /* TIM1 || TIM3 || TIM21 || TIM22 || TIM6 || TIM7 */
3301
3302 /**
3303 * @}
3304 */
3305
3306 #ifdef __cplusplus
3307 }
3308 #endif
3309
3310 #endif /* __STM32L0xx_LL_TIM_H */
3311
