1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g4xx_ll_tim.h"
22 #include "stm32g4xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \
71 || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
72 || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
73
74 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
75 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
76
77 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
78 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
79
80 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
81 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
82
83 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
84 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
85 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
86
87 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
89 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
90 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
91
92 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
108
109 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
111 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
112
113 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
114 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
115 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
116 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
117 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
118 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
119 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
120 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
121 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
122
123 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
124 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
125
126 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
127 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
128
129 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
130 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
131
132 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
133 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
134 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
135 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
136
137 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
138 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
139
140 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
141 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
142
143 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
152 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
153 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
154 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
159
160 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
161 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
162
163 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
164 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
165
166 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
167 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
168
169 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
185
186 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
187 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
188
189 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
190 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
191 /**
192 * @}
193 */
194
195
196 /* Private function prototypes -----------------------------------------------*/
197 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
198 * @{
199 */
200 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
201 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
202 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
203 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
204 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
205 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
206 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
207 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
208 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
209 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
210 /**
211 * @}
212 */
213
214 /* Exported functions --------------------------------------------------------*/
215 /** @addtogroup TIM_LL_Exported_Functions
216 * @{
217 */
218
219 /** @addtogroup TIM_LL_EF_Init
220 * @{
221 */
222
223 /**
224 * @brief Set TIMx registers to their reset values.
225 * @param TIMx Timer instance
226 * @retval An ErrorStatus enumeration value:
227 * - SUCCESS: TIMx registers are de-initialized
228 * - ERROR: invalid TIMx instance
229 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)230 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
231 {
232 ErrorStatus result = SUCCESS;
233
234 /* Check the parameters */
235 assert_param(IS_TIM_INSTANCE(TIMx));
236
237 if (TIMx == TIM1)
238 {
239 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
240 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
241 }
242 else if (TIMx == TIM2)
243 {
244 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
245 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
246 }
247 else if (TIMx == TIM3)
248 {
249 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
250 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
251 }
252 else if (TIMx == TIM4)
253 {
254 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
255 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
256 }
257 #if defined(TIM5)
258 else if (TIMx == TIM5)
259 {
260 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
261 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
262 }
263 #endif /* TIM5 */
264 else if (TIMx == TIM6)
265 {
266 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
267 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
268 }
269 else if (TIMx == TIM7)
270 {
271 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
272 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
273 }
274 else if (TIMx == TIM8)
275 {
276 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
277 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
278 }
279 else if (TIMx == TIM15)
280 {
281 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
282 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
283 }
284 else if (TIMx == TIM16)
285 {
286 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
287 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
288 }
289 else if (TIMx == TIM17)
290 {
291 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
292 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
293 }
294 #if defined(TIM20)
295 else if (TIMx == TIM20)
296 {
297 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
298 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
299 }
300 #endif /* TIM20 */
301 else
302 {
303 result = ERROR;
304 }
305
306 return result;
307 }
308
309 /**
310 * @brief Set the fields of the time base unit configuration data structure
311 * to their default values.
312 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
313 * @retval None
314 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)315 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
316 {
317 /* Set the default configuration */
318 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
319 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
320 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
321 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
322 TIM_InitStruct->RepetitionCounter = 0x00000000U;
323 }
324
325 /**
326 * @brief Configure the TIMx time base unit.
327 * @param TIMx Timer Instance
328 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
329 * (TIMx time base unit configuration data structure)
330 * @retval An ErrorStatus enumeration value:
331 * - SUCCESS: TIMx registers are de-initialized
332 * - ERROR: not applicable
333 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)334 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
335 {
336 uint32_t tmpcr1;
337
338 /* Check the parameters */
339 assert_param(IS_TIM_INSTANCE(TIMx));
340 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
341 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
342
343 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
344
345 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
346 {
347 /* Select the Counter Mode */
348 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
349 }
350
351 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
352 {
353 /* Set the clock division */
354 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
355 }
356
357 /* Write to TIMx CR1 */
358 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
359
360 /* Set the Autoreload value */
361 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
362
363 /* Set the Prescaler value */
364 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
365
366 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
367 {
368 /* Set the Repetition Counter value */
369 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
370 }
371
372 /* Generate an update event to reload the Prescaler
373 and the repetition counter value (if applicable) immediately */
374 LL_TIM_GenerateEvent_UPDATE(TIMx);
375
376 return SUCCESS;
377 }
378
379 /**
380 * @brief Set the fields of the TIMx output channel configuration data
381 * structure to their default values.
382 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
383 * (the output channel configuration data structure)
384 * @retval None
385 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)386 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
387 {
388 /* Set the default configuration */
389 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
390 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
391 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
392 TIM_OC_InitStruct->CompareValue = 0x00000000U;
393 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
394 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
395 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
396 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
397 }
398
399 /**
400 * @brief Configure the TIMx output channel.
401 * @param TIMx Timer Instance
402 * @param Channel This parameter can be one of the following values:
403 * @arg @ref LL_TIM_CHANNEL_CH1
404 * @arg @ref LL_TIM_CHANNEL_CH2
405 * @arg @ref LL_TIM_CHANNEL_CH3
406 * @arg @ref LL_TIM_CHANNEL_CH4
407 * @arg @ref LL_TIM_CHANNEL_CH5
408 * @arg @ref LL_TIM_CHANNEL_CH6
409 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
410 * data structure)
411 * @retval An ErrorStatus enumeration value:
412 * - SUCCESS: TIMx output channel is initialized
413 * - ERROR: TIMx output channel is not initialized
414 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)415 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
416 {
417 ErrorStatus result = ERROR;
418
419 switch (Channel)
420 {
421 case LL_TIM_CHANNEL_CH1:
422 result = OC1Config(TIMx, TIM_OC_InitStruct);
423 break;
424 case LL_TIM_CHANNEL_CH2:
425 result = OC2Config(TIMx, TIM_OC_InitStruct);
426 break;
427 case LL_TIM_CHANNEL_CH3:
428 result = OC3Config(TIMx, TIM_OC_InitStruct);
429 break;
430 case LL_TIM_CHANNEL_CH4:
431 result = OC4Config(TIMx, TIM_OC_InitStruct);
432 break;
433 case LL_TIM_CHANNEL_CH5:
434 result = OC5Config(TIMx, TIM_OC_InitStruct);
435 break;
436 case LL_TIM_CHANNEL_CH6:
437 result = OC6Config(TIMx, TIM_OC_InitStruct);
438 break;
439 default:
440 break;
441 }
442
443 return result;
444 }
445
446 /**
447 * @brief Set the fields of the TIMx input channel configuration data
448 * structure to their default values.
449 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
450 * data structure)
451 * @retval None
452 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)453 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
454 {
455 /* Set the default configuration */
456 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
457 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
458 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
459 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
460 }
461
462 /**
463 * @brief Configure the TIMx input channel.
464 * @param TIMx Timer Instance
465 * @param Channel This parameter can be one of the following values:
466 * @arg @ref LL_TIM_CHANNEL_CH1
467 * @arg @ref LL_TIM_CHANNEL_CH2
468 * @arg @ref LL_TIM_CHANNEL_CH3
469 * @arg @ref LL_TIM_CHANNEL_CH4
470 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
471 * structure)
472 * @retval An ErrorStatus enumeration value:
473 * - SUCCESS: TIMx output channel is initialized
474 * - ERROR: TIMx output channel is not initialized
475 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)476 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
477 {
478 ErrorStatus result = ERROR;
479
480 switch (Channel)
481 {
482 case LL_TIM_CHANNEL_CH1:
483 result = IC1Config(TIMx, TIM_IC_InitStruct);
484 break;
485 case LL_TIM_CHANNEL_CH2:
486 result = IC2Config(TIMx, TIM_IC_InitStruct);
487 break;
488 case LL_TIM_CHANNEL_CH3:
489 result = IC3Config(TIMx, TIM_IC_InitStruct);
490 break;
491 case LL_TIM_CHANNEL_CH4:
492 result = IC4Config(TIMx, TIM_IC_InitStruct);
493 break;
494 default:
495 break;
496 }
497
498 return result;
499 }
500
501 /**
502 * @brief Fills each TIM_EncoderInitStruct field with its default value
503 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
504 * configuration data structure)
505 * @retval None
506 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)507 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
508 {
509 /* Set the default configuration */
510 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
511 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
512 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
513 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
514 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
515 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
516 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
517 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
518 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
519 }
520
521 /**
522 * @brief Configure the encoder interface of the timer instance.
523 * @param TIMx Timer Instance
524 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
525 * configuration data structure)
526 * @retval An ErrorStatus enumeration value:
527 * - SUCCESS: TIMx registers are de-initialized
528 * - ERROR: not applicable
529 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)530 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
531 {
532 uint32_t tmpccmr1;
533 uint32_t tmpccer;
534
535 /* Check the parameters */
536 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
537 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
538 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
539 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
540 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
541 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
542 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
543 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
544 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
545 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
546
547 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
548 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
549
550 /* Get the TIMx CCMR1 register value */
551 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
552
553 /* Get the TIMx CCER register value */
554 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
555
556 /* Configure TI1 */
557 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
558 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
559 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
560 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
561
562 /* Configure TI2 */
563 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
564 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
565 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
566 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
567
568 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
569 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
570 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
571 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
572 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
573
574 /* Set encoder mode */
575 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
576
577 /* Write to TIMx CCMR1 */
578 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
579
580 /* Write to TIMx CCER */
581 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
582
583 return SUCCESS;
584 }
585
586 /**
587 * @brief Set the fields of the TIMx Hall sensor interface configuration data
588 * structure to their default values.
589 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
590 * configuration data structure)
591 * @retval None
592 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)593 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
594 {
595 /* Set the default configuration */
596 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
597 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
598 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
599 TIM_HallSensorInitStruct->CommutationDelay = 0U;
600 }
601
602 /**
603 * @brief Configure the Hall sensor interface of the timer instance.
604 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
605 * to the TI1 input channel
606 * @note TIMx slave mode controller is configured in reset mode.
607 Selected internal trigger is TI1F_ED.
608 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
609 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
610 * between 2 changes on the inputs. It gives information about motor speed.
611 * @note Channel 2 is configured in output PWM 2 mode.
612 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
613 * @note OC2REF is selected as trigger output on TRGO.
614 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
615 * when TIMx operates in Hall sensor interface mode.
616 * @param TIMx Timer Instance
617 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
618 * interface configuration data structure)
619 * @retval An ErrorStatus enumeration value:
620 * - SUCCESS: TIMx registers are de-initialized
621 * - ERROR: not applicable
622 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)623 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
624 {
625 uint32_t tmpcr2;
626 uint32_t tmpccmr1;
627 uint32_t tmpccer;
628 uint32_t tmpsmcr;
629
630 /* Check the parameters */
631 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
632 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
633 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
634 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
635
636 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
637 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
638
639 /* Get the TIMx CR2 register value */
640 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
641
642 /* Get the TIMx CCMR1 register value */
643 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
644
645 /* Get the TIMx CCER register value */
646 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
647
648 /* Get the TIMx SMCR register value */
649 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
650
651 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
652 tmpcr2 |= TIM_CR2_TI1S;
653
654 /* OC2REF signal is used as trigger output (TRGO) */
655 tmpcr2 |= LL_TIM_TRGO_OC2REF;
656
657 /* Configure the slave mode controller */
658 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
659 tmpsmcr |= LL_TIM_TS_TI1F_ED;
660 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
661
662 /* Configure input channel 1 */
663 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
664 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
665 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
666 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
667
668 /* Configure input channel 2 */
669 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
670 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
671
672 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
673 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
674 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
675 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
676
677 /* Write to TIMx CR2 */
678 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
679
680 /* Write to TIMx SMCR */
681 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
682
683 /* Write to TIMx CCMR1 */
684 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
685
686 /* Write to TIMx CCER */
687 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
688
689 /* Write to TIMx CCR2 */
690 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
691
692 return SUCCESS;
693 }
694
695 /**
696 * @brief Set the fields of the Break and Dead Time configuration data structure
697 * to their default values.
698 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
699 * data structure)
700 * @retval None
701 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)702 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
703 {
704 /* Set the default configuration */
705 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
706 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
707 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
708 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
709 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
710 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
711 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
712 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
713 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
714 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
715 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
716 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
717 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
718 }
719
720 /**
721 * @brief Configure the Break and Dead Time feature of the timer instance.
722 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
723 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
724 * can be necessary to configure all of them during the first write access to
725 * the TIMx_BDTR register.
726 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
727 * a timer instance provides a break input.
728 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
729 * a timer instance provides a second break input.
730 * @param TIMx Timer Instance
731 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
732 * data structure)
733 * @retval An ErrorStatus enumeration value:
734 * - SUCCESS: Break and Dead Time is initialized
735 * - ERROR: not applicable
736 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)737 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
738 {
739 uint32_t tmpbdtr = 0;
740
741 /* Check the parameters */
742 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
743 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
744 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
745 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
746 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
747 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
748 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
749
750 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
751 the OSSI State, the dead time value and the Automatic Output Enable Bit */
752
753 /* Set the BDTR bits */
754 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
755 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
756 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
757 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
758 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
759 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
760 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
761 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
762 if (IS_TIM_ADVANCED_INSTANCE(TIMx))
763 {
764 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
765 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
766 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
767 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
768 }
769
770 if (IS_TIM_BKIN2_INSTANCE(TIMx))
771 {
772 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
773 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
774 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
775 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
776
777 /* Set the BREAK2 input related BDTR bit-fields */
778 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
779 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
780 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
781 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
782 }
783
784 /* Set TIMx_BDTR */
785 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
786
787 return SUCCESS;
788 }
789 /**
790 * @}
791 */
792
793 /**
794 * @}
795 */
796
797 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
798 * @brief Private functions
799 * @{
800 */
801 /**
802 * @brief Configure the TIMx output channel 1.
803 * @param TIMx Timer Instance
804 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
805 * @retval An ErrorStatus enumeration value:
806 * - SUCCESS: TIMx registers are de-initialized
807 * - ERROR: not applicable
808 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)809 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
810 {
811 uint32_t tmpccmr1;
812 uint32_t tmpccer;
813 uint32_t tmpcr2;
814
815 /* Check the parameters */
816 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
817 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
818 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
819 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
820 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
821 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
822
823 /* Disable the Channel 1: Reset the CC1E Bit */
824 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
825
826 /* Get the TIMx CCER register value */
827 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
828
829 /* Get the TIMx CR2 register value */
830 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
831
832 /* Get the TIMx CCMR1 register value */
833 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
834
835 /* Reset Capture/Compare selection Bits */
836 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
837
838 /* Set the Output Compare Mode */
839 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
840
841 /* Set the Output Compare Polarity */
842 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
843
844 /* Set the Output State */
845 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
846
847 if (IS_TIM_BREAK_INSTANCE(TIMx))
848 {
849 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
850 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
851
852 /* Set the complementary output Polarity */
853 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
854
855 /* Set the complementary output State */
856 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
857
858 /* Set the Output Idle state */
859 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
860
861 /* Set the complementary output Idle state */
862 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
863 }
864
865 /* Write to TIMx CR2 */
866 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
867
868 /* Write to TIMx CCMR1 */
869 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
870
871 /* Set the Capture Compare Register value */
872 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
873
874 /* Write to TIMx CCER */
875 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
876
877 return SUCCESS;
878 }
879
880 /**
881 * @brief Configure the TIMx output channel 2.
882 * @param TIMx Timer Instance
883 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
884 * @retval An ErrorStatus enumeration value:
885 * - SUCCESS: TIMx registers are de-initialized
886 * - ERROR: not applicable
887 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)888 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
889 {
890 uint32_t tmpccmr1;
891 uint32_t tmpccer;
892 uint32_t tmpcr2;
893
894 /* Check the parameters */
895 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
896 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
897 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
898 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
899 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
900 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
901
902 /* Disable the Channel 2: Reset the CC2E Bit */
903 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
904
905 /* Get the TIMx CCER register value */
906 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
907
908 /* Get the TIMx CR2 register value */
909 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
910
911 /* Get the TIMx CCMR1 register value */
912 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
913
914 /* Reset Capture/Compare selection Bits */
915 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
916
917 /* Select the Output Compare Mode */
918 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
919
920 /* Set the Output Compare Polarity */
921 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
922
923 /* Set the Output State */
924 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
925
926 if (IS_TIM_BREAK_INSTANCE(TIMx))
927 {
928 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
929 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
930
931 /* Set the complementary output Polarity */
932 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
933
934 /* Set the complementary output State */
935 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
936
937 /* Set the Output Idle state */
938 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
939
940 /* Set the complementary output Idle state */
941 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
942 }
943
944 /* Write to TIMx CR2 */
945 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
946
947 /* Write to TIMx CCMR1 */
948 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
949
950 /* Set the Capture Compare Register value */
951 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
952
953 /* Write to TIMx CCER */
954 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
955
956 return SUCCESS;
957 }
958
959 /**
960 * @brief Configure the TIMx output channel 3.
961 * @param TIMx Timer Instance
962 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
963 * @retval An ErrorStatus enumeration value:
964 * - SUCCESS: TIMx registers are de-initialized
965 * - ERROR: not applicable
966 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)967 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
968 {
969 uint32_t tmpccmr2;
970 uint32_t tmpccer;
971 uint32_t tmpcr2;
972
973 /* Check the parameters */
974 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
975 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
976 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
977 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
978 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
979 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
980
981 /* Disable the Channel 3: Reset the CC3E Bit */
982 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
983
984 /* Get the TIMx CCER register value */
985 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
986
987 /* Get the TIMx CR2 register value */
988 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
989
990 /* Get the TIMx CCMR2 register value */
991 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
992
993 /* Reset Capture/Compare selection Bits */
994 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
995
996 /* Select the Output Compare Mode */
997 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
998
999 /* Set the Output Compare Polarity */
1000 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1001
1002 /* Set the Output State */
1003 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1004
1005 if (IS_TIM_BREAK_INSTANCE(TIMx))
1006 {
1007 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1008 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1009
1010 /* Set the complementary output Polarity */
1011 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1012
1013 /* Set the complementary output State */
1014 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1015
1016 /* Set the Output Idle state */
1017 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1018
1019 /* Set the complementary output Idle state */
1020 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1021 }
1022
1023 /* Write to TIMx CR2 */
1024 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1025
1026 /* Write to TIMx CCMR2 */
1027 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1028
1029 /* Set the Capture Compare Register value */
1030 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1031
1032 /* Write to TIMx CCER */
1033 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1034
1035 return SUCCESS;
1036 }
1037
1038 /**
1039 * @brief Configure the TIMx output channel 4.
1040 * @param TIMx Timer Instance
1041 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1042 * @retval An ErrorStatus enumeration value:
1043 * - SUCCESS: TIMx registers are de-initialized
1044 * - ERROR: not applicable
1045 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1046 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1047 {
1048 uint32_t tmpccmr2;
1049 uint32_t tmpccer;
1050 uint32_t tmpcr2;
1051
1052 /* Check the parameters */
1053 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1054 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1055 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1056 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1057 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1058 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1059
1060 /* Disable the Channel 4: Reset the CC4E Bit */
1061 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1062
1063 /* Get the TIMx CCER register value */
1064 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1065
1066 /* Get the TIMx CR2 register value */
1067 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1068
1069 /* Get the TIMx CCMR2 register value */
1070 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1071
1072 /* Reset Capture/Compare selection Bits */
1073 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1074
1075 /* Select the Output Compare Mode */
1076 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1077
1078 /* Set the Output Compare Polarity */
1079 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1080
1081 /* Set the Output State */
1082 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1083
1084 if (IS_TIM_BREAK_INSTANCE(TIMx))
1085 {
1086 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1087 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1088
1089 /* Set the complementary output Polarity */
1090 MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
1091
1092 /* Set the complementary output State */
1093 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
1094
1095 /* Set the Output Idle state */
1096 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1097
1098 /* Set the complementary output Idle state */
1099 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
1100 }
1101
1102 /* Write to TIMx CR2 */
1103 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1104
1105 /* Write to TIMx CCMR2 */
1106 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1107
1108 /* Set the Capture Compare Register value */
1109 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1110
1111 /* Write to TIMx CCER */
1112 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1113
1114 return SUCCESS;
1115 }
1116
1117 /**
1118 * @brief Configure the TIMx output channel 5.
1119 * @param TIMx Timer Instance
1120 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1121 * @retval An ErrorStatus enumeration value:
1122 * - SUCCESS: TIMx registers are de-initialized
1123 * - ERROR: not applicable
1124 */
OC5Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1125 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1126 {
1127 uint32_t tmpccmr3;
1128 uint32_t tmpccer;
1129
1130 /* Check the parameters */
1131 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1132 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1133 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1134 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1135 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1136 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1137
1138 /* Disable the Channel 5: Reset the CC5E Bit */
1139 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1140
1141 /* Get the TIMx CCER register value */
1142 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1143
1144 /* Get the TIMx CCMR3 register value */
1145 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1146
1147 /* Select the Output Compare Mode */
1148 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1149
1150 /* Set the Output Compare Polarity */
1151 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1152
1153 /* Set the Output State */
1154 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1155
1156 if (IS_TIM_BREAK_INSTANCE(TIMx))
1157 {
1158 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1159 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1160
1161 /* Set the Output Idle state */
1162 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1163
1164 }
1165
1166 /* Write to TIMx CCMR3 */
1167 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1168
1169 /* Set the Capture Compare Register value */
1170 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1171
1172 /* Write to TIMx CCER */
1173 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1174
1175 return SUCCESS;
1176 }
1177
1178 /**
1179 * @brief Configure the TIMx output channel 6.
1180 * @param TIMx Timer Instance
1181 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1182 * @retval An ErrorStatus enumeration value:
1183 * - SUCCESS: TIMx registers are de-initialized
1184 * - ERROR: not applicable
1185 */
OC6Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1186 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1187 {
1188 uint32_t tmpccmr3;
1189 uint32_t tmpccer;
1190
1191 /* Check the parameters */
1192 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1193 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1194 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1195 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1196 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1197 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1198
1199 /* Disable the Channel 5: Reset the CC6E Bit */
1200 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1201
1202 /* Get the TIMx CCER register value */
1203 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1204
1205 /* Get the TIMx CCMR3 register value */
1206 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1207
1208 /* Select the Output Compare Mode */
1209 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1210
1211 /* Set the Output Compare Polarity */
1212 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1213
1214 /* Set the Output State */
1215 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1216
1217 if (IS_TIM_BREAK_INSTANCE(TIMx))
1218 {
1219 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1220 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1221
1222 /* Set the Output Idle state */
1223 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1224 }
1225
1226 /* Write to TIMx CCMR3 */
1227 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1228
1229 /* Set the Capture Compare Register value */
1230 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1231
1232 /* Write to TIMx CCER */
1233 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1234
1235 return SUCCESS;
1236 }
1237
1238 /**
1239 * @brief Configure the TIMx input channel 1.
1240 * @param TIMx Timer Instance
1241 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1242 * @retval An ErrorStatus enumeration value:
1243 * - SUCCESS: TIMx registers are de-initialized
1244 * - ERROR: not applicable
1245 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1246 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1247 {
1248 /* Check the parameters */
1249 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1250 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1251 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1252 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1253 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1254
1255 /* Disable the Channel 1: Reset the CC1E Bit */
1256 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1257
1258 /* Select the Input and set the filter and the prescaler value */
1259 MODIFY_REG(TIMx->CCMR1,
1260 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1261 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1262
1263 /* Select the Polarity and set the CC1E Bit */
1264 MODIFY_REG(TIMx->CCER,
1265 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1266 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1267
1268 return SUCCESS;
1269 }
1270
1271 /**
1272 * @brief Configure the TIMx input channel 2.
1273 * @param TIMx Timer Instance
1274 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1275 * @retval An ErrorStatus enumeration value:
1276 * - SUCCESS: TIMx registers are de-initialized
1277 * - ERROR: not applicable
1278 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1279 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1280 {
1281 /* Check the parameters */
1282 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1283 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1284 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1285 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1286 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1287
1288 /* Disable the Channel 2: Reset the CC2E Bit */
1289 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1290
1291 /* Select the Input and set the filter and the prescaler value */
1292 MODIFY_REG(TIMx->CCMR1,
1293 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1294 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1295
1296 /* Select the Polarity and set the CC2E Bit */
1297 MODIFY_REG(TIMx->CCER,
1298 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1299 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1300
1301 return SUCCESS;
1302 }
1303
1304 /**
1305 * @brief Configure the TIMx input channel 3.
1306 * @param TIMx Timer Instance
1307 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1308 * @retval An ErrorStatus enumeration value:
1309 * - SUCCESS: TIMx registers are de-initialized
1310 * - ERROR: not applicable
1311 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1312 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1313 {
1314 /* Check the parameters */
1315 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1316 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1317 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1318 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1319 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1320
1321 /* Disable the Channel 3: Reset the CC3E Bit */
1322 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1323
1324 /* Select the Input and set the filter and the prescaler value */
1325 MODIFY_REG(TIMx->CCMR2,
1326 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1327 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1328
1329 /* Select the Polarity and set the CC3E Bit */
1330 MODIFY_REG(TIMx->CCER,
1331 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1332 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1333
1334 return SUCCESS;
1335 }
1336
1337 /**
1338 * @brief Configure the TIMx input channel 4.
1339 * @param TIMx Timer Instance
1340 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1341 * @retval An ErrorStatus enumeration value:
1342 * - SUCCESS: TIMx registers are de-initialized
1343 * - ERROR: not applicable
1344 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1345 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1346 {
1347 /* Check the parameters */
1348 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1349 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1350 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1351 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1352 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1353
1354 /* Disable the Channel 4: Reset the CC4E Bit */
1355 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1356
1357 /* Select the Input and set the filter and the prescaler value */
1358 MODIFY_REG(TIMx->CCMR2,
1359 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1360 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1361
1362 /* Select the Polarity and set the CC2E Bit */
1363 MODIFY_REG(TIMx->CCER,
1364 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1365 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1366
1367 return SUCCESS;
1368 }
1369
1370
1371 /**
1372 * @}
1373 */
1374
1375 /**
1376 * @}
1377 */
1378
1379 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
1380
1381 /**
1382 * @}
1383 */
1384
1385 #endif /* USE_FULL_LL_DRIVER */
1386
1387
