1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32u5xx_ll_tim.h"
22 #include "stm32u5xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM4) \
38 || defined (TIM5) \
39 || defined (TIM6) \
40 || defined (TIM7) \
41 || defined (TIM8) \
42 || defined (TIM15) \
43 || defined (TIM16) \
44 || defined (TIM17) \
45 || defined (TIM20)
46
47 /** @addtogroup TIM_LL
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53 /* Private constants ---------------------------------------------------------*/
54 /* Private macros ------------------------------------------------------------*/
55 /** @addtogroup TIM_LL_Private_Macros
56 * @{
57 */
58 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
59 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
60 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
61 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
62 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
63
64 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
65 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
66 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
67
68 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
70 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
71 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
72 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
73 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
74 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
75 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
76 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
77 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
78 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
79 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
80 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
81 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \
82 || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
83 || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
84
85 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
86 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
87
88 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
89 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
90
91 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
92 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
93
94 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
95 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
96 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
97
98 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
99 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
100 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
101 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
102
103 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
117 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
118 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
119
120 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
121 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
122 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
123
124 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
125 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
126 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
127 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
128 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
129 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
130 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
131 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
132 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
133
134 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
135 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
136
137 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
138 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
139
140 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
141 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
142
143 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
144 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
145 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
146 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
147
148 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
149 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
150
151 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
152 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
153
154 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
159 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
160 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
161 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
162 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
163 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
164 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
165 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
168 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
169 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
170
171 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
172 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
173
174 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
175 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
176
177 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
178 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
179
180 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
185 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
186 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
187 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
188 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
189 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
190 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
191 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
192 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
193 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
194 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
195 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
196
197 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
198 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
199
200 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
201 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
202 /**
203 * @}
204 */
205
206
207 /* Private function prototypes -----------------------------------------------*/
208 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
209 * @{
210 */
211 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
212 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
213 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
214 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
215 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
216 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
217 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
218 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
219 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
220 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
221 /**
222 * @}
223 */
224
225 /* Exported functions --------------------------------------------------------*/
226 /** @addtogroup TIM_LL_Exported_Functions
227 * @{
228 */
229
230 /** @addtogroup TIM_LL_EF_Init
231 * @{
232 */
233
234 /**
235 * @brief Set TIMx registers to their reset values.
236 * @param TIMx Timer instance
237 * @retval An ErrorStatus enumeration value:
238 * - SUCCESS: TIMx registers are de-initialized
239 * - ERROR: invalid TIMx instance
240 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)241 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
242 {
243 ErrorStatus result = SUCCESS;
244
245 /* Check the parameters */
246 assert_param(IS_TIM_INSTANCE(TIMx));
247
248 if (TIMx == TIM1)
249 {
250 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
251 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
252 }
253 else if (TIMx == TIM2)
254 {
255 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
256 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
257 }
258 else if (TIMx == TIM3)
259 {
260 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
261 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
262 }
263 else if (TIMx == TIM4)
264 {
265 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
266 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
267 }
268 else if (TIMx == TIM5)
269 {
270 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
271 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
272 }
273 else if (TIMx == TIM6)
274 {
275 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
276 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
277 }
278 else if (TIMx == TIM7)
279 {
280 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
281 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
282 }
283 else if (TIMx == TIM8)
284 {
285 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
286 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
287 }
288 else if (TIMx == TIM15)
289 {
290 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
291 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
292 }
293 else if (TIMx == TIM16)
294 {
295 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
296 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
297 }
298 else if (TIMx == TIM17)
299 {
300 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
301 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
302 }
303 else
304 {
305 result = ERROR;
306 }
307
308 return result;
309 }
310
311 /**
312 * @brief Set the fields of the time base unit configuration data structure
313 * to their default values.
314 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
315 * @retval None
316 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)317 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
318 {
319 /* Set the default configuration */
320 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
321 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
322 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
323 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
324 TIM_InitStruct->RepetitionCounter = 0x00000000U;
325 }
326
327 /**
328 * @brief Configure the TIMx time base unit.
329 * @param TIMx Timer Instance
330 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
331 * (TIMx time base unit configuration data structure)
332 * @retval An ErrorStatus enumeration value:
333 * - SUCCESS: TIMx registers are de-initialized
334 * - ERROR: not applicable
335 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)336 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
337 {
338 uint32_t tmpcr1;
339
340 /* Check the parameters */
341 assert_param(IS_TIM_INSTANCE(TIMx));
342 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
343 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
344
345 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
346
347 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
348 {
349 /* Select the Counter Mode */
350 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
351 }
352
353 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
354 {
355 /* Set the clock division */
356 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
357 }
358
359 /* Write to TIMx CR1 */
360 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
361
362 /* Set the Autoreload value */
363 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
364
365 /* Set the Prescaler value */
366 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
367
368 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
369 {
370 /* Set the Repetition Counter value */
371 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
372 }
373
374 /* Generate an update event to reload the Prescaler
375 and the repetition counter value (if applicable) immediately */
376 LL_TIM_GenerateEvent_UPDATE(TIMx);
377
378 return SUCCESS;
379 }
380
381 /**
382 * @brief Set the fields of the TIMx output channel configuration data
383 * structure to their default values.
384 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
385 * (the output channel configuration data structure)
386 * @retval None
387 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)388 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
389 {
390 /* Set the default configuration */
391 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
392 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
393 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
394 TIM_OC_InitStruct->CompareValue = 0x00000000U;
395 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
396 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
397 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
398 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
399 }
400
401 /**
402 * @brief Configure the TIMx output channel.
403 * @param TIMx Timer Instance
404 * @param Channel This parameter can be one of the following values:
405 * @arg @ref LL_TIM_CHANNEL_CH1
406 * @arg @ref LL_TIM_CHANNEL_CH2
407 * @arg @ref LL_TIM_CHANNEL_CH3
408 * @arg @ref LL_TIM_CHANNEL_CH4
409 * @arg @ref LL_TIM_CHANNEL_CH5
410 * @arg @ref LL_TIM_CHANNEL_CH6
411 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
412 * data structure)
413 * @retval An ErrorStatus enumeration value:
414 * - SUCCESS: TIMx output channel is initialized
415 * - ERROR: TIMx output channel is not initialized
416 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)417 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
418 {
419 ErrorStatus result = ERROR;
420
421 switch (Channel)
422 {
423 case LL_TIM_CHANNEL_CH1:
424 result = OC1Config(TIMx, TIM_OC_InitStruct);
425 break;
426 case LL_TIM_CHANNEL_CH2:
427 result = OC2Config(TIMx, TIM_OC_InitStruct);
428 break;
429 case LL_TIM_CHANNEL_CH3:
430 result = OC3Config(TIMx, TIM_OC_InitStruct);
431 break;
432 case LL_TIM_CHANNEL_CH4:
433 result = OC4Config(TIMx, TIM_OC_InitStruct);
434 break;
435 case LL_TIM_CHANNEL_CH5:
436 result = OC5Config(TIMx, TIM_OC_InitStruct);
437 break;
438 case LL_TIM_CHANNEL_CH6:
439 result = OC6Config(TIMx, TIM_OC_InitStruct);
440 break;
441 default:
442 break;
443 }
444
445 return result;
446 }
447
448 /**
449 * @brief Set the fields of the TIMx input channel configuration data
450 * structure to their default values.
451 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
452 * data structure)
453 * @retval None
454 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)455 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
456 {
457 /* Set the default configuration */
458 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
459 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
460 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
461 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
462 }
463
464 /**
465 * @brief Configure the TIMx input channel.
466 * @param TIMx Timer Instance
467 * @param Channel This parameter can be one of the following values:
468 * @arg @ref LL_TIM_CHANNEL_CH1
469 * @arg @ref LL_TIM_CHANNEL_CH2
470 * @arg @ref LL_TIM_CHANNEL_CH3
471 * @arg @ref LL_TIM_CHANNEL_CH4
472 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
473 * structure)
474 * @retval An ErrorStatus enumeration value:
475 * - SUCCESS: TIMx output channel is initialized
476 * - ERROR: TIMx output channel is not initialized
477 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)478 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
479 {
480 ErrorStatus result = ERROR;
481
482 switch (Channel)
483 {
484 case LL_TIM_CHANNEL_CH1:
485 result = IC1Config(TIMx, TIM_IC_InitStruct);
486 break;
487 case LL_TIM_CHANNEL_CH2:
488 result = IC2Config(TIMx, TIM_IC_InitStruct);
489 break;
490 case LL_TIM_CHANNEL_CH3:
491 result = IC3Config(TIMx, TIM_IC_InitStruct);
492 break;
493 case LL_TIM_CHANNEL_CH4:
494 result = IC4Config(TIMx, TIM_IC_InitStruct);
495 break;
496 default:
497 break;
498 }
499
500 return result;
501 }
502
503 /**
504 * @brief Fills each TIM_EncoderInitStruct field with its default value
505 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
506 * configuration data structure)
507 * @retval None
508 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)509 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
510 {
511 /* Set the default configuration */
512 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
513 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
514 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
515 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
516 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
517 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
518 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
519 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
520 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
521 }
522
523 /**
524 * @brief Configure the encoder interface of the timer instance.
525 * @param TIMx Timer Instance
526 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
527 * configuration data structure)
528 * @retval An ErrorStatus enumeration value:
529 * - SUCCESS: TIMx registers are de-initialized
530 * - ERROR: not applicable
531 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)532 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
533 {
534 uint32_t tmpccmr1;
535 uint32_t tmpccer;
536
537 /* Check the parameters */
538 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
539 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
540 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
541 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
542 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
543 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
544 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
545 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
546 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
547 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
548
549 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
550 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
551
552 /* Get the TIMx CCMR1 register value */
553 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
554
555 /* Get the TIMx CCER register value */
556 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
557
558 /* Configure TI1 */
559 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
560 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
561 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
562 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
563
564 /* Configure TI2 */
565 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
566 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
567 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
568 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
569
570 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
571 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
572 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
573 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
574 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
575
576 /* Set encoder mode */
577 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
578
579 /* Write to TIMx CCMR1 */
580 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
581
582 /* Write to TIMx CCER */
583 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
584
585 return SUCCESS;
586 }
587
588 /**
589 * @brief Set the fields of the TIMx Hall sensor interface configuration data
590 * structure to their default values.
591 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
592 * configuration data structure)
593 * @retval None
594 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)595 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
596 {
597 /* Set the default configuration */
598 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
599 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
600 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
601 TIM_HallSensorInitStruct->CommutationDelay = 0U;
602 }
603
604 /**
605 * @brief Configure the Hall sensor interface of the timer instance.
606 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
607 * to the TI1 input channel
608 * @note TIMx slave mode controller is configured in reset mode.
609 Selected internal trigger is TI1F_ED.
610 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
611 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
612 * between 2 changes on the inputs. It gives information about motor speed.
613 * @note Channel 2 is configured in output PWM 2 mode.
614 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
615 * @note OC2REF is selected as trigger output on TRGO.
616 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
617 * when TIMx operates in Hall sensor interface mode.
618 * @param TIMx Timer Instance
619 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
620 * interface configuration data structure)
621 * @retval An ErrorStatus enumeration value:
622 * - SUCCESS: TIMx registers are de-initialized
623 * - ERROR: not applicable
624 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)625 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
626 {
627 uint32_t tmpcr2;
628 uint32_t tmpccmr1;
629 uint32_t tmpccer;
630 uint32_t tmpsmcr;
631
632 /* Check the parameters */
633 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
634 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
635 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
636 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
637
638 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
639 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
640
641 /* Get the TIMx CR2 register value */
642 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
643
644 /* Get the TIMx CCMR1 register value */
645 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
646
647 /* Get the TIMx CCER register value */
648 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
649
650 /* Get the TIMx SMCR register value */
651 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
652
653 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
654 tmpcr2 |= TIM_CR2_TI1S;
655
656 /* OC2REF signal is used as trigger output (TRGO) */
657 tmpcr2 |= LL_TIM_TRGO_OC2REF;
658
659 /* Configure the slave mode controller */
660 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
661 tmpsmcr |= LL_TIM_TS_TI1F_ED;
662 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
663
664 /* Configure input channel 1 */
665 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
666 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
667 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
668 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
669
670 /* Configure input channel 2 */
671 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
672 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
673
674 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
675 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
676 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
677 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
678
679 /* Write to TIMx CR2 */
680 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
681
682 /* Write to TIMx SMCR */
683 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
684
685 /* Write to TIMx CCMR1 */
686 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
687
688 /* Write to TIMx CCER */
689 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
690
691 /* Write to TIMx CCR2 */
692 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
693
694 return SUCCESS;
695 }
696
697 /**
698 * @brief Set the fields of the Break and Dead Time configuration data structure
699 * to their default values.
700 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
701 * data structure)
702 * @retval None
703 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)704 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
705 {
706 /* Set the default configuration */
707 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
708 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
709 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
710 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
711 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
712 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
713 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
714 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
715 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
716 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
717 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
718 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
719 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
720 }
721
722 /**
723 * @brief Configure the Break and Dead Time feature of the timer instance.
724 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
725 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
726 * can be necessary to configure all of them during the first write access to
727 * the TIMx_BDTR register.
728 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
729 * a timer instance provides a break input.
730 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
731 * a timer instance provides a second break input.
732 * @param TIMx Timer Instance
733 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
734 * data structure)
735 * @retval An ErrorStatus enumeration value:
736 * - SUCCESS: Break and Dead Time is initialized
737 * - ERROR: not applicable
738 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)739 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
740 {
741 uint32_t tmpbdtr = 0;
742
743 /* Check the parameters */
744 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
745 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
746 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
747 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
748 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
749 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
750 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
751
752 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
753 the OSSI State, the dead time value and the Automatic Output Enable Bit */
754
755 /* Set the BDTR bits */
756 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
757 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
758 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
759 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
760 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
761 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
762 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
763 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
764 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
765 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
766 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
767
768 if (IS_TIM_BKIN2_INSTANCE(TIMx))
769 {
770 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
771 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
772 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
773 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
774
775 /* Set the BREAK2 input related BDTR bit-fields */
776 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
777 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
778 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
779 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
780 }
781
782 /* Set TIMx_BDTR */
783 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
784
785 return SUCCESS;
786 }
787 /**
788 * @}
789 */
790
791 /**
792 * @}
793 */
794
795 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
796 * @brief Private functions
797 * @{
798 */
799 /**
800 * @brief Configure the TIMx output channel 1.
801 * @param TIMx Timer Instance
802 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
803 * @retval An ErrorStatus enumeration value:
804 * - SUCCESS: TIMx registers are de-initialized
805 * - ERROR: not applicable
806 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)807 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
808 {
809 uint32_t tmpccmr1;
810 uint32_t tmpccer;
811 uint32_t tmpcr2;
812
813 /* Check the parameters */
814 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
815 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
816 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
817 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
818 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
819 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
820
821 /* Disable the Channel 1: Reset the CC1E Bit */
822 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
823
824 /* Get the TIMx CCER register value */
825 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
826
827 /* Get the TIMx CR2 register value */
828 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
829
830 /* Get the TIMx CCMR1 register value */
831 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
832
833 /* Reset Capture/Compare selection Bits */
834 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
835
836 /* Set the Output Compare Mode */
837 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
838
839 /* Set the Output Compare Polarity */
840 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
841
842 /* Set the Output State */
843 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
844
845 if (IS_TIM_BREAK_INSTANCE(TIMx))
846 {
847 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
848 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
849
850 /* Set the complementary output Polarity */
851 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
852
853 /* Set the complementary output State */
854 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
855
856 /* Set the Output Idle state */
857 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
858
859 /* Set the complementary output Idle state */
860 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
861 }
862
863 /* Write to TIMx CR2 */
864 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
865
866 /* Write to TIMx CCMR1 */
867 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
868
869 /* Set the Capture Compare Register value */
870 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
871
872 /* Write to TIMx CCER */
873 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
874
875 return SUCCESS;
876 }
877
878 /**
879 * @brief Configure the TIMx output channel 2.
880 * @param TIMx Timer Instance
881 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
882 * @retval An ErrorStatus enumeration value:
883 * - SUCCESS: TIMx registers are de-initialized
884 * - ERROR: not applicable
885 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)886 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
887 {
888 uint32_t tmpccmr1;
889 uint32_t tmpccer;
890 uint32_t tmpcr2;
891
892 /* Check the parameters */
893 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
894 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
895 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
896 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
897 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
898 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
899
900 /* Disable the Channel 2: Reset the CC2E Bit */
901 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
902
903 /* Get the TIMx CCER register value */
904 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
905
906 /* Get the TIMx CR2 register value */
907 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
908
909 /* Get the TIMx CCMR1 register value */
910 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
911
912 /* Reset Capture/Compare selection Bits */
913 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
914
915 /* Select the Output Compare Mode */
916 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
917
918 /* Set the Output Compare Polarity */
919 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
920
921 /* Set the Output State */
922 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
923
924 if (IS_TIM_BREAK_INSTANCE(TIMx))
925 {
926 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
927 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
928
929 /* Set the complementary output Polarity */
930 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
931
932 /* Set the complementary output State */
933 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
934
935 /* Set the Output Idle state */
936 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
937
938 /* Set the complementary output Idle state */
939 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
940 }
941
942 /* Write to TIMx CR2 */
943 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
944
945 /* Write to TIMx CCMR1 */
946 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
947
948 /* Set the Capture Compare Register value */
949 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
950
951 /* Write to TIMx CCER */
952 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
953
954 return SUCCESS;
955 }
956
957 /**
958 * @brief Configure the TIMx output channel 3.
959 * @param TIMx Timer Instance
960 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
961 * @retval An ErrorStatus enumeration value:
962 * - SUCCESS: TIMx registers are de-initialized
963 * - ERROR: not applicable
964 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)965 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
966 {
967 uint32_t tmpccmr2;
968 uint32_t tmpccer;
969 uint32_t tmpcr2;
970
971 /* Check the parameters */
972 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
973 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
974 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
975 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
976 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
977 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
978
979 /* Disable the Channel 3: Reset the CC3E Bit */
980 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
981
982 /* Get the TIMx CCER register value */
983 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
984
985 /* Get the TIMx CR2 register value */
986 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
987
988 /* Get the TIMx CCMR2 register value */
989 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
990
991 /* Reset Capture/Compare selection Bits */
992 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
993
994 /* Select the Output Compare Mode */
995 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
996
997 /* Set the Output Compare Polarity */
998 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
999
1000 /* Set the Output State */
1001 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1002
1003 if (IS_TIM_BREAK_INSTANCE(TIMx))
1004 {
1005 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1006 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1007
1008 /* Set the complementary output Polarity */
1009 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1010
1011 /* Set the complementary output State */
1012 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1013
1014 /* Set the Output Idle state */
1015 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1016
1017 /* Set the complementary output Idle state */
1018 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1019 }
1020
1021 /* Write to TIMx CR2 */
1022 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1023
1024 /* Write to TIMx CCMR2 */
1025 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1026
1027 /* Set the Capture Compare Register value */
1028 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1029
1030 /* Write to TIMx CCER */
1031 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1032
1033 return SUCCESS;
1034 }
1035
1036 /**
1037 * @brief Configure the TIMx output channel 4.
1038 * @param TIMx Timer Instance
1039 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1040 * @retval An ErrorStatus enumeration value:
1041 * - SUCCESS: TIMx registers are de-initialized
1042 * - ERROR: not applicable
1043 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1044 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1045 {
1046 uint32_t tmpccmr2;
1047 uint32_t tmpccer;
1048 uint32_t tmpcr2;
1049
1050 /* Check the parameters */
1051 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1052 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1053 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1054 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1055 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1056 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1057
1058 /* Disable the Channel 4: Reset the CC4E Bit */
1059 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1060
1061 /* Get the TIMx CCER register value */
1062 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1063
1064 /* Get the TIMx CR2 register value */
1065 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1066
1067 /* Get the TIMx CCMR2 register value */
1068 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1069
1070 /* Reset Capture/Compare selection Bits */
1071 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1072
1073 /* Select the Output Compare Mode */
1074 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1075
1076 /* Set the Output Compare Polarity */
1077 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1078
1079 /* Set the Output State */
1080 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1081
1082 if (IS_TIM_BREAK_INSTANCE(TIMx))
1083 {
1084 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1085 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1086
1087 /* Set the complementary output Polarity */
1088 MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
1089
1090 /* Set the complementary output State */
1091 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
1092
1093 /* Set the Output Idle state */
1094 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1095
1096 /* Set the complementary output Idle state */
1097 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
1098 }
1099
1100 /* Write to TIMx CR2 */
1101 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1102
1103 /* Write to TIMx CCMR2 */
1104 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1105
1106 /* Set the Capture Compare Register value */
1107 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1108
1109 /* Write to TIMx CCER */
1110 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1111
1112 return SUCCESS;
1113 }
1114
1115 /**
1116 * @brief Configure the TIMx output channel 5.
1117 * @param TIMx Timer Instance
1118 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1119 * @retval An ErrorStatus enumeration value:
1120 * - SUCCESS: TIMx registers are de-initialized
1121 * - ERROR: not applicable
1122 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1123 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1124 {
1125 uint32_t tmpccmr3;
1126 uint32_t tmpccer;
1127
1128 /* Check the parameters */
1129 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1130 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1131 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1132 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1133 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1134 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1135
1136 /* Disable the Channel 5: Reset the CC5E Bit */
1137 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1138
1139 /* Get the TIMx CCER register value */
1140 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1141
1142 /* Get the TIMx CCMR3 register value */
1143 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1144
1145 /* Select the Output Compare Mode */
1146 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1147
1148 /* Set the Output Compare Polarity */
1149 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1150
1151 /* Set the Output State */
1152 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1153
1154 if (IS_TIM_BREAK_INSTANCE(TIMx))
1155 {
1156 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1157 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1158
1159 /* Set the Output Idle state */
1160 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1161
1162 }
1163
1164 /* Write to TIMx CCMR3 */
1165 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1166
1167 /* Set the Capture Compare Register value */
1168 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1169
1170 /* Write to TIMx CCER */
1171 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1172
1173 return SUCCESS;
1174 }
1175
1176 /**
1177 * @brief Configure the TIMx output channel 6.
1178 * @param TIMx Timer Instance
1179 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1180 * @retval An ErrorStatus enumeration value:
1181 * - SUCCESS: TIMx registers are de-initialized
1182 * - ERROR: not applicable
1183 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1184 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1185 {
1186 uint32_t tmpccmr3;
1187 uint32_t tmpccer;
1188
1189 /* Check the parameters */
1190 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1191 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1192 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1193 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1194 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1195 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1196
1197 /* Disable the Channel 5: Reset the CC6E Bit */
1198 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1199
1200 /* Get the TIMx CCER register value */
1201 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1202
1203 /* Get the TIMx CCMR3 register value */
1204 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1205
1206 /* Select the Output Compare Mode */
1207 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1208
1209 /* Set the Output Compare Polarity */
1210 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1211
1212 /* Set the Output State */
1213 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1214
1215 if (IS_TIM_BREAK_INSTANCE(TIMx))
1216 {
1217 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1218 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1219
1220 /* Set the Output Idle state */
1221 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1222 }
1223
1224 /* Write to TIMx CCMR3 */
1225 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1226
1227 /* Set the Capture Compare Register value */
1228 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1229
1230 /* Write to TIMx CCER */
1231 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1232
1233 return SUCCESS;
1234 }
1235
1236 /**
1237 * @brief Configure the TIMx input channel 1.
1238 * @param TIMx Timer Instance
1239 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1240 * @retval An ErrorStatus enumeration value:
1241 * - SUCCESS: TIMx registers are de-initialized
1242 * - ERROR: not applicable
1243 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1244 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1245 {
1246 /* Check the parameters */
1247 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1248 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1249 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1250 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1251 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1252
1253 /* Disable the Channel 1: Reset the CC1E Bit */
1254 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1255
1256 /* Select the Input and set the filter and the prescaler value */
1257 MODIFY_REG(TIMx->CCMR1,
1258 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1259 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1260
1261 /* Select the Polarity and set the CC1E Bit */
1262 MODIFY_REG(TIMx->CCER,
1263 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1264 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1265
1266 return SUCCESS;
1267 }
1268
1269 /**
1270 * @brief Configure the TIMx input channel 2.
1271 * @param TIMx Timer Instance
1272 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1273 * @retval An ErrorStatus enumeration value:
1274 * - SUCCESS: TIMx registers are de-initialized
1275 * - ERROR: not applicable
1276 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1277 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1278 {
1279 /* Check the parameters */
1280 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1281 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1282 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1283 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1284 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1285
1286 /* Disable the Channel 2: Reset the CC2E Bit */
1287 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1288
1289 /* Select the Input and set the filter and the prescaler value */
1290 MODIFY_REG(TIMx->CCMR1,
1291 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1292 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1293
1294 /* Select the Polarity and set the CC2E Bit */
1295 MODIFY_REG(TIMx->CCER,
1296 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1297 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1298
1299 return SUCCESS;
1300 }
1301
1302 /**
1303 * @brief Configure the TIMx input channel 3.
1304 * @param TIMx Timer Instance
1305 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1306 * @retval An ErrorStatus enumeration value:
1307 * - SUCCESS: TIMx registers are de-initialized
1308 * - ERROR: not applicable
1309 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1310 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1311 {
1312 /* Check the parameters */
1313 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1314 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1315 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1316 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1317 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1318
1319 /* Disable the Channel 3: Reset the CC3E Bit */
1320 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1321
1322 /* Select the Input and set the filter and the prescaler value */
1323 MODIFY_REG(TIMx->CCMR2,
1324 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1325 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1326
1327 /* Select the Polarity and set the CC3E Bit */
1328 MODIFY_REG(TIMx->CCER,
1329 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1330 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1331
1332 return SUCCESS;
1333 }
1334
1335 /**
1336 * @brief Configure the TIMx input channel 4.
1337 * @param TIMx Timer Instance
1338 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1339 * @retval An ErrorStatus enumeration value:
1340 * - SUCCESS: TIMx registers are de-initialized
1341 * - ERROR: not applicable
1342 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1343 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1344 {
1345 /* Check the parameters */
1346 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1347 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1348 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1349 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1350 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1351
1352 /* Disable the Channel 4: Reset the CC4E Bit */
1353 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1354
1355 /* Select the Input and set the filter and the prescaler value */
1356 MODIFY_REG(TIMx->CCMR2,
1357 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1358 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1359
1360 /* Select the Polarity and set the CC2E Bit */
1361 MODIFY_REG(TIMx->CCER,
1362 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1363 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1364
1365 return SUCCESS;
1366 }
1367
1368
1369 /**
1370 * @}
1371 */
1372
1373 /**
1374 * @}
1375 */
1376
1377 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
1378
1379 /**
1380 * @}
1381 */
1382
1383 #endif /* USE_FULL_LL_DRIVER */
1384
1385
