1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32c0xx_ll_tim.h"
22 #include "stm32c0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM16) || defined (TIM17)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
153 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
154
155 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
156 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
157
158 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
159 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
160
161 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
177
178 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
179 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
180
181 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
182 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
183 /**
184 * @}
185 */
186
187
188 /* Private function prototypes -----------------------------------------------*/
189 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
190 * @{
191 */
192 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
193 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
194 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
195 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
199 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
200 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
201 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
202 /**
203 * @}
204 */
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @addtogroup TIM_LL_Exported_Functions
208 * @{
209 */
210
211 /** @addtogroup TIM_LL_EF_Init
212 * @{
213 */
214
215 /**
216 * @brief Set TIMx registers to their reset values.
217 * @param TIMx Timer instance
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: TIMx registers are de-initialized
220 * - ERROR: invalid TIMx instance
221 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)222 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
223 {
224 ErrorStatus result = SUCCESS;
225
226 /* Check the parameters */
227 assert_param(IS_TIM_INSTANCE(TIMx));
228
229 if (TIMx == TIM1)
230 {
231 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
232 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
233 }
234 #if defined(TIM2)
235 else if (TIMx == TIM2)
236 {
237 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
238 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
239 }
240 #endif /* TIM2 */
241 else if (TIMx == TIM3)
242 {
243 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
244 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
245 }
246 else if (TIMx == TIM14)
247 {
248 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14);
249 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM14);
250 }
251 else if (TIMx == TIM16)
252 {
253 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
254 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
255 }
256 else if (TIMx == TIM17)
257 {
258 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
259 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
260 }
261 else
262 {
263 result = ERROR;
264 }
265
266 return result;
267 }
268
269 /**
270 * @brief Set the fields of the time base unit configuration data structure
271 * to their default values.
272 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
273 * @retval None
274 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)275 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
276 {
277 /* Set the default configuration */
278 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
279 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
280 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
281 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
282 TIM_InitStruct->RepetitionCounter = 0x00000000U;
283 }
284
285 /**
286 * @brief Configure the TIMx time base unit.
287 * @param TIMx Timer Instance
288 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
289 * (TIMx time base unit configuration data structure)
290 * @retval An ErrorStatus enumeration value:
291 * - SUCCESS: TIMx registers are de-initialized
292 * - ERROR: not applicable
293 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)294 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
295 {
296 uint32_t tmpcr1;
297
298 /* Check the parameters */
299 assert_param(IS_TIM_INSTANCE(TIMx));
300 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
301 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
302
303 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
304
305 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
306 {
307 /* Select the Counter Mode */
308 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
309 }
310
311 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
312 {
313 /* Set the clock division */
314 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
315 }
316
317 /* Write to TIMx CR1 */
318 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
319
320 /* Set the Autoreload value */
321 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
322
323 /* Set the Prescaler value */
324 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
325
326 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
327 {
328 /* Set the Repetition Counter value */
329 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
330 }
331
332 /* Generate an update event to reload the Prescaler
333 and the repetition counter value (if applicable) immediately */
334 LL_TIM_GenerateEvent_UPDATE(TIMx);
335
336 return SUCCESS;
337 }
338
339 /**
340 * @brief Set the fields of the TIMx output channel configuration data
341 * structure to their default values.
342 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
343 * (the output channel configuration data structure)
344 * @retval None
345 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)346 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
347 {
348 /* Set the default configuration */
349 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
350 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
351 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
352 TIM_OC_InitStruct->CompareValue = 0x00000000U;
353 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
354 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
355 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
356 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
357 }
358
359 /**
360 * @brief Configure the TIMx output channel.
361 * @param TIMx Timer Instance
362 * @param Channel This parameter can be one of the following values:
363 * @arg @ref LL_TIM_CHANNEL_CH1
364 * @arg @ref LL_TIM_CHANNEL_CH2
365 * @arg @ref LL_TIM_CHANNEL_CH3
366 * @arg @ref LL_TIM_CHANNEL_CH4
367 * @arg @ref LL_TIM_CHANNEL_CH5
368 * @arg @ref LL_TIM_CHANNEL_CH6
369 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
370 * data structure)
371 * @retval An ErrorStatus enumeration value:
372 * - SUCCESS: TIMx output channel is initialized
373 * - ERROR: TIMx output channel is not initialized
374 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)375 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
376 {
377 ErrorStatus result = ERROR;
378
379 switch (Channel)
380 {
381 case LL_TIM_CHANNEL_CH1:
382 result = OC1Config(TIMx, TIM_OC_InitStruct);
383 break;
384 case LL_TIM_CHANNEL_CH2:
385 result = OC2Config(TIMx, TIM_OC_InitStruct);
386 break;
387 case LL_TIM_CHANNEL_CH3:
388 result = OC3Config(TIMx, TIM_OC_InitStruct);
389 break;
390 case LL_TIM_CHANNEL_CH4:
391 result = OC4Config(TIMx, TIM_OC_InitStruct);
392 break;
393 case LL_TIM_CHANNEL_CH5:
394 result = OC5Config(TIMx, TIM_OC_InitStruct);
395 break;
396 case LL_TIM_CHANNEL_CH6:
397 result = OC6Config(TIMx, TIM_OC_InitStruct);
398 break;
399 default:
400 break;
401 }
402
403 return result;
404 }
405
406 /**
407 * @brief Set the fields of the TIMx input channel configuration data
408 * structure to their default values.
409 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
410 * data structure)
411 * @retval None
412 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)413 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
414 {
415 /* Set the default configuration */
416 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
417 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
418 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
419 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
420 }
421
422 /**
423 * @brief Configure the TIMx input channel.
424 * @param TIMx Timer Instance
425 * @param Channel This parameter can be one of the following values:
426 * @arg @ref LL_TIM_CHANNEL_CH1
427 * @arg @ref LL_TIM_CHANNEL_CH2
428 * @arg @ref LL_TIM_CHANNEL_CH3
429 * @arg @ref LL_TIM_CHANNEL_CH4
430 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
431 * structure)
432 * @retval An ErrorStatus enumeration value:
433 * - SUCCESS: TIMx output channel is initialized
434 * - ERROR: TIMx output channel is not initialized
435 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)436 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
437 {
438 ErrorStatus result = ERROR;
439
440 switch (Channel)
441 {
442 case LL_TIM_CHANNEL_CH1:
443 result = IC1Config(TIMx, TIM_IC_InitStruct);
444 break;
445 case LL_TIM_CHANNEL_CH2:
446 result = IC2Config(TIMx, TIM_IC_InitStruct);
447 break;
448 case LL_TIM_CHANNEL_CH3:
449 result = IC3Config(TIMx, TIM_IC_InitStruct);
450 break;
451 case LL_TIM_CHANNEL_CH4:
452 result = IC4Config(TIMx, TIM_IC_InitStruct);
453 break;
454 default:
455 break;
456 }
457
458 return result;
459 }
460
461 /**
462 * @brief Fills each TIM_EncoderInitStruct field with its default value
463 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
464 * configuration data structure)
465 * @retval None
466 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)467 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
468 {
469 /* Set the default configuration */
470 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
471 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
472 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
473 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
474 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
475 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
476 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
477 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
478 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
479 }
480
481 /**
482 * @brief Configure the encoder interface of the timer instance.
483 * @param TIMx Timer Instance
484 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
485 * configuration data structure)
486 * @retval An ErrorStatus enumeration value:
487 * - SUCCESS: TIMx registers are de-initialized
488 * - ERROR: not applicable
489 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)490 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
491 {
492 uint32_t tmpccmr1;
493 uint32_t tmpccer;
494
495 /* Check the parameters */
496 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
497 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
498 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
499 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
500 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
501 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
502 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
503 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
504 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
505 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
506
507 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
508 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
509
510 /* Get the TIMx CCMR1 register value */
511 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
512
513 /* Get the TIMx CCER register value */
514 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
515
516 /* Configure TI1 */
517 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
518 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
519 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
520 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
521
522 /* Configure TI2 */
523 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
524 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
525 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
526 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
527
528 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
529 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
530 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
531 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
532 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
533
534 /* Set encoder mode */
535 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
536
537 /* Write to TIMx CCMR1 */
538 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
539
540 /* Write to TIMx CCER */
541 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
542
543 return SUCCESS;
544 }
545
546 /**
547 * @brief Set the fields of the TIMx Hall sensor interface configuration data
548 * structure to their default values.
549 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
550 * configuration data structure)
551 * @retval None
552 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)553 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
554 {
555 /* Set the default configuration */
556 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
557 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
558 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
559 TIM_HallSensorInitStruct->CommutationDelay = 0U;
560 }
561
562 /**
563 * @brief Configure the Hall sensor interface of the timer instance.
564 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
565 * to the TI1 input channel
566 * @note TIMx slave mode controller is configured in reset mode.
567 Selected internal trigger is TI1F_ED.
568 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
569 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
570 * between 2 changes on the inputs. It gives information about motor speed.
571 * @note Channel 2 is configured in output PWM 2 mode.
572 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
573 * @note OC2REF is selected as trigger output on TRGO.
574 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
575 * when TIMx operates in Hall sensor interface mode.
576 * @param TIMx Timer Instance
577 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
578 * interface configuration data structure)
579 * @retval An ErrorStatus enumeration value:
580 * - SUCCESS: TIMx registers are de-initialized
581 * - ERROR: not applicable
582 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)583 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
584 {
585 uint32_t tmpcr2;
586 uint32_t tmpccmr1;
587 uint32_t tmpccer;
588 uint32_t tmpsmcr;
589
590 /* Check the parameters */
591 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
592 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
593 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
594 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
595
596 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
597 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
598
599 /* Get the TIMx CR2 register value */
600 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
601
602 /* Get the TIMx CCMR1 register value */
603 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
604
605 /* Get the TIMx CCER register value */
606 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
607
608 /* Get the TIMx SMCR register value */
609 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
610
611 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
612 tmpcr2 |= TIM_CR2_TI1S;
613
614 /* OC2REF signal is used as trigger output (TRGO) */
615 tmpcr2 |= LL_TIM_TRGO_OC2REF;
616
617 /* Configure the slave mode controller */
618 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
619 tmpsmcr |= LL_TIM_TS_TI1F_ED;
620 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
621
622 /* Configure input channel 1 */
623 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
624 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
625 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
626 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
627
628 /* Configure input channel 2 */
629 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
630 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
631
632 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
633 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
634 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
635 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
636
637 /* Write to TIMx CR2 */
638 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
639
640 /* Write to TIMx SMCR */
641 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
642
643 /* Write to TIMx CCMR1 */
644 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
645
646 /* Write to TIMx CCER */
647 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
648
649 /* Write to TIMx CCR2 */
650 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
651
652 return SUCCESS;
653 }
654
655 /**
656 * @brief Set the fields of the Break and Dead Time configuration data structure
657 * to their default values.
658 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
659 * data structure)
660 * @retval None
661 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)662 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
663 {
664 /* Set the default configuration */
665 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
666 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
667 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
668 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
669 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
670 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
671 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
672 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
673 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
674 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
675 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
676 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
677 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
678 }
679
680 /**
681 * @brief Configure the Break and Dead Time feature of the timer instance.
682 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
683 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
684 * can be necessary to configure all of them during the first write access to
685 * the TIMx_BDTR register.
686 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
687 * a timer instance provides a break input.
688 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
689 * a timer instance provides a second break input.
690 * @param TIMx Timer Instance
691 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
692 * data structure)
693 * @retval An ErrorStatus enumeration value:
694 * - SUCCESS: Break and Dead Time is initialized
695 * - ERROR: not applicable
696 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)697 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
698 {
699 uint32_t tmpbdtr = 0;
700
701 /* Check the parameters */
702 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
703 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
704 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
705 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
706 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
707 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
708 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
709
710 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
711 the OSSI State, the dead time value and the Automatic Output Enable Bit */
712
713 /* Set the BDTR bits */
714 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
715 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
716 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
717 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
718 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
719 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
720 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
721 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
722 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
723 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
724 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
725
726 if (IS_TIM_BKIN2_INSTANCE(TIMx))
727 {
728 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
729 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
730 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
731 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
732
733 /* Set the BREAK2 input related BDTR bit-fields */
734 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
735 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
736 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
737 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
738 }
739
740 /* Set TIMx_BDTR */
741 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
742
743 return SUCCESS;
744 }
745 /**
746 * @}
747 */
748
749 /**
750 * @}
751 */
752
753 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
754 * @brief Private functions
755 * @{
756 */
757 /**
758 * @brief Configure the TIMx output channel 1.
759 * @param TIMx Timer Instance
760 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
761 * @retval An ErrorStatus enumeration value:
762 * - SUCCESS: TIMx registers are de-initialized
763 * - ERROR: not applicable
764 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)765 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
766 {
767 uint32_t tmpccmr1;
768 uint32_t tmpccer;
769 uint32_t tmpcr2;
770
771 /* Check the parameters */
772 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
773 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
774 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
775 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
776 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
777 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
778
779 /* Disable the Channel 1: Reset the CC1E Bit */
780 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
781
782 /* Get the TIMx CCER register value */
783 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
784
785 /* Get the TIMx CR2 register value */
786 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
787
788 /* Get the TIMx CCMR1 register value */
789 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
790
791 /* Reset Capture/Compare selection Bits */
792 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
793
794 /* Set the Output Compare Mode */
795 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
796
797 /* Set the Output Compare Polarity */
798 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
799
800 /* Set the Output State */
801 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
802
803 if (IS_TIM_BREAK_INSTANCE(TIMx))
804 {
805 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
806 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
807
808 /* Set the complementary output Polarity */
809 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
810
811 /* Set the complementary output State */
812 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
813
814 /* Set the Output Idle state */
815 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
816
817 /* Set the complementary output Idle state */
818 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
819 }
820
821 /* Write to TIMx CR2 */
822 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
823
824 /* Write to TIMx CCMR1 */
825 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
826
827 /* Set the Capture Compare Register value */
828 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
829
830 /* Write to TIMx CCER */
831 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
832
833 return SUCCESS;
834 }
835
836 /**
837 * @brief Configure the TIMx output channel 2.
838 * @param TIMx Timer Instance
839 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
840 * @retval An ErrorStatus enumeration value:
841 * - SUCCESS: TIMx registers are de-initialized
842 * - ERROR: not applicable
843 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)844 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
845 {
846 uint32_t tmpccmr1;
847 uint32_t tmpccer;
848 uint32_t tmpcr2;
849
850 /* Check the parameters */
851 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
852 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
853 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
854 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
855 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
856 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
857
858 /* Disable the Channel 2: Reset the CC2E Bit */
859 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
860
861 /* Get the TIMx CCER register value */
862 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
863
864 /* Get the TIMx CR2 register value */
865 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
866
867 /* Get the TIMx CCMR1 register value */
868 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
869
870 /* Reset Capture/Compare selection Bits */
871 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
872
873 /* Select the Output Compare Mode */
874 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
875
876 /* Set the Output Compare Polarity */
877 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
878
879 /* Set the Output State */
880 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
881
882 if (IS_TIM_BREAK_INSTANCE(TIMx))
883 {
884 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
885 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
886
887 /* Set the complementary output Polarity */
888 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
889
890 /* Set the complementary output State */
891 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
892
893 /* Set the Output Idle state */
894 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
895
896 /* Set the complementary output Idle state */
897 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
898 }
899
900 /* Write to TIMx CR2 */
901 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
902
903 /* Write to TIMx CCMR1 */
904 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
905
906 /* Set the Capture Compare Register value */
907 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
908
909 /* Write to TIMx CCER */
910 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
911
912 return SUCCESS;
913 }
914
915 /**
916 * @brief Configure the TIMx output channel 3.
917 * @param TIMx Timer Instance
918 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
919 * @retval An ErrorStatus enumeration value:
920 * - SUCCESS: TIMx registers are de-initialized
921 * - ERROR: not applicable
922 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)923 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
924 {
925 uint32_t tmpccmr2;
926 uint32_t tmpccer;
927 uint32_t tmpcr2;
928
929 /* Check the parameters */
930 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
931 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
932 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
933 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
934 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
935 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
936
937 /* Disable the Channel 3: Reset the CC3E Bit */
938 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
939
940 /* Get the TIMx CCER register value */
941 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
942
943 /* Get the TIMx CR2 register value */
944 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
945
946 /* Get the TIMx CCMR2 register value */
947 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
948
949 /* Reset Capture/Compare selection Bits */
950 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
951
952 /* Select the Output Compare Mode */
953 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
954
955 /* Set the Output Compare Polarity */
956 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
957
958 /* Set the Output State */
959 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
960
961 if (IS_TIM_BREAK_INSTANCE(TIMx))
962 {
963 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
964 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
965
966 /* Set the complementary output Polarity */
967 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
968
969 /* Set the complementary output State */
970 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
971
972 /* Set the Output Idle state */
973 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
974
975 /* Set the complementary output Idle state */
976 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
977 }
978
979 /* Write to TIMx CR2 */
980 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
981
982 /* Write to TIMx CCMR2 */
983 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
984
985 /* Set the Capture Compare Register value */
986 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
987
988 /* Write to TIMx CCER */
989 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
990
991 return SUCCESS;
992 }
993
994 /**
995 * @brief Configure the TIMx output channel 4.
996 * @param TIMx Timer Instance
997 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
998 * @retval An ErrorStatus enumeration value:
999 * - SUCCESS: TIMx registers are de-initialized
1000 * - ERROR: not applicable
1001 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1002 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1003 {
1004 uint32_t tmpccmr2;
1005 uint32_t tmpccer;
1006 uint32_t tmpcr2;
1007
1008 /* Check the parameters */
1009 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1010 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1011 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1012 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1013 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1014 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1015
1016 /* Disable the Channel 4: Reset the CC4E Bit */
1017 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1018
1019 /* Get the TIMx CCER register value */
1020 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1021
1022 /* Get the TIMx CR2 register value */
1023 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1024
1025 /* Get the TIMx CCMR2 register value */
1026 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1027
1028 /* Reset Capture/Compare selection Bits */
1029 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1030
1031 /* Select the Output Compare Mode */
1032 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1033
1034 /* Set the Output Compare Polarity */
1035 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1036
1037 /* Set the Output State */
1038 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1039
1040 if (IS_TIM_BREAK_INSTANCE(TIMx))
1041 {
1042 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1043 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1044
1045 /* Set the Output Idle state */
1046 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1047 }
1048
1049 /* Write to TIMx CR2 */
1050 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1051
1052 /* Write to TIMx CCMR2 */
1053 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1054
1055 /* Set the Capture Compare Register value */
1056 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1057
1058 /* Write to TIMx CCER */
1059 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1060
1061 return SUCCESS;
1062 }
1063
1064 /**
1065 * @brief Configure the TIMx output channel 5.
1066 * @param TIMx Timer Instance
1067 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1068 * @retval An ErrorStatus enumeration value:
1069 * - SUCCESS: TIMx registers are de-initialized
1070 * - ERROR: not applicable
1071 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1072 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1073 {
1074 uint32_t tmpccmr3;
1075 uint32_t tmpccer;
1076
1077 /* Check the parameters */
1078 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1079 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1080 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1081 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1082 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1083 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1084
1085 /* Disable the Channel 5: Reset the CC5E Bit */
1086 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1087
1088 /* Get the TIMx CCER register value */
1089 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1090
1091 /* Get the TIMx CCMR3 register value */
1092 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1093
1094 /* Select the Output Compare Mode */
1095 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1096
1097 /* Set the Output Compare Polarity */
1098 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1099
1100 /* Set the Output State */
1101 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1102
1103 if (IS_TIM_BREAK_INSTANCE(TIMx))
1104 {
1105 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1106 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1107
1108 /* Set the Output Idle state */
1109 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1110
1111 }
1112
1113 /* Write to TIMx CCMR3 */
1114 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1115
1116 /* Set the Capture Compare Register value */
1117 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1118
1119 /* Write to TIMx CCER */
1120 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1121
1122 return SUCCESS;
1123 }
1124
1125 /**
1126 * @brief Configure the TIMx output channel 6.
1127 * @param TIMx Timer Instance
1128 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1129 * @retval An ErrorStatus enumeration value:
1130 * - SUCCESS: TIMx registers are de-initialized
1131 * - ERROR: not applicable
1132 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1133 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1134 {
1135 uint32_t tmpccmr3;
1136 uint32_t tmpccer;
1137
1138 /* Check the parameters */
1139 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1140 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1141 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1142 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1143 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1144 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1145
1146 /* Disable the Channel 5: Reset the CC6E Bit */
1147 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1148
1149 /* Get the TIMx CCER register value */
1150 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1151
1152 /* Get the TIMx CCMR3 register value */
1153 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1154
1155 /* Select the Output Compare Mode */
1156 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1157
1158 /* Set the Output Compare Polarity */
1159 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1160
1161 /* Set the Output State */
1162 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1163
1164 if (IS_TIM_BREAK_INSTANCE(TIMx))
1165 {
1166 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1167 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1168
1169 /* Set the Output Idle state */
1170 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1171 }
1172
1173 /* Write to TIMx CCMR3 */
1174 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1175
1176 /* Set the Capture Compare Register value */
1177 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1178
1179 /* Write to TIMx CCER */
1180 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1181
1182 return SUCCESS;
1183 }
1184
1185 /**
1186 * @brief Configure the TIMx input channel 1.
1187 * @param TIMx Timer Instance
1188 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1189 * @retval An ErrorStatus enumeration value:
1190 * - SUCCESS: TIMx registers are de-initialized
1191 * - ERROR: not applicable
1192 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1193 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1194 {
1195 /* Check the parameters */
1196 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1197 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1198 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1199 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1200 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1201
1202 /* Disable the Channel 1: Reset the CC1E Bit */
1203 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1204
1205 /* Select the Input and set the filter and the prescaler value */
1206 MODIFY_REG(TIMx->CCMR1,
1207 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1208 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1209
1210 /* Select the Polarity and set the CC1E Bit */
1211 MODIFY_REG(TIMx->CCER,
1212 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1213 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1214
1215 return SUCCESS;
1216 }
1217
1218 /**
1219 * @brief Configure the TIMx input channel 2.
1220 * @param TIMx Timer Instance
1221 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1222 * @retval An ErrorStatus enumeration value:
1223 * - SUCCESS: TIMx registers are de-initialized
1224 * - ERROR: not applicable
1225 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1226 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1227 {
1228 /* Check the parameters */
1229 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1230 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1231 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1232 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1233 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1234
1235 /* Disable the Channel 2: Reset the CC2E Bit */
1236 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1237
1238 /* Select the Input and set the filter and the prescaler value */
1239 MODIFY_REG(TIMx->CCMR1,
1240 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1241 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1242
1243 /* Select the Polarity and set the CC2E Bit */
1244 MODIFY_REG(TIMx->CCER,
1245 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1246 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1247
1248 return SUCCESS;
1249 }
1250
1251 /**
1252 * @brief Configure the TIMx input channel 3.
1253 * @param TIMx Timer Instance
1254 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1255 * @retval An ErrorStatus enumeration value:
1256 * - SUCCESS: TIMx registers are de-initialized
1257 * - ERROR: not applicable
1258 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1259 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1260 {
1261 /* Check the parameters */
1262 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1263 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1264 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1265 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1266 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1267
1268 /* Disable the Channel 3: Reset the CC3E Bit */
1269 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1270
1271 /* Select the Input and set the filter and the prescaler value */
1272 MODIFY_REG(TIMx->CCMR2,
1273 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1274 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1275
1276 /* Select the Polarity and set the CC3E Bit */
1277 MODIFY_REG(TIMx->CCER,
1278 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1279 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1280
1281 return SUCCESS;
1282 }
1283
1284 /**
1285 * @brief Configure the TIMx input channel 4.
1286 * @param TIMx Timer Instance
1287 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1288 * @retval An ErrorStatus enumeration value:
1289 * - SUCCESS: TIMx registers are de-initialized
1290 * - ERROR: not applicable
1291 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1292 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1293 {
1294 /* Check the parameters */
1295 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1296 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1297 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1298 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1299 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1300
1301 /* Disable the Channel 4: Reset the CC4E Bit */
1302 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1303
1304 /* Select the Input and set the filter and the prescaler value */
1305 MODIFY_REG(TIMx->CCMR2,
1306 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1307 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1308
1309 /* Select the Polarity and set the CC2E Bit */
1310 MODIFY_REG(TIMx->CCER,
1311 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1312 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1313
1314 return SUCCESS;
1315 }
1316
1317
1318 /**
1319 * @}
1320 */
1321
1322 /**
1323 * @}
1324 */
1325
1326 #endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM16 || TIM17 */
1327
1328 /**
1329 * @}
1330 */
1331
1332 #endif /* USE_FULL_LL_DRIVER */
1333
1334
