1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wbaxx_ll_tim.h"
22 #include "stm32wbaxx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM16) || defined (TIM17)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \
71 || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
72 || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
73
74 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
75 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
76
77 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
78 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
79
80 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
81 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
82
83 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
84 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
85 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
86
87 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
89 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
90 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
91
92 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
108
109 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
111 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
112
113 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
114 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
115 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
116 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
117 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
118 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
119 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
120 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
121 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
122
123 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
124 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
125
126 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
127 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
128
129 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
130 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
131
132 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
133 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
134 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
135 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
136
137 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
138 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
139
140 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
141 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
142
143 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
152 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
153 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
154 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
159
160 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
161 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
162
163 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
164 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
165
166 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
167 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
168
169 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
185
186 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
187 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
188
189 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
190 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
191 /**
192 * @}
193 */
194
195
196 /* Private function prototypes -----------------------------------------------*/
197 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
198 * @{
199 */
200 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
201 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
202 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
203 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
204 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
205 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
206 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
207 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
208 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
209 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
210 /**
211 * @}
212 */
213
214 /* Exported functions --------------------------------------------------------*/
215 /** @addtogroup TIM_LL_Exported_Functions
216 * @{
217 */
218
219 /** @addtogroup TIM_LL_EF_Init
220 * @{
221 */
222
223 /**
224 * @brief Set TIMx registers to their reset values.
225 * @param TIMx Timer instance
226 * @retval An ErrorStatus enumeration value:
227 * - SUCCESS: TIMx registers are de-initialized
228 * - ERROR: invalid TIMx instance
229 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)230 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
231 {
232 ErrorStatus result = SUCCESS;
233
234 /* Check the parameters */
235 assert_param(IS_TIM_INSTANCE(TIMx));
236
237 if (TIMx == TIM1)
238 {
239 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
240 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
241 }
242 else if (TIMx == TIM2)
243 {
244 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
245 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
246 }
247 #if defined(TIM3)
248 else if (TIMx == TIM3)
249 {
250 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
251 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
252 }
253 #endif /* TIM3 */
254 else if (TIMx == TIM16)
255 {
256 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
257 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
258 }
259 #if defined(TIM17)
260 else if (TIMx == TIM17)
261 {
262 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
263 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
264 }
265 #endif /* TIM17 */
266 else
267 {
268 result = ERROR;
269 }
270
271 return result;
272 }
273
274 /**
275 * @brief Set the fields of the time base unit configuration data structure
276 * to their default values.
277 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
278 * @retval None
279 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)280 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
281 {
282 /* Set the default configuration */
283 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
284 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
285 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
286 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
287 TIM_InitStruct->RepetitionCounter = 0x00000000U;
288 }
289
290 /**
291 * @brief Configure the TIMx time base unit.
292 * @param TIMx Timer Instance
293 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
294 * (TIMx time base unit configuration data structure)
295 * @retval An ErrorStatus enumeration value:
296 * - SUCCESS: TIMx registers are de-initialized
297 * - ERROR: not applicable
298 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)299 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
300 {
301 uint32_t tmpcr1;
302
303 /* Check the parameters */
304 assert_param(IS_TIM_INSTANCE(TIMx));
305 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
306 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
307
308 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
309
310 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
311 {
312 /* Select the Counter Mode */
313 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
314 }
315
316 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
317 {
318 /* Set the clock division */
319 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
320 }
321
322 /* Write to TIMx CR1 */
323 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
324
325 /* Set the Autoreload value */
326 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
327
328 /* Set the Prescaler value */
329 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
330
331 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
332 {
333 /* Set the Repetition Counter value */
334 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
335 }
336
337 /* Generate an update event to reload the Prescaler
338 and the repetition counter value (if applicable) immediately */
339 LL_TIM_GenerateEvent_UPDATE(TIMx);
340
341 return SUCCESS;
342 }
343
344 /**
345 * @brief Set the fields of the TIMx output channel configuration data
346 * structure to their default values.
347 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
348 * (the output channel configuration data structure)
349 * @retval None
350 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)351 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
352 {
353 /* Set the default configuration */
354 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
355 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
356 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
357 TIM_OC_InitStruct->CompareValue = 0x00000000U;
358 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
359 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
360 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
361 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
362 }
363
364 /**
365 * @brief Configure the TIMx output channel.
366 * @param TIMx Timer Instance
367 * @param Channel This parameter can be one of the following values:
368 * @arg @ref LL_TIM_CHANNEL_CH1
369 * @arg @ref LL_TIM_CHANNEL_CH2
370 * @arg @ref LL_TIM_CHANNEL_CH3
371 * @arg @ref LL_TIM_CHANNEL_CH4
372 * @arg @ref LL_TIM_CHANNEL_CH5
373 * @arg @ref LL_TIM_CHANNEL_CH6
374 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
375 * data structure)
376 * @retval An ErrorStatus enumeration value:
377 * - SUCCESS: TIMx output channel is initialized
378 * - ERROR: TIMx output channel is not initialized
379 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)380 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
381 {
382 ErrorStatus result = ERROR;
383
384 switch (Channel)
385 {
386 case LL_TIM_CHANNEL_CH1:
387 result = OC1Config(TIMx, TIM_OC_InitStruct);
388 break;
389 case LL_TIM_CHANNEL_CH2:
390 result = OC2Config(TIMx, TIM_OC_InitStruct);
391 break;
392 case LL_TIM_CHANNEL_CH3:
393 result = OC3Config(TIMx, TIM_OC_InitStruct);
394 break;
395 case LL_TIM_CHANNEL_CH4:
396 result = OC4Config(TIMx, TIM_OC_InitStruct);
397 break;
398 case LL_TIM_CHANNEL_CH5:
399 result = OC5Config(TIMx, TIM_OC_InitStruct);
400 break;
401 case LL_TIM_CHANNEL_CH6:
402 result = OC6Config(TIMx, TIM_OC_InitStruct);
403 break;
404 default:
405 break;
406 }
407
408 return result;
409 }
410
411 /**
412 * @brief Set the fields of the TIMx input channel configuration data
413 * structure to their default values.
414 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
415 * data structure)
416 * @retval None
417 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)418 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
419 {
420 /* Set the default configuration */
421 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
422 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
423 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
424 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
425 }
426
427 /**
428 * @brief Configure the TIMx input channel.
429 * @param TIMx Timer Instance
430 * @param Channel This parameter can be one of the following values:
431 * @arg @ref LL_TIM_CHANNEL_CH1
432 * @arg @ref LL_TIM_CHANNEL_CH2
433 * @arg @ref LL_TIM_CHANNEL_CH3
434 * @arg @ref LL_TIM_CHANNEL_CH4
435 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
436 * structure)
437 * @retval An ErrorStatus enumeration value:
438 * - SUCCESS: TIMx output channel is initialized
439 * - ERROR: TIMx output channel is not initialized
440 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)441 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
442 {
443 ErrorStatus result = ERROR;
444
445 switch (Channel)
446 {
447 case LL_TIM_CHANNEL_CH1:
448 result = IC1Config(TIMx, TIM_IC_InitStruct);
449 break;
450 case LL_TIM_CHANNEL_CH2:
451 result = IC2Config(TIMx, TIM_IC_InitStruct);
452 break;
453 case LL_TIM_CHANNEL_CH3:
454 result = IC3Config(TIMx, TIM_IC_InitStruct);
455 break;
456 case LL_TIM_CHANNEL_CH4:
457 result = IC4Config(TIMx, TIM_IC_InitStruct);
458 break;
459 default:
460 break;
461 }
462
463 return result;
464 }
465
466 /**
467 * @brief Fills each TIM_EncoderInitStruct field with its default value
468 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
469 * configuration data structure)
470 * @retval None
471 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)472 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
473 {
474 /* Set the default configuration */
475 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
476 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
477 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
478 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
479 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
480 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
481 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
482 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
483 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
484 }
485
486 /**
487 * @brief Configure the encoder interface of the timer instance.
488 * @param TIMx Timer Instance
489 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
490 * configuration data structure)
491 * @retval An ErrorStatus enumeration value:
492 * - SUCCESS: TIMx registers are de-initialized
493 * - ERROR: not applicable
494 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)495 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
496 {
497 uint32_t tmpccmr1;
498 uint32_t tmpccer;
499
500 /* Check the parameters */
501 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
502 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
503 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
504 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
505 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
506 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
507 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
508 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
509 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
510 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
511
512 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
513 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
514
515 /* Get the TIMx CCMR1 register value */
516 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
517
518 /* Get the TIMx CCER register value */
519 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
520
521 /* Configure TI1 */
522 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
523 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
524 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
525 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
526
527 /* Configure TI2 */
528 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
529 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
530 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
531 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
532
533 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
534 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
535 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
536 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
537 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
538
539 /* Set encoder mode */
540 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
541
542 /* Write to TIMx CCMR1 */
543 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
544
545 /* Write to TIMx CCER */
546 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
547
548 return SUCCESS;
549 }
550
551 /**
552 * @brief Set the fields of the TIMx Hall sensor interface configuration data
553 * structure to their default values.
554 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
555 * configuration data structure)
556 * @retval None
557 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)558 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
559 {
560 /* Set the default configuration */
561 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
562 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
563 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
564 TIM_HallSensorInitStruct->CommutationDelay = 0U;
565 }
566
567 /**
568 * @brief Configure the Hall sensor interface of the timer instance.
569 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
570 * to the TI1 input channel
571 * @note TIMx slave mode controller is configured in reset mode.
572 Selected internal trigger is TI1F_ED.
573 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
574 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
575 * between 2 changes on the inputs. It gives information about motor speed.
576 * @note Channel 2 is configured in output PWM 2 mode.
577 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
578 * @note OC2REF is selected as trigger output on TRGO.
579 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
580 * when TIMx operates in Hall sensor interface mode.
581 * @param TIMx Timer Instance
582 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
583 * interface configuration data structure)
584 * @retval An ErrorStatus enumeration value:
585 * - SUCCESS: TIMx registers are de-initialized
586 * - ERROR: not applicable
587 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)588 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
589 {
590 uint32_t tmpcr2;
591 uint32_t tmpccmr1;
592 uint32_t tmpccer;
593 uint32_t tmpsmcr;
594
595 /* Check the parameters */
596 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
597 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
598 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
599 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
600
601 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
602 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
603
604 /* Get the TIMx CR2 register value */
605 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
606
607 /* Get the TIMx CCMR1 register value */
608 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
609
610 /* Get the TIMx CCER register value */
611 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
612
613 /* Get the TIMx SMCR register value */
614 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
615
616 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
617 tmpcr2 |= TIM_CR2_TI1S;
618
619 /* OC2REF signal is used as trigger output (TRGO) */
620 tmpcr2 |= LL_TIM_TRGO_OC2REF;
621
622 /* Configure the slave mode controller */
623 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
624 tmpsmcr |= LL_TIM_TS_TI1F_ED;
625 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
626
627 /* Configure input channel 1 */
628 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
629 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
630 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
631 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
632
633 /* Configure input channel 2 */
634 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
635 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
636
637 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
638 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
639 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
640 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
641
642 /* Write to TIMx CR2 */
643 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
644
645 /* Write to TIMx SMCR */
646 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
647
648 /* Write to TIMx CCMR1 */
649 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
650
651 /* Write to TIMx CCER */
652 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
653
654 /* Write to TIMx CCR2 */
655 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
656
657 return SUCCESS;
658 }
659
660 /**
661 * @brief Set the fields of the Break and Dead Time configuration data structure
662 * to their default values.
663 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
664 * data structure)
665 * @retval None
666 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)667 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
668 {
669 /* Set the default configuration */
670 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
671 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
672 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
673 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
674 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
675 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
676 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
677 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
678 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
679 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
680 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
681 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
682 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
683 }
684
685 /**
686 * @brief Configure the Break and Dead Time feature of the timer instance.
687 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
688 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
689 * can be necessary to configure all of them during the first write access to
690 * the TIMx_BDTR register.
691 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
692 * a timer instance provides a break input.
693 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
694 * a timer instance provides a second break input.
695 * @param TIMx Timer Instance
696 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
697 * data structure)
698 * @retval An ErrorStatus enumeration value:
699 * - SUCCESS: Break and Dead Time is initialized
700 * - ERROR: not applicable
701 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)702 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
703 {
704 uint32_t tmpbdtr = 0;
705
706 /* Check the parameters */
707 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
708 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
709 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
710 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
711 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
712 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
713 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
714
715 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
716 the OSSI State, the dead time value and the Automatic Output Enable Bit */
717
718 /* Set the BDTR bits */
719 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
720 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
721 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
722 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
723 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
724 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
725 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
726 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
727 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
728 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
729 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
730
731 if (IS_TIM_BKIN2_INSTANCE(TIMx))
732 {
733 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
734 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
735 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
736 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
737
738 /* Set the BREAK2 input related BDTR bit-fields */
739 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
740 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
741 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
742 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
743 }
744
745 /* Set TIMx_BDTR */
746 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
747
748 return SUCCESS;
749 }
750 /**
751 * @}
752 */
753
754 /**
755 * @}
756 */
757
758 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
759 * @brief Private functions
760 * @{
761 */
762 /**
763 * @brief Configure the TIMx output channel 1.
764 * @param TIMx Timer Instance
765 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
766 * @retval An ErrorStatus enumeration value:
767 * - SUCCESS: TIMx registers are de-initialized
768 * - ERROR: not applicable
769 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)770 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
771 {
772 uint32_t tmpccmr1;
773 uint32_t tmpccer;
774 uint32_t tmpcr2;
775
776 /* Check the parameters */
777 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
778 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
779 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
780 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
781 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
782 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
783
784 /* Disable the Channel 1: Reset the CC1E Bit */
785 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
786
787 /* Get the TIMx CCER register value */
788 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
789
790 /* Get the TIMx CR2 register value */
791 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
792
793 /* Get the TIMx CCMR1 register value */
794 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
795
796 /* Reset Capture/Compare selection Bits */
797 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
798
799 /* Set the Output Compare Mode */
800 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
801
802 /* Set the Output Compare Polarity */
803 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
804
805 /* Set the Output State */
806 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
807
808 if (IS_TIM_BREAK_INSTANCE(TIMx))
809 {
810 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
811 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
812
813 /* Set the complementary output Polarity */
814 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
815
816 /* Set the complementary output State */
817 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
818
819 /* Set the Output Idle state */
820 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
821
822 /* Set the complementary output Idle state */
823 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
824 }
825
826 /* Write to TIMx CR2 */
827 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
828
829 /* Write to TIMx CCMR1 */
830 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
831
832 /* Set the Capture Compare Register value */
833 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
834
835 /* Write to TIMx CCER */
836 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
837
838 return SUCCESS;
839 }
840
841 /**
842 * @brief Configure the TIMx output channel 2.
843 * @param TIMx Timer Instance
844 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
845 * @retval An ErrorStatus enumeration value:
846 * - SUCCESS: TIMx registers are de-initialized
847 * - ERROR: not applicable
848 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)849 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
850 {
851 uint32_t tmpccmr1;
852 uint32_t tmpccer;
853 uint32_t tmpcr2;
854
855 /* Check the parameters */
856 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
857 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
858 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
859 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
860 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
861 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
862
863 /* Disable the Channel 2: Reset the CC2E Bit */
864 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
865
866 /* Get the TIMx CCER register value */
867 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
868
869 /* Get the TIMx CR2 register value */
870 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
871
872 /* Get the TIMx CCMR1 register value */
873 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
874
875 /* Reset Capture/Compare selection Bits */
876 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
877
878 /* Select the Output Compare Mode */
879 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
880
881 /* Set the Output Compare Polarity */
882 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
883
884 /* Set the Output State */
885 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
886
887 if (IS_TIM_BREAK_INSTANCE(TIMx))
888 {
889 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
890 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
891
892 /* Set the complementary output Polarity */
893 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
894
895 /* Set the complementary output State */
896 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
897
898 /* Set the Output Idle state */
899 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
900
901 /* Set the complementary output Idle state */
902 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
903 }
904
905 /* Write to TIMx CR2 */
906 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
907
908 /* Write to TIMx CCMR1 */
909 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
910
911 /* Set the Capture Compare Register value */
912 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
913
914 /* Write to TIMx CCER */
915 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
916
917 return SUCCESS;
918 }
919
920 /**
921 * @brief Configure the TIMx output channel 3.
922 * @param TIMx Timer Instance
923 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
924 * @retval An ErrorStatus enumeration value:
925 * - SUCCESS: TIMx registers are de-initialized
926 * - ERROR: not applicable
927 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)928 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
929 {
930 uint32_t tmpccmr2;
931 uint32_t tmpccer;
932 uint32_t tmpcr2;
933
934 /* Check the parameters */
935 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
936 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
937 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
938 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
939 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
940 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
941
942 /* Disable the Channel 3: Reset the CC3E Bit */
943 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
944
945 /* Get the TIMx CCER register value */
946 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
947
948 /* Get the TIMx CR2 register value */
949 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
950
951 /* Get the TIMx CCMR2 register value */
952 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
953
954 /* Reset Capture/Compare selection Bits */
955 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
956
957 /* Select the Output Compare Mode */
958 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
959
960 /* Set the Output Compare Polarity */
961 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
962
963 /* Set the Output State */
964 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
965
966 if (IS_TIM_BREAK_INSTANCE(TIMx))
967 {
968 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
969 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
970
971 /* Set the complementary output Polarity */
972 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
973
974 /* Set the complementary output State */
975 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
976
977 /* Set the Output Idle state */
978 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
979
980 /* Set the complementary output Idle state */
981 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
982 }
983
984 /* Write to TIMx CR2 */
985 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
986
987 /* Write to TIMx CCMR2 */
988 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
989
990 /* Set the Capture Compare Register value */
991 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
992
993 /* Write to TIMx CCER */
994 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
995
996 return SUCCESS;
997 }
998
999 /**
1000 * @brief Configure the TIMx output channel 4.
1001 * @param TIMx Timer Instance
1002 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1003 * @retval An ErrorStatus enumeration value:
1004 * - SUCCESS: TIMx registers are de-initialized
1005 * - ERROR: not applicable
1006 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1007 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1008 {
1009 uint32_t tmpccmr2;
1010 uint32_t tmpccer;
1011 uint32_t tmpcr2;
1012
1013 /* Check the parameters */
1014 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1015 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1016 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1017 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1018 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1019 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1020
1021 /* Disable the Channel 4: Reset the CC4E Bit */
1022 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1023
1024 /* Get the TIMx CCER register value */
1025 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1026
1027 /* Get the TIMx CR2 register value */
1028 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1029
1030 /* Get the TIMx CCMR2 register value */
1031 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1032
1033 /* Reset Capture/Compare selection Bits */
1034 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1035
1036 /* Select the Output Compare Mode */
1037 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1038
1039 /* Set the Output Compare Polarity */
1040 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1041
1042 /* Set the Output State */
1043 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1044
1045 if (IS_TIM_BREAK_INSTANCE(TIMx))
1046 {
1047 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1048 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1049
1050 /* Set the complementary output Polarity */
1051 MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
1052
1053 /* Set the complementary output State */
1054 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
1055
1056 /* Set the Output Idle state */
1057 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1058
1059 /* Set the complementary output Idle state */
1060 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
1061 }
1062
1063 /* Write to TIMx CR2 */
1064 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1065
1066 /* Write to TIMx CCMR2 */
1067 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1068
1069 /* Set the Capture Compare Register value */
1070 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1071
1072 /* Write to TIMx CCER */
1073 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1074
1075 return SUCCESS;
1076 }
1077
1078 /**
1079 * @brief Configure the TIMx output channel 5.
1080 * @param TIMx Timer Instance
1081 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1082 * @retval An ErrorStatus enumeration value:
1083 * - SUCCESS: TIMx registers are de-initialized
1084 * - ERROR: not applicable
1085 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1086 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1087 {
1088 uint32_t tmpccmr3;
1089 uint32_t tmpccer;
1090
1091 /* Check the parameters */
1092 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1093 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1094 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1095 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1096 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1097 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1098
1099 /* Disable the Channel 5: Reset the CC5E Bit */
1100 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1101
1102 /* Get the TIMx CCER register value */
1103 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1104
1105 /* Get the TIMx CCMR3 register value */
1106 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1107
1108 /* Select the Output Compare Mode */
1109 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1110
1111 /* Set the Output Compare Polarity */
1112 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1113
1114 /* Set the Output State */
1115 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1116
1117 if (IS_TIM_BREAK_INSTANCE(TIMx))
1118 {
1119 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1120 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1121
1122 /* Set the Output Idle state */
1123 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1124
1125 }
1126
1127 /* Write to TIMx CCMR3 */
1128 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1129
1130 /* Set the Capture Compare Register value */
1131 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1132
1133 /* Write to TIMx CCER */
1134 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1135
1136 return SUCCESS;
1137 }
1138
1139 /**
1140 * @brief Configure the TIMx output channel 6.
1141 * @param TIMx Timer Instance
1142 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1143 * @retval An ErrorStatus enumeration value:
1144 * - SUCCESS: TIMx registers are de-initialized
1145 * - ERROR: not applicable
1146 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1147 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1148 {
1149 uint32_t tmpccmr3;
1150 uint32_t tmpccer;
1151
1152 /* Check the parameters */
1153 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1154 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1155 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1156 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1157 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1158 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1159
1160 /* Disable the Channel 5: Reset the CC6E Bit */
1161 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1162
1163 /* Get the TIMx CCER register value */
1164 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1165
1166 /* Get the TIMx CCMR3 register value */
1167 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1168
1169 /* Select the Output Compare Mode */
1170 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1171
1172 /* Set the Output Compare Polarity */
1173 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1174
1175 /* Set the Output State */
1176 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1177
1178 if (IS_TIM_BREAK_INSTANCE(TIMx))
1179 {
1180 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1181 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1182
1183 /* Set the Output Idle state */
1184 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1185 }
1186
1187 /* Write to TIMx CCMR3 */
1188 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1189
1190 /* Set the Capture Compare Register value */
1191 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1192
1193 /* Write to TIMx CCER */
1194 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1195
1196 return SUCCESS;
1197 }
1198
1199 /**
1200 * @brief Configure the TIMx input channel 1.
1201 * @param TIMx Timer Instance
1202 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1203 * @retval An ErrorStatus enumeration value:
1204 * - SUCCESS: TIMx registers are de-initialized
1205 * - ERROR: not applicable
1206 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1207 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1208 {
1209 /* Check the parameters */
1210 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1211 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1212 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1213 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1214 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1215
1216 /* Disable the Channel 1: Reset the CC1E Bit */
1217 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1218
1219 /* Select the Input and set the filter and the prescaler value */
1220 MODIFY_REG(TIMx->CCMR1,
1221 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1222 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1223
1224 /* Select the Polarity and set the CC1E Bit */
1225 MODIFY_REG(TIMx->CCER,
1226 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1227 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1228
1229 return SUCCESS;
1230 }
1231
1232 /**
1233 * @brief Configure the TIMx input channel 2.
1234 * @param TIMx Timer Instance
1235 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1236 * @retval An ErrorStatus enumeration value:
1237 * - SUCCESS: TIMx registers are de-initialized
1238 * - ERROR: not applicable
1239 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1240 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1241 {
1242 /* Check the parameters */
1243 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1244 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1245 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1246 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1247 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1248
1249 /* Disable the Channel 2: Reset the CC2E Bit */
1250 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1251
1252 /* Select the Input and set the filter and the prescaler value */
1253 MODIFY_REG(TIMx->CCMR1,
1254 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1255 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1256
1257 /* Select the Polarity and set the CC2E Bit */
1258 MODIFY_REG(TIMx->CCER,
1259 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1260 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1261
1262 return SUCCESS;
1263 }
1264
1265 /**
1266 * @brief Configure the TIMx input channel 3.
1267 * @param TIMx Timer Instance
1268 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1269 * @retval An ErrorStatus enumeration value:
1270 * - SUCCESS: TIMx registers are de-initialized
1271 * - ERROR: not applicable
1272 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1273 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1274 {
1275 /* Check the parameters */
1276 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1277 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1278 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1279 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1280 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1281
1282 /* Disable the Channel 3: Reset the CC3E Bit */
1283 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1284
1285 /* Select the Input and set the filter and the prescaler value */
1286 MODIFY_REG(TIMx->CCMR2,
1287 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1288 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1289
1290 /* Select the Polarity and set the CC3E Bit */
1291 MODIFY_REG(TIMx->CCER,
1292 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1293 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1294
1295 return SUCCESS;
1296 }
1297
1298 /**
1299 * @brief Configure the TIMx input channel 4.
1300 * @param TIMx Timer Instance
1301 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1302 * @retval An ErrorStatus enumeration value:
1303 * - SUCCESS: TIMx registers are de-initialized
1304 * - ERROR: not applicable
1305 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1306 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1307 {
1308 /* Check the parameters */
1309 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1310 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1311 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1312 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1313 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1314
1315 /* Disable the Channel 4: Reset the CC4E Bit */
1316 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1317
1318 /* Select the Input and set the filter and the prescaler value */
1319 MODIFY_REG(TIMx->CCMR2,
1320 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1321 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1322
1323 /* Select the Polarity and set the CC2E Bit */
1324 MODIFY_REG(TIMx->CCER,
1325 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1326 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1327
1328 return SUCCESS;
1329 }
1330
1331
1332 /**
1333 * @}
1334 */
1335
1336 /**
1337 * @}
1338 */
1339
1340 #endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 */
1341
1342 /**
1343 * @}
1344 */
1345
1346 #endif /* USE_FULL_LL_DRIVER */
1347
1348
