1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wbxx_ll_tim.h"
22 #include "stm32wbxx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
153 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
154
155 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
156 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
157
158 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
159 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
160
161 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
177
178 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
179 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
180
181 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
182 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
183 /**
184 * @}
185 */
186
187
188 /* Private function prototypes -----------------------------------------------*/
189 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
190 * @{
191 */
192 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
193 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
194 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
195 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
199 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
200 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
201 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
202 /**
203 * @}
204 */
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @addtogroup TIM_LL_Exported_Functions
208 * @{
209 */
210
211 /** @addtogroup TIM_LL_EF_Init
212 * @{
213 */
214
215 /**
216 * @brief Set TIMx registers to their reset values.
217 * @param TIMx Timer instance
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: TIMx registers are de-initialized
220 * - ERROR: invalid TIMx instance
221 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)222 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
223 {
224 ErrorStatus result = SUCCESS;
225
226 /* Check the parameters */
227 assert_param(IS_TIM_INSTANCE(TIMx));
228
229 if (TIMx == TIM1)
230 {
231 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
232 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
233 }
234 else if (TIMx == TIM2)
235 {
236 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
237 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
238 }
239 #if defined(TIM16)
240 else if (TIMx == TIM16)
241 {
242 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
243 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
244 }
245 #endif
246 #if defined(TIM17)
247 else if (TIMx == TIM17)
248 {
249 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
250 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
251 }
252 #endif
253 else
254 {
255 result = ERROR;
256 }
257
258 return result;
259 }
260
261 /**
262 * @brief Set the fields of the time base unit configuration data structure
263 * to their default values.
264 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
265 * @retval None
266 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)267 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
268 {
269 /* Set the default configuration */
270 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
271 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
272 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
273 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
274 TIM_InitStruct->RepetitionCounter = 0x00000000U;
275 }
276
277 /**
278 * @brief Configure the TIMx time base unit.
279 * @param TIMx Timer Instance
280 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
281 * (TIMx time base unit configuration data structure)
282 * @retval An ErrorStatus enumeration value:
283 * - SUCCESS: TIMx registers are de-initialized
284 * - ERROR: not applicable
285 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)286 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
287 {
288 uint32_t tmpcr1;
289
290 /* Check the parameters */
291 assert_param(IS_TIM_INSTANCE(TIMx));
292 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
293 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
294
295 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
296
297 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
298 {
299 /* Select the Counter Mode */
300 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
301 }
302
303 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
304 {
305 /* Set the clock division */
306 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
307 }
308
309 /* Write to TIMx CR1 */
310 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
311
312 /* Set the Autoreload value */
313 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
314
315 /* Set the Prescaler value */
316 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
317
318 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
319 {
320 /* Set the Repetition Counter value */
321 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
322 }
323
324 /* Generate an update event to reload the Prescaler
325 and the repetition counter value (if applicable) immediately */
326 LL_TIM_GenerateEvent_UPDATE(TIMx);
327
328 return SUCCESS;
329 }
330
331 /**
332 * @brief Set the fields of the TIMx output channel configuration data
333 * structure to their default values.
334 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
335 * (the output channel configuration data structure)
336 * @retval None
337 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)338 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
339 {
340 /* Set the default configuration */
341 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
342 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
343 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
344 TIM_OC_InitStruct->CompareValue = 0x00000000U;
345 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
346 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
347 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
348 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
349 }
350
351 /**
352 * @brief Configure the TIMx output channel.
353 * @param TIMx Timer Instance
354 * @param Channel This parameter can be one of the following values:
355 * @arg @ref LL_TIM_CHANNEL_CH1
356 * @arg @ref LL_TIM_CHANNEL_CH2
357 * @arg @ref LL_TIM_CHANNEL_CH3
358 * @arg @ref LL_TIM_CHANNEL_CH4
359 * @arg @ref LL_TIM_CHANNEL_CH5
360 * @arg @ref LL_TIM_CHANNEL_CH6
361 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
362 * data structure)
363 * @retval An ErrorStatus enumeration value:
364 * - SUCCESS: TIMx output channel is initialized
365 * - ERROR: TIMx output channel is not initialized
366 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)367 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
368 {
369 ErrorStatus result = ERROR;
370
371 switch (Channel)
372 {
373 case LL_TIM_CHANNEL_CH1:
374 result = OC1Config(TIMx, TIM_OC_InitStruct);
375 break;
376 case LL_TIM_CHANNEL_CH2:
377 result = OC2Config(TIMx, TIM_OC_InitStruct);
378 break;
379 case LL_TIM_CHANNEL_CH3:
380 result = OC3Config(TIMx, TIM_OC_InitStruct);
381 break;
382 case LL_TIM_CHANNEL_CH4:
383 result = OC4Config(TIMx, TIM_OC_InitStruct);
384 break;
385 case LL_TIM_CHANNEL_CH5:
386 result = OC5Config(TIMx, TIM_OC_InitStruct);
387 break;
388 case LL_TIM_CHANNEL_CH6:
389 result = OC6Config(TIMx, TIM_OC_InitStruct);
390 break;
391 default:
392 break;
393 }
394
395 return result;
396 }
397
398 /**
399 * @brief Set the fields of the TIMx input channel configuration data
400 * structure to their default values.
401 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
402 * data structure)
403 * @retval None
404 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)405 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
406 {
407 /* Set the default configuration */
408 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
409 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
410 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
411 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
412 }
413
414 /**
415 * @brief Configure the TIMx input channel.
416 * @param TIMx Timer Instance
417 * @param Channel This parameter can be one of the following values:
418 * @arg @ref LL_TIM_CHANNEL_CH1
419 * @arg @ref LL_TIM_CHANNEL_CH2
420 * @arg @ref LL_TIM_CHANNEL_CH3
421 * @arg @ref LL_TIM_CHANNEL_CH4
422 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
423 * structure)
424 * @retval An ErrorStatus enumeration value:
425 * - SUCCESS: TIMx output channel is initialized
426 * - ERROR: TIMx output channel is not initialized
427 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)428 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
429 {
430 ErrorStatus result = ERROR;
431
432 switch (Channel)
433 {
434 case LL_TIM_CHANNEL_CH1:
435 result = IC1Config(TIMx, TIM_IC_InitStruct);
436 break;
437 case LL_TIM_CHANNEL_CH2:
438 result = IC2Config(TIMx, TIM_IC_InitStruct);
439 break;
440 case LL_TIM_CHANNEL_CH3:
441 result = IC3Config(TIMx, TIM_IC_InitStruct);
442 break;
443 case LL_TIM_CHANNEL_CH4:
444 result = IC4Config(TIMx, TIM_IC_InitStruct);
445 break;
446 default:
447 break;
448 }
449
450 return result;
451 }
452
453 /**
454 * @brief Fills each TIM_EncoderInitStruct field with its default value
455 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
456 * configuration data structure)
457 * @retval None
458 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)459 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
460 {
461 /* Set the default configuration */
462 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
463 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
464 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
465 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
466 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
467 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
468 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
469 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
470 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
471 }
472
473 /**
474 * @brief Configure the encoder interface of the timer instance.
475 * @param TIMx Timer Instance
476 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
477 * configuration data structure)
478 * @retval An ErrorStatus enumeration value:
479 * - SUCCESS: TIMx registers are de-initialized
480 * - ERROR: not applicable
481 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)482 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
483 {
484 uint32_t tmpccmr1;
485 uint32_t tmpccer;
486
487 /* Check the parameters */
488 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
489 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
490 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
491 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
492 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
493 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
494 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
495 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
496 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
497 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
498
499 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
500 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
501
502 /* Get the TIMx CCMR1 register value */
503 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
504
505 /* Get the TIMx CCER register value */
506 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
507
508 /* Configure TI1 */
509 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
510 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
511 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
512 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
513
514 /* Configure TI2 */
515 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
516 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
517 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
518 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
519
520 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
521 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
522 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
523 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
524 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
525
526 /* Set encoder mode */
527 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
528
529 /* Write to TIMx CCMR1 */
530 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
531
532 /* Write to TIMx CCER */
533 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
534
535 return SUCCESS;
536 }
537
538 /**
539 * @brief Set the fields of the TIMx Hall sensor interface configuration data
540 * structure to their default values.
541 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
542 * configuration data structure)
543 * @retval None
544 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)545 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
546 {
547 /* Set the default configuration */
548 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
549 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
550 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
551 TIM_HallSensorInitStruct->CommutationDelay = 0U;
552 }
553
554 /**
555 * @brief Configure the Hall sensor interface of the timer instance.
556 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
557 * to the TI1 input channel
558 * @note TIMx slave mode controller is configured in reset mode.
559 Selected internal trigger is TI1F_ED.
560 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
561 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
562 * between 2 changes on the inputs. It gives information about motor speed.
563 * @note Channel 2 is configured in output PWM 2 mode.
564 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
565 * @note OC2REF is selected as trigger output on TRGO.
566 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
567 * when TIMx operates in Hall sensor interface mode.
568 * @param TIMx Timer Instance
569 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
570 * interface configuration data structure)
571 * @retval An ErrorStatus enumeration value:
572 * - SUCCESS: TIMx registers are de-initialized
573 * - ERROR: not applicable
574 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)575 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
576 {
577 uint32_t tmpcr2;
578 uint32_t tmpccmr1;
579 uint32_t tmpccer;
580 uint32_t tmpsmcr;
581
582 /* Check the parameters */
583 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
584 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
585 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
586 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
587
588 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
589 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
590
591 /* Get the TIMx CR2 register value */
592 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
593
594 /* Get the TIMx CCMR1 register value */
595 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
596
597 /* Get the TIMx CCER register value */
598 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
599
600 /* Get the TIMx SMCR register value */
601 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
602
603 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
604 tmpcr2 |= TIM_CR2_TI1S;
605
606 /* OC2REF signal is used as trigger output (TRGO) */
607 tmpcr2 |= LL_TIM_TRGO_OC2REF;
608
609 /* Configure the slave mode controller */
610 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
611 tmpsmcr |= LL_TIM_TS_TI1F_ED;
612 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
613
614 /* Configure input channel 1 */
615 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
616 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
617 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
618 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
619
620 /* Configure input channel 2 */
621 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
622 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
623
624 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
625 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
626 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
627 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
628
629 /* Write to TIMx CR2 */
630 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
631
632 /* Write to TIMx SMCR */
633 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
634
635 /* Write to TIMx CCMR1 */
636 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
637
638 /* Write to TIMx CCER */
639 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
640
641 /* Write to TIMx CCR2 */
642 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
643
644 return SUCCESS;
645 }
646
647 /**
648 * @brief Set the fields of the Break and Dead Time configuration data structure
649 * to their default values.
650 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
651 * data structure)
652 * @retval None
653 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)654 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
655 {
656 /* Set the default configuration */
657 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
658 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
659 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
660 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
661 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
662 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
663 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
664 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
665 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
666 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
667 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
668 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
669 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
670 }
671
672 /**
673 * @brief Configure the Break and Dead Time feature of the timer instance.
674 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
675 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
676 * can be necessary to configure all of them during the first write access to
677 * the TIMx_BDTR register.
678 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
679 * a timer instance provides a break input.
680 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
681 * a timer instance provides a second break input.
682 * @param TIMx Timer Instance
683 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
684 * data structure)
685 * @retval An ErrorStatus enumeration value:
686 * - SUCCESS: Break and Dead Time is initialized
687 * - ERROR: not applicable
688 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)689 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
690 {
691 uint32_t tmpbdtr = 0;
692
693 /* Check the parameters */
694 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
695 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
696 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
697 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
698 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
699 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
700 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
701
702 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
703 the OSSI State, the dead time value and the Automatic Output Enable Bit */
704
705 /* Set the BDTR bits */
706 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
707 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
708 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
709 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
710 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
711 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
712 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
713 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
714 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
715 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
716 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
717
718 if (IS_TIM_BKIN2_INSTANCE(TIMx))
719 {
720 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
721 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
722 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
723 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
724
725 /* Set the BREAK2 input related BDTR bit-fields */
726 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
727 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
728 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
729 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
730 }
731
732 /* Set TIMx_BDTR */
733 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
734
735 return SUCCESS;
736 }
737 /**
738 * @}
739 */
740
741 /**
742 * @}
743 */
744
745 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
746 * @brief Private functions
747 * @{
748 */
749 /**
750 * @brief Configure the TIMx output channel 1.
751 * @param TIMx Timer Instance
752 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
753 * @retval An ErrorStatus enumeration value:
754 * - SUCCESS: TIMx registers are de-initialized
755 * - ERROR: not applicable
756 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)757 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
758 {
759 uint32_t tmpccmr1;
760 uint32_t tmpccer;
761 uint32_t tmpcr2;
762
763 /* Check the parameters */
764 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
765 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
766 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
767 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
768 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
769 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
770
771 /* Disable the Channel 1: Reset the CC1E Bit */
772 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
773
774 /* Get the TIMx CCER register value */
775 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
776
777 /* Get the TIMx CR2 register value */
778 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
779
780 /* Get the TIMx CCMR1 register value */
781 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
782
783 /* Reset Capture/Compare selection Bits */
784 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
785
786 /* Set the Output Compare Mode */
787 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
788
789 /* Set the Output Compare Polarity */
790 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
791
792 /* Set the Output State */
793 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
794
795 if (IS_TIM_BREAK_INSTANCE(TIMx))
796 {
797 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
798 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
799
800 /* Set the complementary output Polarity */
801 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
802
803 /* Set the complementary output State */
804 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
805
806 /* Set the Output Idle state */
807 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
808
809 /* Set the complementary output Idle state */
810 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
811 }
812
813 /* Write to TIMx CR2 */
814 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
815
816 /* Write to TIMx CCMR1 */
817 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
818
819 /* Set the Capture Compare Register value */
820 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
821
822 /* Write to TIMx CCER */
823 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
824
825 return SUCCESS;
826 }
827
828 /**
829 * @brief Configure the TIMx output channel 2.
830 * @param TIMx Timer Instance
831 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
832 * @retval An ErrorStatus enumeration value:
833 * - SUCCESS: TIMx registers are de-initialized
834 * - ERROR: not applicable
835 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)836 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
837 {
838 uint32_t tmpccmr1;
839 uint32_t tmpccer;
840 uint32_t tmpcr2;
841
842 /* Check the parameters */
843 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
844 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
845 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
846 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
847 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
848 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
849
850 /* Disable the Channel 2: Reset the CC2E Bit */
851 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
852
853 /* Get the TIMx CCER register value */
854 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
855
856 /* Get the TIMx CR2 register value */
857 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
858
859 /* Get the TIMx CCMR1 register value */
860 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
861
862 /* Reset Capture/Compare selection Bits */
863 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
864
865 /* Select the Output Compare Mode */
866 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
867
868 /* Set the Output Compare Polarity */
869 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
870
871 /* Set the Output State */
872 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
873
874 if (IS_TIM_BREAK_INSTANCE(TIMx))
875 {
876 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
877 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
878
879 /* Set the complementary output Polarity */
880 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
881
882 /* Set the complementary output State */
883 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
884
885 /* Set the Output Idle state */
886 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
887
888 /* Set the complementary output Idle state */
889 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
890 }
891
892 /* Write to TIMx CR2 */
893 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
894
895 /* Write to TIMx CCMR1 */
896 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
897
898 /* Set the Capture Compare Register value */
899 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
900
901 /* Write to TIMx CCER */
902 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
903
904 return SUCCESS;
905 }
906
907 /**
908 * @brief Configure the TIMx output channel 3.
909 * @param TIMx Timer Instance
910 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
911 * @retval An ErrorStatus enumeration value:
912 * - SUCCESS: TIMx registers are de-initialized
913 * - ERROR: not applicable
914 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)915 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
916 {
917 uint32_t tmpccmr2;
918 uint32_t tmpccer;
919 uint32_t tmpcr2;
920
921 /* Check the parameters */
922 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
923 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
924 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
925 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
926 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
927 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
928
929 /* Disable the Channel 3: Reset the CC3E Bit */
930 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
931
932 /* Get the TIMx CCER register value */
933 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
934
935 /* Get the TIMx CR2 register value */
936 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
937
938 /* Get the TIMx CCMR2 register value */
939 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
940
941 /* Reset Capture/Compare selection Bits */
942 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
943
944 /* Select the Output Compare Mode */
945 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
946
947 /* Set the Output Compare Polarity */
948 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
949
950 /* Set the Output State */
951 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
952
953 if (IS_TIM_BREAK_INSTANCE(TIMx))
954 {
955 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
956 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
957
958 /* Set the complementary output Polarity */
959 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
960
961 /* Set the complementary output State */
962 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
963
964 /* Set the Output Idle state */
965 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
966
967 /* Set the complementary output Idle state */
968 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
969 }
970
971 /* Write to TIMx CR2 */
972 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
973
974 /* Write to TIMx CCMR2 */
975 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
976
977 /* Set the Capture Compare Register value */
978 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
979
980 /* Write to TIMx CCER */
981 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
982
983 return SUCCESS;
984 }
985
986 /**
987 * @brief Configure the TIMx output channel 4.
988 * @param TIMx Timer Instance
989 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
990 * @retval An ErrorStatus enumeration value:
991 * - SUCCESS: TIMx registers are de-initialized
992 * - ERROR: not applicable
993 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)994 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
995 {
996 uint32_t tmpccmr2;
997 uint32_t tmpccer;
998 uint32_t tmpcr2;
999
1000 /* Check the parameters */
1001 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1002 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1003 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1004 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1005 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1006 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1007
1008 /* Disable the Channel 4: Reset the CC4E Bit */
1009 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1010
1011 /* Get the TIMx CCER register value */
1012 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1013
1014 /* Get the TIMx CR2 register value */
1015 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1016
1017 /* Get the TIMx CCMR2 register value */
1018 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1019
1020 /* Reset Capture/Compare selection Bits */
1021 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1022
1023 /* Select the Output Compare Mode */
1024 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1025
1026 /* Set the Output Compare Polarity */
1027 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1028
1029 /* Set the Output State */
1030 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1031
1032 if (IS_TIM_BREAK_INSTANCE(TIMx))
1033 {
1034 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1035 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1036
1037 /* Set the Output Idle state */
1038 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1039 }
1040
1041 /* Write to TIMx CR2 */
1042 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1043
1044 /* Write to TIMx CCMR2 */
1045 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1046
1047 /* Set the Capture Compare Register value */
1048 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1049
1050 /* Write to TIMx CCER */
1051 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1052
1053 return SUCCESS;
1054 }
1055
1056 /**
1057 * @brief Configure the TIMx output channel 5.
1058 * @param TIMx Timer Instance
1059 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1060 * @retval An ErrorStatus enumeration value:
1061 * - SUCCESS: TIMx registers are de-initialized
1062 * - ERROR: not applicable
1063 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1064 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1065 {
1066 uint32_t tmpccmr3;
1067 uint32_t tmpccer;
1068
1069 /* Check the parameters */
1070 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1071 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1072 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1073 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1074 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1075 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1076
1077 /* Disable the Channel 5: Reset the CC5E Bit */
1078 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1079
1080 /* Get the TIMx CCER register value */
1081 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1082
1083 /* Get the TIMx CCMR3 register value */
1084 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1085
1086 /* Select the Output Compare Mode */
1087 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1088
1089 /* Set the Output Compare Polarity */
1090 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1091
1092 /* Set the Output State */
1093 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1094
1095 if (IS_TIM_BREAK_INSTANCE(TIMx))
1096 {
1097 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1098 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1099
1100 /* Set the Output Idle state */
1101 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1102
1103 }
1104
1105 /* Write to TIMx CCMR3 */
1106 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1107
1108 /* Set the Capture Compare Register value */
1109 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1110
1111 /* Write to TIMx CCER */
1112 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1113
1114 return SUCCESS;
1115 }
1116
1117 /**
1118 * @brief Configure the TIMx output channel 6.
1119 * @param TIMx Timer Instance
1120 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1121 * @retval An ErrorStatus enumeration value:
1122 * - SUCCESS: TIMx registers are de-initialized
1123 * - ERROR: not applicable
1124 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1125 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1126 {
1127 uint32_t tmpccmr3;
1128 uint32_t tmpccer;
1129
1130 /* Check the parameters */
1131 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1132 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1133 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1134 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1135 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1136 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1137
1138 /* Disable the Channel 5: Reset the CC6E Bit */
1139 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1140
1141 /* Get the TIMx CCER register value */
1142 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1143
1144 /* Get the TIMx CCMR3 register value */
1145 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1146
1147 /* Select the Output Compare Mode */
1148 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1149
1150 /* Set the Output Compare Polarity */
1151 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1152
1153 /* Set the Output State */
1154 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1155
1156 if (IS_TIM_BREAK_INSTANCE(TIMx))
1157 {
1158 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1159 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1160
1161 /* Set the Output Idle state */
1162 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1163 }
1164
1165 /* Write to TIMx CCMR3 */
1166 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1167
1168 /* Set the Capture Compare Register value */
1169 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1170
1171 /* Write to TIMx CCER */
1172 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1173
1174 return SUCCESS;
1175 }
1176
1177 /**
1178 * @brief Configure the TIMx input channel 1.
1179 * @param TIMx Timer Instance
1180 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1181 * @retval An ErrorStatus enumeration value:
1182 * - SUCCESS: TIMx registers are de-initialized
1183 * - ERROR: not applicable
1184 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1185 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1186 {
1187 /* Check the parameters */
1188 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1189 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1190 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1191 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1192 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1193
1194 /* Disable the Channel 1: Reset the CC1E Bit */
1195 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1196
1197 /* Select the Input and set the filter and the prescaler value */
1198 MODIFY_REG(TIMx->CCMR1,
1199 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1200 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1201
1202 /* Select the Polarity and set the CC1E Bit */
1203 MODIFY_REG(TIMx->CCER,
1204 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1205 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1206
1207 return SUCCESS;
1208 }
1209
1210 /**
1211 * @brief Configure the TIMx input channel 2.
1212 * @param TIMx Timer Instance
1213 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1214 * @retval An ErrorStatus enumeration value:
1215 * - SUCCESS: TIMx registers are de-initialized
1216 * - ERROR: not applicable
1217 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1218 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1219 {
1220 /* Check the parameters */
1221 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1222 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1223 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1224 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1225 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1226
1227 /* Disable the Channel 2: Reset the CC2E Bit */
1228 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1229
1230 /* Select the Input and set the filter and the prescaler value */
1231 MODIFY_REG(TIMx->CCMR1,
1232 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1233 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1234
1235 /* Select the Polarity and set the CC2E Bit */
1236 MODIFY_REG(TIMx->CCER,
1237 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1238 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1239
1240 return SUCCESS;
1241 }
1242
1243 /**
1244 * @brief Configure the TIMx input channel 3.
1245 * @param TIMx Timer Instance
1246 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1247 * @retval An ErrorStatus enumeration value:
1248 * - SUCCESS: TIMx registers are de-initialized
1249 * - ERROR: not applicable
1250 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1251 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1252 {
1253 /* Check the parameters */
1254 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1255 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1256 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1257 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1258 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1259
1260 /* Disable the Channel 3: Reset the CC3E Bit */
1261 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1262
1263 /* Select the Input and set the filter and the prescaler value */
1264 MODIFY_REG(TIMx->CCMR2,
1265 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1266 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1267
1268 /* Select the Polarity and set the CC3E Bit */
1269 MODIFY_REG(TIMx->CCER,
1270 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1271 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1272
1273 return SUCCESS;
1274 }
1275
1276 /**
1277 * @brief Configure the TIMx input channel 4.
1278 * @param TIMx Timer Instance
1279 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1280 * @retval An ErrorStatus enumeration value:
1281 * - SUCCESS: TIMx registers are de-initialized
1282 * - ERROR: not applicable
1283 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1284 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1285 {
1286 /* Check the parameters */
1287 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1288 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1289 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1290 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1291 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1292
1293 /* Disable the Channel 4: Reset the CC4E Bit */
1294 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1295
1296 /* Select the Input and set the filter and the prescaler value */
1297 MODIFY_REG(TIMx->CCMR2,
1298 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1299 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1300
1301 /* Select the Polarity and set the CC2E Bit */
1302 MODIFY_REG(TIMx->CCER,
1303 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1304 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1305
1306 return SUCCESS;
1307 }
1308
1309
1310 /**
1311 * @}
1312 */
1313
1314 /**
1315 * @}
1316 */
1317
1318 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
1319
1320 /**
1321 * @}
1322 */
1323
1324 #endif /* USE_FULL_LL_DRIVER */
1325
1326
