1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F4xx_LL_TIM_H
21 #define __STM32F4xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U /* 6: TIMx_CH4 */
54 };
55
56 static const uint8_t SHIFT_TAB_OCxx[] =
57 {
58 0U, /* 0: OC1M, OC1FE, OC1PE */
59 0U, /* 1: - NA */
60 8U, /* 2: OC2M, OC2FE, OC2PE */
61 0U, /* 3: - NA */
62 0U, /* 4: OC3M, OC3FE, OC3PE */
63 0U, /* 5: - NA */
64 8U /* 6: OC4M, OC4FE, OC4PE */
65 };
66
67 static const uint8_t SHIFT_TAB_ICxx[] =
68 {
69 0U, /* 0: CC1S, IC1PSC, IC1F */
70 0U, /* 1: - NA */
71 8U, /* 2: CC2S, IC2PSC, IC2F */
72 0U, /* 3: - NA */
73 0U, /* 4: CC3S, IC3PSC, IC3F */
74 0U, /* 5: - NA */
75 8U /* 6: CC4S, IC4PSC, IC4F */
76 };
77
78 static const uint8_t SHIFT_TAB_CCxP[] =
79 {
80 0U, /* 0: CC1P */
81 2U, /* 1: CC1NP */
82 4U, /* 2: CC2P */
83 6U, /* 3: CC2NP */
84 8U, /* 4: CC3P */
85 10U, /* 5: CC3NP */
86 12U /* 6: CC4P */
87 };
88
89 static const uint8_t SHIFT_TAB_OISx[] =
90 {
91 0U, /* 0: OIS1 */
92 1U, /* 1: OIS1N */
93 2U, /* 2: OIS2 */
94 3U, /* 3: OIS2N */
95 4U, /* 4: OIS3 */
96 5U, /* 5: OIS3N */
97 6U /* 6: OIS4 */
98 };
99 /**
100 * @}
101 */
102
103 /* Private constants ---------------------------------------------------------*/
104 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
105 * @{
106 */
107
108
109 /* Remap mask definitions */
110 #define TIMx_OR_RMP_SHIFT 16U
111 #define TIMx_OR_RMP_MASK 0x0000FFFFU
112 #define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
113 #define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
114 #define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
115
116 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
117 #define DT_DELAY_1 ((uint8_t)0x7F)
118 #define DT_DELAY_2 ((uint8_t)0x3F)
119 #define DT_DELAY_3 ((uint8_t)0x1F)
120 #define DT_DELAY_4 ((uint8_t)0x1F)
121
122 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
123 #define DT_RANGE_1 ((uint8_t)0x00)
124 #define DT_RANGE_2 ((uint8_t)0x80)
125 #define DT_RANGE_3 ((uint8_t)0xC0)
126 #define DT_RANGE_4 ((uint8_t)0xE0)
127
128
129 /**
130 * @}
131 */
132
133 /* Private macros ------------------------------------------------------------*/
134 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
135 * @{
136 */
137 /** @brief Convert channel id into channel index.
138 * @param __CHANNEL__ This parameter can be one of the following values:
139 * @arg @ref LL_TIM_CHANNEL_CH1
140 * @arg @ref LL_TIM_CHANNEL_CH1N
141 * @arg @ref LL_TIM_CHANNEL_CH2
142 * @arg @ref LL_TIM_CHANNEL_CH2N
143 * @arg @ref LL_TIM_CHANNEL_CH3
144 * @arg @ref LL_TIM_CHANNEL_CH3N
145 * @arg @ref LL_TIM_CHANNEL_CH4
146 * @retval none
147 */
148 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
149 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
150 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
151 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
152 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
153 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
154 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
155
156 /** @brief Calculate the deadtime sampling period(in ps).
157 * @param __TIMCLK__ timer input clock frequency (in Hz).
158 * @param __CKD__ This parameter can be one of the following values:
159 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
160 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
161 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
162 * @retval none
163 */
164 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
165 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
166 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
167 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
168 /**
169 * @}
170 */
171
172
173 /* Exported types ------------------------------------------------------------*/
174 #if defined(USE_FULL_LL_DRIVER)
175 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
176 * @{
177 */
178
179 /**
180 * @brief TIM Time Base configuration structure definition.
181 */
182 typedef struct
183 {
184 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
185 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
186
187 This feature can be modified afterwards using unitary function
188 @ref LL_TIM_SetPrescaler().*/
189
190 uint32_t CounterMode; /*!< Specifies the counter mode.
191 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
192
193 This feature can be modified afterwards using unitary function
194 @ref LL_TIM_SetCounterMode().*/
195
196 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
197 Auto-Reload Register at the next update event.
198 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
199 Some timer instances may support 32 bits counters. In that case this parameter must
200 be a number between 0x0000 and 0xFFFFFFFF.
201
202 This feature can be modified afterwards using unitary function
203 @ref LL_TIM_SetAutoReload().*/
204
205 uint32_t ClockDivision; /*!< Specifies the clock division.
206 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
207
208 This feature can be modified afterwards using unitary function
209 @ref LL_TIM_SetClockDivision().*/
210
211 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
212 reaches zero, an update event is generated and counting restarts
213 from the RCR value (N).
214 This means in PWM mode that (N+1) corresponds to:
215 - the number of PWM periods in edge-aligned mode
216 - the number of half PWM period in center-aligned mode
217 GP timers: this parameter must be a number between Min_Data = 0x00 and
218 Max_Data = 0xFF.
219 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
220 Max_Data = 0xFFFF.
221
222 This feature can be modified afterwards using unitary function
223 @ref LL_TIM_SetRepetitionCounter().*/
224 } LL_TIM_InitTypeDef;
225
226 /**
227 * @brief TIM Output Compare configuration structure definition.
228 */
229 typedef struct
230 {
231 uint32_t OCMode; /*!< Specifies the output mode.
232 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
233
234 This feature can be modified afterwards using unitary function
235 @ref LL_TIM_OC_SetMode().*/
236
237 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
238 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
239
240 This feature can be modified afterwards using unitary functions
241 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
242
243 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
244 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
245
246 This feature can be modified afterwards using unitary functions
247 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
248
249 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
250 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
251
252 This feature can be modified afterwards using unitary function
253 LL_TIM_OC_SetCompareCHx (x=1..6).*/
254
255 uint32_t OCPolarity; /*!< Specifies the output polarity.
256 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
257
258 This feature can be modified afterwards using unitary function
259 @ref LL_TIM_OC_SetPolarity().*/
260
261 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
262 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_OC_SetPolarity().*/
266
267
268 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
269 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
270
271 This feature can be modified afterwards using unitary function
272 @ref LL_TIM_OC_SetIdleState().*/
273
274 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
275 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
276
277 This feature can be modified afterwards using unitary function
278 @ref LL_TIM_OC_SetIdleState().*/
279 } LL_TIM_OC_InitTypeDef;
280
281 /**
282 * @brief TIM Input Capture configuration structure definition.
283 */
284
285 typedef struct
286 {
287
288 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
289 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
290
291 This feature can be modified afterwards using unitary function
292 @ref LL_TIM_IC_SetPolarity().*/
293
294 uint32_t ICActiveInput; /*!< Specifies the input.
295 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
296
297 This feature can be modified afterwards using unitary function
298 @ref LL_TIM_IC_SetActiveInput().*/
299
300 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
301 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
302
303 This feature can be modified afterwards using unitary function
304 @ref LL_TIM_IC_SetPrescaler().*/
305
306 uint32_t ICFilter; /*!< Specifies the input capture filter.
307 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
308
309 This feature can be modified afterwards using unitary function
310 @ref LL_TIM_IC_SetFilter().*/
311 } LL_TIM_IC_InitTypeDef;
312
313
314 /**
315 * @brief TIM Encoder interface configuration structure definition.
316 */
317 typedef struct
318 {
319 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
320 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
321
322 This feature can be modified afterwards using unitary function
323 @ref LL_TIM_SetEncoderMode().*/
324
325 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
326 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
327
328 This feature can be modified afterwards using unitary function
329 @ref LL_TIM_IC_SetPolarity().*/
330
331 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
332 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
333
334 This feature can be modified afterwards using unitary function
335 @ref LL_TIM_IC_SetActiveInput().*/
336
337 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
338 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
339
340 This feature can be modified afterwards using unitary function
341 @ref LL_TIM_IC_SetPrescaler().*/
342
343 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
344 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
345
346 This feature can be modified afterwards using unitary function
347 @ref LL_TIM_IC_SetFilter().*/
348
349 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
350 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_IC_SetPolarity().*/
354
355 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
356 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_IC_SetActiveInput().*/
360
361 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
362 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetPrescaler().*/
366
367 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
368 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetFilter().*/
372
373 } LL_TIM_ENCODER_InitTypeDef;
374
375 /**
376 * @brief TIM Hall sensor interface configuration structure definition.
377 */
378 typedef struct
379 {
380
381 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
382 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
383
384 This feature can be modified afterwards using unitary function
385 @ref LL_TIM_IC_SetPolarity().*/
386
387 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
388 Prescaler must be set to get a maximum counter period longer than the
389 time interval between 2 consecutive changes on the Hall inputs.
390 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
391
392 This feature can be modified afterwards using unitary function
393 @ref LL_TIM_IC_SetPrescaler().*/
394
395 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
396 This parameter can be a value of
397 @ref TIM_LL_EC_IC_FILTER.
398
399 This feature can be modified afterwards using unitary function
400 @ref LL_TIM_IC_SetFilter().*/
401
402 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
403 A positive pulse (TRGO event) is generated with a programmable delay every time
404 a change occurs on the Hall inputs.
405 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
406
407 This feature can be modified afterwards using unitary function
408 @ref LL_TIM_OC_SetCompareCH2().*/
409 } LL_TIM_HALLSENSOR_InitTypeDef;
410
411 /**
412 * @brief BDTR (Break and Dead Time) structure definition
413 */
414 typedef struct
415 {
416 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
417 This parameter can be a value of @ref TIM_LL_EC_OSSR
418
419 This feature can be modified afterwards using unitary function
420 @ref LL_TIM_SetOffStates()
421
422 @note This bit-field cannot be modified as long as LOCK level 2 has been
423 programmed. */
424
425 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
426 This parameter can be a value of @ref TIM_LL_EC_OSSI
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_SetOffStates()
430
431 @note This bit-field cannot be modified as long as LOCK level 2 has been
432 programmed. */
433
434 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
435 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
436
437 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
438 register has been written, their content is frozen until the next reset.*/
439
440 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
441 switching-on of the outputs.
442 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
443
444 This feature can be modified afterwards using unitary function
445 @ref LL_TIM_OC_SetDeadTime()
446
447 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
448 programmed. */
449
450 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
451 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
452
453 This feature can be modified afterwards using unitary functions
454 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
455
456 @note This bit-field can not be modified as long as LOCK level 1 has been
457 programmed. */
458
459 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
460 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
461
462 This feature can be modified afterwards using unitary function
463 @ref LL_TIM_ConfigBRK()
464
465 @note This bit-field can not be modified as long as LOCK level 1 has been
466 programmed. */
467
468 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
469 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
470
471 This feature can be modified afterwards using unitary functions
472 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
473
474 @note This bit-field can not be modified as long as LOCK level 1 has been
475 programmed. */
476 } LL_TIM_BDTR_InitTypeDef;
477
478 /**
479 * @}
480 */
481 #endif /* USE_FULL_LL_DRIVER */
482
483 /* Exported constants --------------------------------------------------------*/
484 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
485 * @{
486 */
487
488 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
489 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
490 * @{
491 */
492 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
493 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
494 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
495 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
496 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
497 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
498 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
499 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
500 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
501 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
502 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
503 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
504 /**
505 * @}
506 */
507
508 #if defined(USE_FULL_LL_DRIVER)
509 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
510 * @{
511 */
512 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
513 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
514 /**
515 * @}
516 */
517
518 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
519 * @{
520 */
521 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
522 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
523 /**
524 * @}
525 */
526 #endif /* USE_FULL_LL_DRIVER */
527
528 /** @defgroup TIM_LL_EC_IT IT Defines
529 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
530 * @{
531 */
532 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
533 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
534 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
535 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
536 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
537 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
538 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
539 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
540 /**
541 * @}
542 */
543
544 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
545 * @{
546 */
547 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
548 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
549 /**
550 * @}
551 */
552
553 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
554 * @{
555 */
556 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
557 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
558 /**
559 * @}
560 */
561
562 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
563 * @{
564 */
565 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
566 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
567 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
568 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
569 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
570 /**
571 * @}
572 */
573
574 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
575 * @{
576 */
577 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
578 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
579 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
580 /**
581 * @}
582 */
583
584 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
585 * @{
586 */
587 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
588 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
589 /**
590 * @}
591 */
592
593 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
594 * @{
595 */
596 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
597 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
598 /**
599 * @}
600 */
601
602 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
603 * @{
604 */
605 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
606 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
612 * @{
613 */
614 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
615 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
616 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
617 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
618 /**
619 * @}
620 */
621
622 /** @defgroup TIM_LL_EC_CHANNEL Channel
623 * @{
624 */
625 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
626 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
627 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
628 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
629 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
630 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
631 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
632 /**
633 * @}
634 */
635
636 #if defined(USE_FULL_LL_DRIVER)
637 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
638 * @{
639 */
640 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
641 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
642 /**
643 * @}
644 */
645 #endif /* USE_FULL_LL_DRIVER */
646
647 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
648 * @{
649 */
650 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
651 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
652 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
653 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
654 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
655 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
656 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
657 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
663 * @{
664 */
665 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
666 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
672 * @{
673 */
674 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
675 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
676 /**
677 * @}
678 */
679
680
681 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
682 * @{
683 */
684 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
685 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
686 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
692 * @{
693 */
694 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
695 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
696 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
697 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
703 * @{
704 */
705 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
706 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
707 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
708 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
709 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
710 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
711 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
712 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
713 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
714 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
715 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
716 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
717 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
718 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
719 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
720 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
721 /**
722 * @}
723 */
724
725 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
726 * @{
727 */
728 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
729 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
730 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
731 /**
732 * @}
733 */
734
735 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
736 * @{
737 */
738 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
739 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
740 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
741 /**
742 * @}
743 */
744
745 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
746 * @{
747 */
748 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
749 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
750 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
751 /**
752 * @}
753 */
754
755 /** @defgroup TIM_LL_EC_TRGO Trigger Output
756 * @{
757 */
758 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
759 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
760 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
761 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
762 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
763 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
764 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
765 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
766 /**
767 * @}
768 */
769
770
771 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
772 * @{
773 */
774 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
775 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
776 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
777 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
778 /**
779 * @}
780 */
781
782 /** @defgroup TIM_LL_EC_TS Trigger Selection
783 * @{
784 */
785 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
786 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
787 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
788 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
789 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
790 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
791 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
792 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
793 /**
794 * @}
795 */
796
797 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
798 * @{
799 */
800 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
801 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
802 /**
803 * @}
804 */
805
806 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
807 * @{
808 */
809 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
810 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
811 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
812 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
813 /**
814 * @}
815 */
816
817 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
818 * @{
819 */
820 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
821 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
822 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
823 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
824 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
825 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
826 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
827 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
828 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
829 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
830 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
831 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
832 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
833 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
834 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
835 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
836 /**
837 * @}
838 */
839
840
841 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
842 * @{
843 */
844 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
845 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
846 /**
847 * @}
848 */
849
850
851
852
853 /** @defgroup TIM_LL_EC_OSSI OSSI
854 * @{
855 */
856 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
857 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
858 /**
859 * @}
860 */
861
862 /** @defgroup TIM_LL_EC_OSSR OSSR
863 * @{
864 */
865 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
866 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
867 /**
868 * @}
869 */
870
871
872 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
873 * @{
874 */
875 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
876 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
877 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
878 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
879 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
880 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
881 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
882 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
883 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
884 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
885 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
886 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
887 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
888 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
889 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
890 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
891 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
892 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
893 /**
894 * @}
895 */
896
897 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
898 * @{
899 */
900 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
901 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
902 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
903 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
904 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
905 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
906 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
907 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
908 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
909 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
910 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
911 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
912 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
913 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
914 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
915 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
916 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
917 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
918 /**
919 * @}
920 */
921
922
923 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
924 * @{
925 */
926 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
927 #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
928 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
929 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
930 /**
931 * @}
932 */
933
934 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
935 * @{
936 */
937 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
938 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
939 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
940 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
941 /**
942 * @}
943 */
944
945 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
946 * @{
947 */
948 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
949 #if defined(SPDIFRX)
950 #define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
951
952 /* Legacy define */
953 #define LL_TIM_TIM11_TI1_RMP_GPIO1 LL_TIM_TIM11_TI1_RMP_SPDIFRX /*!< Legacy define for LL_TIM_TIM11_TI1_RMP_SPDIFRX */
954
955 #else
956 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
957 #endif /* SPDIFRX */
958 #define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
959 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */
960 /**
961 * @}
962 */
963 #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
964
965 #define LL_TIM_LPTIM_REMAP_MASK 0x10000000U
966
967 #define LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM9_ITR1 is connected to TIM3 TRGO */
968 #define LL_TIM_TIM9_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9_ITR1 is connected to LPTIM1 output */
969
970 #define LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM5_ITR1 is connected to TIM3 TRGO */
971 #define LL_TIM_TIM5_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5_ITR1 is connected to LPTIM1 output */
972
973 #define LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM1_ITR2 is connected to TIM3 TRGO */
974 #define LL_TIM_TIM1_ITR2_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1_ITR2 is connected to LPTIM1 output */
975
976 #endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
977
978 /**
979 * @}
980 */
981
982 /* Exported macro ------------------------------------------------------------*/
983 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
984 * @{
985 */
986
987 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
988 * @{
989 */
990 /**
991 * @brief Write a value in TIM register.
992 * @param __INSTANCE__ TIM Instance
993 * @param __REG__ Register to be written
994 * @param __VALUE__ Value to be written in the register
995 * @retval None
996 */
997 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
998
999 /**
1000 * @brief Read a value in TIM register.
1001 * @param __INSTANCE__ TIM Instance
1002 * @param __REG__ Register to be read
1003 * @retval Register value
1004 */
1005 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1011 * @{
1012 */
1013
1014 /**
1015 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1016 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1017 * @param __TIMCLK__ timer input clock frequency (in Hz)
1018 * @param __CKD__ This parameter can be one of the following values:
1019 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1020 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1021 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1022 * @param __DT__ deadtime duration (in ns)
1023 * @retval DTG[0:7]
1024 */
1025 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1026 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1027 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1028 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1029 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1030 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1031 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1032 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1033 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1034 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1035 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1036 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1037 0U)
1038
1039 /**
1040 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1041 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1042 * @param __TIMCLK__ timer input clock frequency (in Hz)
1043 * @param __CNTCLK__ counter clock frequency (in Hz)
1044 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1045 */
1046 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1047 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1048
1049 /**
1050 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1051 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1052 * @param __TIMCLK__ timer input clock frequency (in Hz)
1053 * @param __PSC__ prescaler
1054 * @param __FREQ__ output signal frequency (in Hz)
1055 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1056 */
1057 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1058 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1059
1060 /**
1061 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1062 * active/inactive delay.
1063 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1064 * @param __TIMCLK__ timer input clock frequency (in Hz)
1065 * @param __PSC__ prescaler
1066 * @param __DELAY__ timer output compare active/inactive delay (in us)
1067 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1068 */
1069 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1070 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1071 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1072
1073 /**
1074 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1075 * (when the timer operates in one pulse mode).
1076 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1077 * @param __TIMCLK__ timer input clock frequency (in Hz)
1078 * @param __PSC__ prescaler
1079 * @param __DELAY__ timer output compare active/inactive delay (in us)
1080 * @param __PULSE__ pulse duration (in us)
1081 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1082 */
1083 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1084 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1085 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1086
1087 /**
1088 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1089 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1090 * @param __ICPSC__ This parameter can be one of the following values:
1091 * @arg @ref LL_TIM_ICPSC_DIV1
1092 * @arg @ref LL_TIM_ICPSC_DIV2
1093 * @arg @ref LL_TIM_ICPSC_DIV4
1094 * @arg @ref LL_TIM_ICPSC_DIV8
1095 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1096 */
1097 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1098 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1099
1100
1101 /**
1102 * @}
1103 */
1104
1105
1106 /**
1107 * @}
1108 */
1109
1110 /* Exported functions --------------------------------------------------------*/
1111 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1112 * @{
1113 */
1114
1115 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1116 * @{
1117 */
1118 /**
1119 * @brief Enable timer counter.
1120 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1121 * @param TIMx Timer instance
1122 * @retval None
1123 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1124 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1125 {
1126 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1127 }
1128
1129 /**
1130 * @brief Disable timer counter.
1131 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1132 * @param TIMx Timer instance
1133 * @retval None
1134 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1135 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1136 {
1137 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1138 }
1139
1140 /**
1141 * @brief Indicates whether the timer counter is enabled.
1142 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1143 * @param TIMx Timer instance
1144 * @retval State of bit (1 or 0).
1145 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)1146 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1147 {
1148 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1149 }
1150
1151 /**
1152 * @brief Enable update event generation.
1153 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1154 * @param TIMx Timer instance
1155 * @retval None
1156 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1157 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1158 {
1159 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1160 }
1161
1162 /**
1163 * @brief Disable update event generation.
1164 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1165 * @param TIMx Timer instance
1166 * @retval None
1167 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1168 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1169 {
1170 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1171 }
1172
1173 /**
1174 * @brief Indicates whether update event generation is enabled.
1175 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1176 * @param TIMx Timer instance
1177 * @retval Inverted state of bit (0 or 1).
1178 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)1179 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1180 {
1181 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1182 }
1183
1184 /**
1185 * @brief Set update event source
1186 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1187 * generate an update interrupt or DMA request if enabled:
1188 * - Counter overflow/underflow
1189 * - Setting the UG bit
1190 * - Update generation through the slave mode controller
1191 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1192 * overflow/underflow generates an update interrupt or DMA request if enabled.
1193 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1194 * @param TIMx Timer instance
1195 * @param UpdateSource This parameter can be one of the following values:
1196 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1197 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1198 * @retval None
1199 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1200 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1201 {
1202 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1203 }
1204
1205 /**
1206 * @brief Get actual event update source
1207 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1208 * @param TIMx Timer instance
1209 * @retval Returned value can be one of the following values:
1210 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1211 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1212 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)1213 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1214 {
1215 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1216 }
1217
1218 /**
1219 * @brief Set one pulse mode (one shot v.s. repetitive).
1220 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1221 * @param TIMx Timer instance
1222 * @param OnePulseMode This parameter can be one of the following values:
1223 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1224 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1225 * @retval None
1226 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1227 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1228 {
1229 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1230 }
1231
1232 /**
1233 * @brief Get actual one pulse mode.
1234 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1235 * @param TIMx Timer instance
1236 * @retval Returned value can be one of the following values:
1237 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1238 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1239 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)1240 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1241 {
1242 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1243 }
1244
1245 /**
1246 * @brief Set the timer counter counting mode.
1247 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1248 * check whether or not the counter mode selection feature is supported
1249 * by a timer instance.
1250 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1251 * requires a timer reset to avoid unexpected direction
1252 * due to DIR bit readonly in center aligned mode.
1253 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1254 * CR1 CMS LL_TIM_SetCounterMode
1255 * @param TIMx Timer instance
1256 * @param CounterMode This parameter can be one of the following values:
1257 * @arg @ref LL_TIM_COUNTERMODE_UP
1258 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1259 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1260 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1261 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1262 * @retval None
1263 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1264 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1265 {
1266 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1267 }
1268
1269 /**
1270 * @brief Get actual counter mode.
1271 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1272 * check whether or not the counter mode selection feature is supported
1273 * by a timer instance.
1274 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1275 * CR1 CMS LL_TIM_GetCounterMode
1276 * @param TIMx Timer instance
1277 * @retval Returned value can be one of the following values:
1278 * @arg @ref LL_TIM_COUNTERMODE_UP
1279 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1280 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1281 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1282 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1283 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)1284 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1285 {
1286 uint32_t counter_mode;
1287
1288 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1289
1290 if (counter_mode == 0U)
1291 {
1292 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1293 }
1294
1295 return counter_mode;
1296 }
1297
1298 /**
1299 * @brief Enable auto-reload (ARR) preload.
1300 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1301 * @param TIMx Timer instance
1302 * @retval None
1303 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1304 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1305 {
1306 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1307 }
1308
1309 /**
1310 * @brief Disable auto-reload (ARR) preload.
1311 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1312 * @param TIMx Timer instance
1313 * @retval None
1314 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1315 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1316 {
1317 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1318 }
1319
1320 /**
1321 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1322 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1323 * @param TIMx Timer instance
1324 * @retval State of bit (1 or 0).
1325 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)1326 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1327 {
1328 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1329 }
1330
1331 /**
1332 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1333 * (when supported) and the digital filters.
1334 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1335 * whether or not the clock division feature is supported by the timer
1336 * instance.
1337 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1338 * @param TIMx Timer instance
1339 * @param ClockDivision This parameter can be one of the following values:
1340 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1341 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1342 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1343 * @retval None
1344 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1345 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1346 {
1347 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1348 }
1349
1350 /**
1351 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1352 * generators (when supported) and the digital filters.
1353 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1354 * whether or not the clock division feature is supported by the timer
1355 * instance.
1356 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1357 * @param TIMx Timer instance
1358 * @retval Returned value can be one of the following values:
1359 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1360 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1361 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1362 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)1363 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1364 {
1365 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1366 }
1367
1368 /**
1369 * @brief Set the counter value.
1370 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1371 * whether or not a timer instance supports a 32 bits counter.
1372 * @rmtoll CNT CNT LL_TIM_SetCounter
1373 * @param TIMx Timer instance
1374 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1375 * @retval None
1376 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1377 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1378 {
1379 WRITE_REG(TIMx->CNT, Counter);
1380 }
1381
1382 /**
1383 * @brief Get the counter value.
1384 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1385 * whether or not a timer instance supports a 32 bits counter.
1386 * @rmtoll CNT CNT LL_TIM_GetCounter
1387 * @param TIMx Timer instance
1388 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1389 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)1390 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1391 {
1392 return (uint32_t)(READ_REG(TIMx->CNT));
1393 }
1394
1395 /**
1396 * @brief Get the current direction of the counter
1397 * @rmtoll CR1 DIR LL_TIM_GetDirection
1398 * @param TIMx Timer instance
1399 * @retval Returned value can be one of the following values:
1400 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1401 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1402 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)1403 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1404 {
1405 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1406 }
1407
1408 /**
1409 * @brief Set the prescaler value.
1410 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1411 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1412 * prescaler ratio is taken into account at the next update event.
1413 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1414 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1415 * @param TIMx Timer instance
1416 * @param Prescaler between Min_Data=0 and Max_Data=65535
1417 * @retval None
1418 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1419 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1420 {
1421 WRITE_REG(TIMx->PSC, Prescaler);
1422 }
1423
1424 /**
1425 * @brief Get the prescaler value.
1426 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1427 * @param TIMx Timer instance
1428 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1429 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)1430 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1431 {
1432 return (uint32_t)(READ_REG(TIMx->PSC));
1433 }
1434
1435 /**
1436 * @brief Set the auto-reload value.
1437 * @note The counter is blocked while the auto-reload value is null.
1438 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1439 * whether or not a timer instance supports a 32 bits counter.
1440 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1441 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1442 * @param TIMx Timer instance
1443 * @param AutoReload between Min_Data=0 and Max_Data=65535
1444 * @retval None
1445 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1446 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1447 {
1448 WRITE_REG(TIMx->ARR, AutoReload);
1449 }
1450
1451 /**
1452 * @brief Get the auto-reload value.
1453 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1454 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1455 * whether or not a timer instance supports a 32 bits counter.
1456 * @param TIMx Timer instance
1457 * @retval Auto-reload value
1458 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)1459 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1460 {
1461 return (uint32_t)(READ_REG(TIMx->ARR));
1462 }
1463
1464 /**
1465 * @brief Set the repetition counter value.
1466 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1467 * whether or not a timer instance supports a repetition counter.
1468 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1469 * @param TIMx Timer instance
1470 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1471 * @retval None
1472 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1473 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1474 {
1475 WRITE_REG(TIMx->RCR, RepetitionCounter);
1476 }
1477
1478 /**
1479 * @brief Get the repetition counter value.
1480 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1481 * whether or not a timer instance supports a repetition counter.
1482 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1483 * @param TIMx Timer instance
1484 * @retval Repetition counter value
1485 */
LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)1486 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1487 {
1488 return (uint32_t)(READ_REG(TIMx->RCR));
1489 }
1490
1491 /**
1492 * @}
1493 */
1494
1495 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1496 * @{
1497 */
1498 /**
1499 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1500 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1501 * they are updated only when a commutation event (COM) occurs.
1502 * @note Only on channels that have a complementary output.
1503 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1504 * whether or not a timer instance is able to generate a commutation event.
1505 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1506 * @param TIMx Timer instance
1507 * @retval None
1508 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1509 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1510 {
1511 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1512 }
1513
1514 /**
1515 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1516 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1517 * whether or not a timer instance is able to generate a commutation event.
1518 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1519 * @param TIMx Timer instance
1520 * @retval None
1521 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1522 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1523 {
1524 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1525 }
1526
1527 /**
1528 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1529 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1530 * whether or not a timer instance is able to generate a commutation event.
1531 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1532 * @param TIMx Timer instance
1533 * @param CCUpdateSource This parameter can be one of the following values:
1534 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1535 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1536 * @retval None
1537 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1538 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1539 {
1540 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1541 }
1542
1543 /**
1544 * @brief Set the trigger of the capture/compare DMA request.
1545 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1546 * @param TIMx Timer instance
1547 * @param DMAReqTrigger This parameter can be one of the following values:
1548 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1549 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1550 * @retval None
1551 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1552 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1553 {
1554 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1555 }
1556
1557 /**
1558 * @brief Get actual trigger of the capture/compare DMA request.
1559 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1560 * @param TIMx Timer instance
1561 * @retval Returned value can be one of the following values:
1562 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1563 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1564 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)1565 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1566 {
1567 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1568 }
1569
1570 /**
1571 * @brief Set the lock level to freeze the
1572 * configuration of several capture/compare parameters.
1573 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1574 * the lock mechanism is supported by a timer instance.
1575 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1576 * @param TIMx Timer instance
1577 * @param LockLevel This parameter can be one of the following values:
1578 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1579 * @arg @ref LL_TIM_LOCKLEVEL_1
1580 * @arg @ref LL_TIM_LOCKLEVEL_2
1581 * @arg @ref LL_TIM_LOCKLEVEL_3
1582 * @retval None
1583 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1584 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1585 {
1586 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1587 }
1588
1589 /**
1590 * @brief Enable capture/compare channels.
1591 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1592 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1593 * CCER CC2E LL_TIM_CC_EnableChannel\n
1594 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1595 * CCER CC3E LL_TIM_CC_EnableChannel\n
1596 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1597 * CCER CC4E LL_TIM_CC_EnableChannel
1598 * @param TIMx Timer instance
1599 * @param Channels This parameter can be a combination of the following values:
1600 * @arg @ref LL_TIM_CHANNEL_CH1
1601 * @arg @ref LL_TIM_CHANNEL_CH1N
1602 * @arg @ref LL_TIM_CHANNEL_CH2
1603 * @arg @ref LL_TIM_CHANNEL_CH2N
1604 * @arg @ref LL_TIM_CHANNEL_CH3
1605 * @arg @ref LL_TIM_CHANNEL_CH3N
1606 * @arg @ref LL_TIM_CHANNEL_CH4
1607 * @retval None
1608 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1609 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1610 {
1611 SET_BIT(TIMx->CCER, Channels);
1612 }
1613
1614 /**
1615 * @brief Disable capture/compare channels.
1616 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1617 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1618 * CCER CC2E LL_TIM_CC_DisableChannel\n
1619 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1620 * CCER CC3E LL_TIM_CC_DisableChannel\n
1621 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1622 * CCER CC4E LL_TIM_CC_DisableChannel
1623 * @param TIMx Timer instance
1624 * @param Channels This parameter can be a combination of the following values:
1625 * @arg @ref LL_TIM_CHANNEL_CH1
1626 * @arg @ref LL_TIM_CHANNEL_CH1N
1627 * @arg @ref LL_TIM_CHANNEL_CH2
1628 * @arg @ref LL_TIM_CHANNEL_CH2N
1629 * @arg @ref LL_TIM_CHANNEL_CH3
1630 * @arg @ref LL_TIM_CHANNEL_CH3N
1631 * @arg @ref LL_TIM_CHANNEL_CH4
1632 * @retval None
1633 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1634 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1635 {
1636 CLEAR_BIT(TIMx->CCER, Channels);
1637 }
1638
1639 /**
1640 * @brief Indicate whether channel(s) is(are) enabled.
1641 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1642 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1643 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1644 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1645 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1646 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1647 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1648 * @param TIMx Timer instance
1649 * @param Channels This parameter can be a combination of the following values:
1650 * @arg @ref LL_TIM_CHANNEL_CH1
1651 * @arg @ref LL_TIM_CHANNEL_CH1N
1652 * @arg @ref LL_TIM_CHANNEL_CH2
1653 * @arg @ref LL_TIM_CHANNEL_CH2N
1654 * @arg @ref LL_TIM_CHANNEL_CH3
1655 * @arg @ref LL_TIM_CHANNEL_CH3N
1656 * @arg @ref LL_TIM_CHANNEL_CH4
1657 * @retval State of bit (1 or 0).
1658 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1659 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1660 {
1661 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1662 }
1663
1664 /**
1665 * @}
1666 */
1667
1668 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1669 * @{
1670 */
1671 /**
1672 * @brief Configure an output channel.
1673 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1674 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1675 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1676 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1677 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1678 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1679 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1680 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1681 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1682 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1683 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1684 * CR2 OIS4 LL_TIM_OC_ConfigOutput
1685 * @param TIMx Timer instance
1686 * @param Channel This parameter can be one of the following values:
1687 * @arg @ref LL_TIM_CHANNEL_CH1
1688 * @arg @ref LL_TIM_CHANNEL_CH2
1689 * @arg @ref LL_TIM_CHANNEL_CH3
1690 * @arg @ref LL_TIM_CHANNEL_CH4
1691 * @param Configuration This parameter must be a combination of all the following values:
1692 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1693 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1694 * @retval None
1695 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1696 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1697 {
1698 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1699 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1700 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1701 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1702 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1703 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1704 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1705 }
1706
1707 /**
1708 * @brief Define the behavior of the output reference signal OCxREF from which
1709 * OCx and OCxN (when relevant) are derived.
1710 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1711 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1712 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1713 * CCMR2 OC4M LL_TIM_OC_SetMode
1714 * @param TIMx Timer instance
1715 * @param Channel This parameter can be one of the following values:
1716 * @arg @ref LL_TIM_CHANNEL_CH1
1717 * @arg @ref LL_TIM_CHANNEL_CH2
1718 * @arg @ref LL_TIM_CHANNEL_CH3
1719 * @arg @ref LL_TIM_CHANNEL_CH4
1720 * @param Mode This parameter can be one of the following values:
1721 * @arg @ref LL_TIM_OCMODE_FROZEN
1722 * @arg @ref LL_TIM_OCMODE_ACTIVE
1723 * @arg @ref LL_TIM_OCMODE_INACTIVE
1724 * @arg @ref LL_TIM_OCMODE_TOGGLE
1725 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1726 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1727 * @arg @ref LL_TIM_OCMODE_PWM1
1728 * @arg @ref LL_TIM_OCMODE_PWM2
1729 * @retval None
1730 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1731 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1732 {
1733 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1734 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1735 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1736 }
1737
1738 /**
1739 * @brief Get the output compare mode of an output channel.
1740 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1741 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1742 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1743 * CCMR2 OC4M LL_TIM_OC_GetMode
1744 * @param TIMx Timer instance
1745 * @param Channel This parameter can be one of the following values:
1746 * @arg @ref LL_TIM_CHANNEL_CH1
1747 * @arg @ref LL_TIM_CHANNEL_CH2
1748 * @arg @ref LL_TIM_CHANNEL_CH3
1749 * @arg @ref LL_TIM_CHANNEL_CH4
1750 * @retval Returned value can be one of the following values:
1751 * @arg @ref LL_TIM_OCMODE_FROZEN
1752 * @arg @ref LL_TIM_OCMODE_ACTIVE
1753 * @arg @ref LL_TIM_OCMODE_INACTIVE
1754 * @arg @ref LL_TIM_OCMODE_TOGGLE
1755 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1756 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1757 * @arg @ref LL_TIM_OCMODE_PWM1
1758 * @arg @ref LL_TIM_OCMODE_PWM2
1759 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)1760 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
1761 {
1762 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1763 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1764 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1765 }
1766
1767 /**
1768 * @brief Set the polarity of an output channel.
1769 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1770 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1771 * CCER CC2P LL_TIM_OC_SetPolarity\n
1772 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1773 * CCER CC3P LL_TIM_OC_SetPolarity\n
1774 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1775 * CCER CC4P LL_TIM_OC_SetPolarity
1776 * @param TIMx Timer instance
1777 * @param Channel This parameter can be one of the following values:
1778 * @arg @ref LL_TIM_CHANNEL_CH1
1779 * @arg @ref LL_TIM_CHANNEL_CH1N
1780 * @arg @ref LL_TIM_CHANNEL_CH2
1781 * @arg @ref LL_TIM_CHANNEL_CH2N
1782 * @arg @ref LL_TIM_CHANNEL_CH3
1783 * @arg @ref LL_TIM_CHANNEL_CH3N
1784 * @arg @ref LL_TIM_CHANNEL_CH4
1785 * @param Polarity This parameter can be one of the following values:
1786 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1787 * @arg @ref LL_TIM_OCPOLARITY_LOW
1788 * @retval None
1789 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1790 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1791 {
1792 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1793 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1794 }
1795
1796 /**
1797 * @brief Get the polarity of an output channel.
1798 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1799 * CCER CC1NP LL_TIM_OC_GetPolarity\n
1800 * CCER CC2P LL_TIM_OC_GetPolarity\n
1801 * CCER CC2NP LL_TIM_OC_GetPolarity\n
1802 * CCER CC3P LL_TIM_OC_GetPolarity\n
1803 * CCER CC3NP LL_TIM_OC_GetPolarity\n
1804 * CCER CC4P LL_TIM_OC_GetPolarity
1805 * @param TIMx Timer instance
1806 * @param Channel This parameter can be one of the following values:
1807 * @arg @ref LL_TIM_CHANNEL_CH1
1808 * @arg @ref LL_TIM_CHANNEL_CH1N
1809 * @arg @ref LL_TIM_CHANNEL_CH2
1810 * @arg @ref LL_TIM_CHANNEL_CH2N
1811 * @arg @ref LL_TIM_CHANNEL_CH3
1812 * @arg @ref LL_TIM_CHANNEL_CH3N
1813 * @arg @ref LL_TIM_CHANNEL_CH4
1814 * @retval Returned value can be one of the following values:
1815 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1816 * @arg @ref LL_TIM_OCPOLARITY_LOW
1817 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)1818 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
1819 {
1820 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1821 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1822 }
1823
1824 /**
1825 * @brief Set the IDLE state of an output channel
1826 * @note This function is significant only for the timer instances
1827 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
1828 * can be used to check whether or not a timer instance provides
1829 * a break input.
1830 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1831 * CR2 OIS1N LL_TIM_OC_SetIdleState\n
1832 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
1833 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
1834 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
1835 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
1836 * CR2 OIS4 LL_TIM_OC_SetIdleState
1837 * @param TIMx Timer instance
1838 * @param Channel This parameter can be one of the following values:
1839 * @arg @ref LL_TIM_CHANNEL_CH1
1840 * @arg @ref LL_TIM_CHANNEL_CH1N
1841 * @arg @ref LL_TIM_CHANNEL_CH2
1842 * @arg @ref LL_TIM_CHANNEL_CH2N
1843 * @arg @ref LL_TIM_CHANNEL_CH3
1844 * @arg @ref LL_TIM_CHANNEL_CH3N
1845 * @arg @ref LL_TIM_CHANNEL_CH4
1846 * @param IdleState This parameter can be one of the following values:
1847 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1848 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1849 * @retval None
1850 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)1851 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1852 {
1853 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1854 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1855 }
1856
1857 /**
1858 * @brief Get the IDLE state of an output channel
1859 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1860 * CR2 OIS1N LL_TIM_OC_GetIdleState\n
1861 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
1862 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
1863 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
1864 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
1865 * CR2 OIS4 LL_TIM_OC_GetIdleState
1866 * @param TIMx Timer instance
1867 * @param Channel This parameter can be one of the following values:
1868 * @arg @ref LL_TIM_CHANNEL_CH1
1869 * @arg @ref LL_TIM_CHANNEL_CH1N
1870 * @arg @ref LL_TIM_CHANNEL_CH2
1871 * @arg @ref LL_TIM_CHANNEL_CH2N
1872 * @arg @ref LL_TIM_CHANNEL_CH3
1873 * @arg @ref LL_TIM_CHANNEL_CH3N
1874 * @arg @ref LL_TIM_CHANNEL_CH4
1875 * @retval Returned value can be one of the following values:
1876 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1877 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1878 */
LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx,uint32_t Channel)1879 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
1880 {
1881 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1882 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1883 }
1884
1885 /**
1886 * @brief Enable fast mode for the output channel.
1887 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1888 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1889 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1890 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1891 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1892 * @param TIMx Timer instance
1893 * @param Channel This parameter can be one of the following values:
1894 * @arg @ref LL_TIM_CHANNEL_CH1
1895 * @arg @ref LL_TIM_CHANNEL_CH2
1896 * @arg @ref LL_TIM_CHANNEL_CH3
1897 * @arg @ref LL_TIM_CHANNEL_CH4
1898 * @retval None
1899 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1900 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1901 {
1902 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1903 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1904 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1905
1906 }
1907
1908 /**
1909 * @brief Disable fast mode for the output channel.
1910 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1911 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1912 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1913 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1914 * @param TIMx Timer instance
1915 * @param Channel This parameter can be one of the following values:
1916 * @arg @ref LL_TIM_CHANNEL_CH1
1917 * @arg @ref LL_TIM_CHANNEL_CH2
1918 * @arg @ref LL_TIM_CHANNEL_CH3
1919 * @arg @ref LL_TIM_CHANNEL_CH4
1920 * @retval None
1921 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1922 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1923 {
1924 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1925 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1926 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1927
1928 }
1929
1930 /**
1931 * @brief Indicates whether fast mode is enabled for the output channel.
1932 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1933 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1934 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1935 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1936 * @param TIMx Timer instance
1937 * @param Channel This parameter can be one of the following values:
1938 * @arg @ref LL_TIM_CHANNEL_CH1
1939 * @arg @ref LL_TIM_CHANNEL_CH2
1940 * @arg @ref LL_TIM_CHANNEL_CH3
1941 * @arg @ref LL_TIM_CHANNEL_CH4
1942 * @retval State of bit (1 or 0).
1943 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)1944 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
1945 {
1946 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1947 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1948 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1949 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1950 }
1951
1952 /**
1953 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1954 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1955 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1956 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1957 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1958 * @param TIMx Timer instance
1959 * @param Channel This parameter can be one of the following values:
1960 * @arg @ref LL_TIM_CHANNEL_CH1
1961 * @arg @ref LL_TIM_CHANNEL_CH2
1962 * @arg @ref LL_TIM_CHANNEL_CH3
1963 * @arg @ref LL_TIM_CHANNEL_CH4
1964 * @retval None
1965 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1966 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1967 {
1968 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1969 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1970 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1971 }
1972
1973 /**
1974 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1975 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1976 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1977 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1978 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1979 * @param TIMx Timer instance
1980 * @param Channel This parameter can be one of the following values:
1981 * @arg @ref LL_TIM_CHANNEL_CH1
1982 * @arg @ref LL_TIM_CHANNEL_CH2
1983 * @arg @ref LL_TIM_CHANNEL_CH3
1984 * @arg @ref LL_TIM_CHANNEL_CH4
1985 * @retval None
1986 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1987 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1988 {
1989 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1990 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1991 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1992 }
1993
1994 /**
1995 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1996 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1997 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1998 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1999 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2000 * @param TIMx Timer instance
2001 * @param Channel This parameter can be one of the following values:
2002 * @arg @ref LL_TIM_CHANNEL_CH1
2003 * @arg @ref LL_TIM_CHANNEL_CH2
2004 * @arg @ref LL_TIM_CHANNEL_CH3
2005 * @arg @ref LL_TIM_CHANNEL_CH4
2006 * @retval State of bit (1 or 0).
2007 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2008 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2009 {
2010 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2011 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2012 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2013 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2014 }
2015
2016 /**
2017 * @brief Enable clearing the output channel on an external event.
2018 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2019 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2020 * or not a timer instance can clear the OCxREF signal on an external event.
2021 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2022 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2023 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2024 * CCMR2 OC4CE LL_TIM_OC_EnableClear
2025 * @param TIMx Timer instance
2026 * @param Channel This parameter can be one of the following values:
2027 * @arg @ref LL_TIM_CHANNEL_CH1
2028 * @arg @ref LL_TIM_CHANNEL_CH2
2029 * @arg @ref LL_TIM_CHANNEL_CH3
2030 * @arg @ref LL_TIM_CHANNEL_CH4
2031 * @retval None
2032 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2033 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2034 {
2035 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2036 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2037 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2038 }
2039
2040 /**
2041 * @brief Disable clearing the output channel on an external event.
2042 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2043 * or not a timer instance can clear the OCxREF signal on an external event.
2044 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2045 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2046 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2047 * CCMR2 OC4CE LL_TIM_OC_DisableClear
2048 * @param TIMx Timer instance
2049 * @param Channel This parameter can be one of the following values:
2050 * @arg @ref LL_TIM_CHANNEL_CH1
2051 * @arg @ref LL_TIM_CHANNEL_CH2
2052 * @arg @ref LL_TIM_CHANNEL_CH3
2053 * @arg @ref LL_TIM_CHANNEL_CH4
2054 * @retval None
2055 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2056 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2057 {
2058 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2059 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2060 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2061 }
2062
2063 /**
2064 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2065 * @note This function enables clearing the output channel on an external event.
2066 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2067 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2068 * or not a timer instance can clear the OCxREF signal on an external event.
2069 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2070 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2071 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2072 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2073 * @param TIMx Timer instance
2074 * @param Channel This parameter can be one of the following values:
2075 * @arg @ref LL_TIM_CHANNEL_CH1
2076 * @arg @ref LL_TIM_CHANNEL_CH2
2077 * @arg @ref LL_TIM_CHANNEL_CH3
2078 * @arg @ref LL_TIM_CHANNEL_CH4
2079 * @retval State of bit (1 or 0).
2080 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2081 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2082 {
2083 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2084 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2085 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2086 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2087 }
2088
2089 /**
2090 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2091 * the Ocx and OCxN signals).
2092 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2093 * dead-time insertion feature is supported by a timer instance.
2094 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2095 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2096 * @param TIMx Timer instance
2097 * @param DeadTime between Min_Data=0 and Max_Data=255
2098 * @retval None
2099 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2100 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2101 {
2102 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2103 }
2104
2105 /**
2106 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2107 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2108 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2109 * whether or not a timer instance supports a 32 bits counter.
2110 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2111 * output channel 1 is supported by a timer instance.
2112 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2113 * @param TIMx Timer instance
2114 * @param CompareValue between Min_Data=0 and Max_Data=65535
2115 * @retval None
2116 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2117 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2118 {
2119 WRITE_REG(TIMx->CCR1, CompareValue);
2120 }
2121
2122 /**
2123 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2124 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2125 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2126 * whether or not a timer instance supports a 32 bits counter.
2127 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2128 * output channel 2 is supported by a timer instance.
2129 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2130 * @param TIMx Timer instance
2131 * @param CompareValue between Min_Data=0 and Max_Data=65535
2132 * @retval None
2133 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2134 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2135 {
2136 WRITE_REG(TIMx->CCR2, CompareValue);
2137 }
2138
2139 /**
2140 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2141 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2142 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2143 * whether or not a timer instance supports a 32 bits counter.
2144 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2145 * output channel is supported by a timer instance.
2146 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2147 * @param TIMx Timer instance
2148 * @param CompareValue between Min_Data=0 and Max_Data=65535
2149 * @retval None
2150 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2151 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2152 {
2153 WRITE_REG(TIMx->CCR3, CompareValue);
2154 }
2155
2156 /**
2157 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2158 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2159 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2160 * whether or not a timer instance supports a 32 bits counter.
2161 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2162 * output channel 4 is supported by a timer instance.
2163 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2164 * @param TIMx Timer instance
2165 * @param CompareValue between Min_Data=0 and Max_Data=65535
2166 * @retval None
2167 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2168 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2169 {
2170 WRITE_REG(TIMx->CCR4, CompareValue);
2171 }
2172
2173 /**
2174 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2175 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2176 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2177 * whether or not a timer instance supports a 32 bits counter.
2178 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2179 * output channel 1 is supported by a timer instance.
2180 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2181 * @param TIMx Timer instance
2182 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2183 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)2184 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2185 {
2186 return (uint32_t)(READ_REG(TIMx->CCR1));
2187 }
2188
2189 /**
2190 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2191 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2192 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2193 * whether or not a timer instance supports a 32 bits counter.
2194 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2195 * output channel 2 is supported by a timer instance.
2196 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2197 * @param TIMx Timer instance
2198 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2199 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)2200 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2201 {
2202 return (uint32_t)(READ_REG(TIMx->CCR2));
2203 }
2204
2205 /**
2206 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2207 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2208 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2209 * whether or not a timer instance supports a 32 bits counter.
2210 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2211 * output channel 3 is supported by a timer instance.
2212 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2213 * @param TIMx Timer instance
2214 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2215 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)2216 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2217 {
2218 return (uint32_t)(READ_REG(TIMx->CCR3));
2219 }
2220
2221 /**
2222 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2223 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2224 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2225 * whether or not a timer instance supports a 32 bits counter.
2226 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2227 * output channel 4 is supported by a timer instance.
2228 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2229 * @param TIMx Timer instance
2230 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2231 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)2232 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2233 {
2234 return (uint32_t)(READ_REG(TIMx->CCR4));
2235 }
2236
2237 /**
2238 * @}
2239 */
2240
2241 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2242 * @{
2243 */
2244 /**
2245 * @brief Configure input channel.
2246 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2247 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2248 * CCMR1 IC1F LL_TIM_IC_Config\n
2249 * CCMR1 CC2S LL_TIM_IC_Config\n
2250 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2251 * CCMR1 IC2F LL_TIM_IC_Config\n
2252 * CCMR2 CC3S LL_TIM_IC_Config\n
2253 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2254 * CCMR2 IC3F LL_TIM_IC_Config\n
2255 * CCMR2 CC4S LL_TIM_IC_Config\n
2256 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2257 * CCMR2 IC4F LL_TIM_IC_Config\n
2258 * CCER CC1P LL_TIM_IC_Config\n
2259 * CCER CC1NP LL_TIM_IC_Config\n
2260 * CCER CC2P LL_TIM_IC_Config\n
2261 * CCER CC2NP LL_TIM_IC_Config\n
2262 * CCER CC3P LL_TIM_IC_Config\n
2263 * CCER CC3NP LL_TIM_IC_Config\n
2264 * CCER CC4P LL_TIM_IC_Config\n
2265 * CCER CC4NP LL_TIM_IC_Config
2266 * @param TIMx Timer instance
2267 * @param Channel This parameter can be one of the following values:
2268 * @arg @ref LL_TIM_CHANNEL_CH1
2269 * @arg @ref LL_TIM_CHANNEL_CH2
2270 * @arg @ref LL_TIM_CHANNEL_CH3
2271 * @arg @ref LL_TIM_CHANNEL_CH4
2272 * @param Configuration This parameter must be a combination of all the following values:
2273 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2274 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2275 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2276 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2277 * @retval None
2278 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2279 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2280 {
2281 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2282 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2283 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2284 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2285 << SHIFT_TAB_ICxx[iChannel]);
2286 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2287 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2288 }
2289
2290 /**
2291 * @brief Set the active input.
2292 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2293 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2294 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2295 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2296 * @param TIMx Timer instance
2297 * @param Channel This parameter can be one of the following values:
2298 * @arg @ref LL_TIM_CHANNEL_CH1
2299 * @arg @ref LL_TIM_CHANNEL_CH2
2300 * @arg @ref LL_TIM_CHANNEL_CH3
2301 * @arg @ref LL_TIM_CHANNEL_CH4
2302 * @param ICActiveInput This parameter can be one of the following values:
2303 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2304 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2305 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2306 * @retval None
2307 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2308 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2309 {
2310 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2311 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2312 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2313 }
2314
2315 /**
2316 * @brief Get the current active input.
2317 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2318 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2319 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2320 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2321 * @param TIMx Timer instance
2322 * @param Channel This parameter can be one of the following values:
2323 * @arg @ref LL_TIM_CHANNEL_CH1
2324 * @arg @ref LL_TIM_CHANNEL_CH2
2325 * @arg @ref LL_TIM_CHANNEL_CH3
2326 * @arg @ref LL_TIM_CHANNEL_CH4
2327 * @retval Returned value can be one of the following values:
2328 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2329 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2330 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2331 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)2332 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2333 {
2334 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2335 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2336 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2337 }
2338
2339 /**
2340 * @brief Set the prescaler of input channel.
2341 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2342 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2343 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2344 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2345 * @param TIMx Timer instance
2346 * @param Channel This parameter can be one of the following values:
2347 * @arg @ref LL_TIM_CHANNEL_CH1
2348 * @arg @ref LL_TIM_CHANNEL_CH2
2349 * @arg @ref LL_TIM_CHANNEL_CH3
2350 * @arg @ref LL_TIM_CHANNEL_CH4
2351 * @param ICPrescaler This parameter can be one of the following values:
2352 * @arg @ref LL_TIM_ICPSC_DIV1
2353 * @arg @ref LL_TIM_ICPSC_DIV2
2354 * @arg @ref LL_TIM_ICPSC_DIV4
2355 * @arg @ref LL_TIM_ICPSC_DIV8
2356 * @retval None
2357 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2358 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2359 {
2360 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2361 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2362 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2363 }
2364
2365 /**
2366 * @brief Get the current prescaler value acting on an input channel.
2367 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2368 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2369 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2370 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2371 * @param TIMx Timer instance
2372 * @param Channel This parameter can be one of the following values:
2373 * @arg @ref LL_TIM_CHANNEL_CH1
2374 * @arg @ref LL_TIM_CHANNEL_CH2
2375 * @arg @ref LL_TIM_CHANNEL_CH3
2376 * @arg @ref LL_TIM_CHANNEL_CH4
2377 * @retval Returned value can be one of the following values:
2378 * @arg @ref LL_TIM_ICPSC_DIV1
2379 * @arg @ref LL_TIM_ICPSC_DIV2
2380 * @arg @ref LL_TIM_ICPSC_DIV4
2381 * @arg @ref LL_TIM_ICPSC_DIV8
2382 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)2383 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2384 {
2385 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2386 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2387 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2388 }
2389
2390 /**
2391 * @brief Set the input filter duration.
2392 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2393 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2394 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2395 * CCMR2 IC4F LL_TIM_IC_SetFilter
2396 * @param TIMx Timer instance
2397 * @param Channel This parameter can be one of the following values:
2398 * @arg @ref LL_TIM_CHANNEL_CH1
2399 * @arg @ref LL_TIM_CHANNEL_CH2
2400 * @arg @ref LL_TIM_CHANNEL_CH3
2401 * @arg @ref LL_TIM_CHANNEL_CH4
2402 * @param ICFilter This parameter can be one of the following values:
2403 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2404 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2405 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2406 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2407 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2408 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2409 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2410 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2411 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2412 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2413 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2414 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2415 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2416 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2417 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2418 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2419 * @retval None
2420 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2421 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2422 {
2423 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2424 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2425 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2426 }
2427
2428 /**
2429 * @brief Get the input filter duration.
2430 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2431 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2432 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2433 * CCMR2 IC4F LL_TIM_IC_GetFilter
2434 * @param TIMx Timer instance
2435 * @param Channel This parameter can be one of the following values:
2436 * @arg @ref LL_TIM_CHANNEL_CH1
2437 * @arg @ref LL_TIM_CHANNEL_CH2
2438 * @arg @ref LL_TIM_CHANNEL_CH3
2439 * @arg @ref LL_TIM_CHANNEL_CH4
2440 * @retval Returned value can be one of the following values:
2441 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2442 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2443 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2444 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2445 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2446 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2447 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2448 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2449 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2450 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2451 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2452 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2453 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2454 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2455 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2456 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2457 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)2458 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2459 {
2460 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2461 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2462 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2463 }
2464
2465 /**
2466 * @brief Set the input channel polarity.
2467 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2468 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2469 * CCER CC2P LL_TIM_IC_SetPolarity\n
2470 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2471 * CCER CC3P LL_TIM_IC_SetPolarity\n
2472 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2473 * CCER CC4P LL_TIM_IC_SetPolarity\n
2474 * CCER CC4NP LL_TIM_IC_SetPolarity
2475 * @param TIMx Timer instance
2476 * @param Channel This parameter can be one of the following values:
2477 * @arg @ref LL_TIM_CHANNEL_CH1
2478 * @arg @ref LL_TIM_CHANNEL_CH2
2479 * @arg @ref LL_TIM_CHANNEL_CH3
2480 * @arg @ref LL_TIM_CHANNEL_CH4
2481 * @param ICPolarity This parameter can be one of the following values:
2482 * @arg @ref LL_TIM_IC_POLARITY_RISING
2483 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2484 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2485 * @retval None
2486 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2487 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2488 {
2489 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2490 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2491 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2492 }
2493
2494 /**
2495 * @brief Get the current input channel polarity.
2496 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2497 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2498 * CCER CC2P LL_TIM_IC_GetPolarity\n
2499 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2500 * CCER CC3P LL_TIM_IC_GetPolarity\n
2501 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2502 * CCER CC4P LL_TIM_IC_GetPolarity\n
2503 * CCER CC4NP LL_TIM_IC_GetPolarity
2504 * @param TIMx Timer instance
2505 * @param Channel This parameter can be one of the following values:
2506 * @arg @ref LL_TIM_CHANNEL_CH1
2507 * @arg @ref LL_TIM_CHANNEL_CH2
2508 * @arg @ref LL_TIM_CHANNEL_CH3
2509 * @arg @ref LL_TIM_CHANNEL_CH4
2510 * @retval Returned value can be one of the following values:
2511 * @arg @ref LL_TIM_IC_POLARITY_RISING
2512 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2513 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2514 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2515 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2516 {
2517 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2518 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2519 SHIFT_TAB_CCxP[iChannel]);
2520 }
2521
2522 /**
2523 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2524 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2525 * a timer instance provides an XOR input.
2526 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2527 * @param TIMx Timer instance
2528 * @retval None
2529 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2530 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2531 {
2532 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2533 }
2534
2535 /**
2536 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2537 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2538 * a timer instance provides an XOR input.
2539 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2540 * @param TIMx Timer instance
2541 * @retval None
2542 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2543 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2544 {
2545 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2546 }
2547
2548 /**
2549 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2550 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2551 * a timer instance provides an XOR input.
2552 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2553 * @param TIMx Timer instance
2554 * @retval State of bit (1 or 0).
2555 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)2556 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
2557 {
2558 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2559 }
2560
2561 /**
2562 * @brief Get captured value for input channel 1.
2563 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2564 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2565 * whether or not a timer instance supports a 32 bits counter.
2566 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2567 * input channel 1 is supported by a timer instance.
2568 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2569 * @param TIMx Timer instance
2570 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2571 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)2572 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
2573 {
2574 return (uint32_t)(READ_REG(TIMx->CCR1));
2575 }
2576
2577 /**
2578 * @brief Get captured value for input channel 2.
2579 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2580 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2581 * whether or not a timer instance supports a 32 bits counter.
2582 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2583 * input channel 2 is supported by a timer instance.
2584 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2585 * @param TIMx Timer instance
2586 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2587 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)2588 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
2589 {
2590 return (uint32_t)(READ_REG(TIMx->CCR2));
2591 }
2592
2593 /**
2594 * @brief Get captured value for input channel 3.
2595 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2596 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2597 * whether or not a timer instance supports a 32 bits counter.
2598 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2599 * input channel 3 is supported by a timer instance.
2600 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2601 * @param TIMx Timer instance
2602 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2603 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)2604 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
2605 {
2606 return (uint32_t)(READ_REG(TIMx->CCR3));
2607 }
2608
2609 /**
2610 * @brief Get captured value for input channel 4.
2611 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2612 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2613 * whether or not a timer instance supports a 32 bits counter.
2614 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2615 * input channel 4 is supported by a timer instance.
2616 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2617 * @param TIMx Timer instance
2618 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2619 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)2620 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
2621 {
2622 return (uint32_t)(READ_REG(TIMx->CCR4));
2623 }
2624
2625 /**
2626 * @}
2627 */
2628
2629 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2630 * @{
2631 */
2632 /**
2633 * @brief Enable external clock mode 2.
2634 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2635 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2636 * whether or not a timer instance supports external clock mode2.
2637 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2638 * @param TIMx Timer instance
2639 * @retval None
2640 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2641 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2642 {
2643 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2644 }
2645
2646 /**
2647 * @brief Disable external clock mode 2.
2648 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2649 * whether or not a timer instance supports external clock mode2.
2650 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2651 * @param TIMx Timer instance
2652 * @retval None
2653 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2654 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2655 {
2656 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2657 }
2658
2659 /**
2660 * @brief Indicate whether external clock mode 2 is enabled.
2661 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2662 * whether or not a timer instance supports external clock mode2.
2663 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2664 * @param TIMx Timer instance
2665 * @retval State of bit (1 or 0).
2666 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)2667 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
2668 {
2669 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2670 }
2671
2672 /**
2673 * @brief Set the clock source of the counter clock.
2674 * @note when selected clock source is external clock mode 1, the timer input
2675 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2676 * function. This timer input must be configured by calling
2677 * the @ref LL_TIM_IC_Config() function.
2678 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2679 * whether or not a timer instance supports external clock mode1.
2680 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2681 * whether or not a timer instance supports external clock mode2.
2682 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2683 * SMCR ECE LL_TIM_SetClockSource
2684 * @param TIMx Timer instance
2685 * @param ClockSource This parameter can be one of the following values:
2686 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2687 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2688 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2689 * @retval None
2690 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2691 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2692 {
2693 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2694 }
2695
2696 /**
2697 * @brief Set the encoder interface mode.
2698 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2699 * whether or not a timer instance supports the encoder mode.
2700 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2701 * @param TIMx Timer instance
2702 * @param EncoderMode This parameter can be one of the following values:
2703 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2704 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2705 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2706 * @retval None
2707 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2708 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2709 {
2710 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2711 }
2712
2713 /**
2714 * @}
2715 */
2716
2717 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2718 * @{
2719 */
2720 /**
2721 * @brief Set the trigger output (TRGO) used for timer synchronization .
2722 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2723 * whether or not a timer instance can operate as a master timer.
2724 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2725 * @param TIMx Timer instance
2726 * @param TimerSynchronization This parameter can be one of the following values:
2727 * @arg @ref LL_TIM_TRGO_RESET
2728 * @arg @ref LL_TIM_TRGO_ENABLE
2729 * @arg @ref LL_TIM_TRGO_UPDATE
2730 * @arg @ref LL_TIM_TRGO_CC1IF
2731 * @arg @ref LL_TIM_TRGO_OC1REF
2732 * @arg @ref LL_TIM_TRGO_OC2REF
2733 * @arg @ref LL_TIM_TRGO_OC3REF
2734 * @arg @ref LL_TIM_TRGO_OC4REF
2735 * @retval None
2736 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2737 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2738 {
2739 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2740 }
2741
2742 /**
2743 * @brief Set the synchronization mode of a slave timer.
2744 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2745 * a timer instance can operate as a slave timer.
2746 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2747 * @param TIMx Timer instance
2748 * @param SlaveMode This parameter can be one of the following values:
2749 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2750 * @arg @ref LL_TIM_SLAVEMODE_RESET
2751 * @arg @ref LL_TIM_SLAVEMODE_GATED
2752 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2753 * @retval None
2754 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2755 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2756 {
2757 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2758 }
2759
2760 /**
2761 * @brief Set the selects the trigger input to be used to synchronize the counter.
2762 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2763 * a timer instance can operate as a slave timer.
2764 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2765 * @param TIMx Timer instance
2766 * @param TriggerInput This parameter can be one of the following values:
2767 * @arg @ref LL_TIM_TS_ITR0
2768 * @arg @ref LL_TIM_TS_ITR1
2769 * @arg @ref LL_TIM_TS_ITR2
2770 * @arg @ref LL_TIM_TS_ITR3
2771 * @arg @ref LL_TIM_TS_TI1F_ED
2772 * @arg @ref LL_TIM_TS_TI1FP1
2773 * @arg @ref LL_TIM_TS_TI2FP2
2774 * @arg @ref LL_TIM_TS_ETRF
2775 * @retval None
2776 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2777 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2778 {
2779 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2780 }
2781
2782 /**
2783 * @brief Enable the Master/Slave mode.
2784 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2785 * a timer instance can operate as a slave timer.
2786 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2787 * @param TIMx Timer instance
2788 * @retval None
2789 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2790 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2791 {
2792 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2793 }
2794
2795 /**
2796 * @brief Disable the Master/Slave mode.
2797 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2798 * a timer instance can operate as a slave timer.
2799 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2800 * @param TIMx Timer instance
2801 * @retval None
2802 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2803 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2804 {
2805 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2806 }
2807
2808 /**
2809 * @brief Indicates whether the Master/Slave mode is enabled.
2810 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2811 * a timer instance can operate as a slave timer.
2812 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2813 * @param TIMx Timer instance
2814 * @retval State of bit (1 or 0).
2815 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)2816 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
2817 {
2818 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2819 }
2820
2821 /**
2822 * @brief Configure the external trigger (ETR) input.
2823 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2824 * a timer instance provides an external trigger input.
2825 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2826 * SMCR ETPS LL_TIM_ConfigETR\n
2827 * SMCR ETF LL_TIM_ConfigETR
2828 * @param TIMx Timer instance
2829 * @param ETRPolarity This parameter can be one of the following values:
2830 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2831 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2832 * @param ETRPrescaler This parameter can be one of the following values:
2833 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2834 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2835 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2836 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2837 * @param ETRFilter This parameter can be one of the following values:
2838 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2839 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2840 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2841 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2842 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2843 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2844 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2845 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2846 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2847 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2848 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2849 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2850 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2851 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2852 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2853 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2854 * @retval None
2855 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2856 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2857 uint32_t ETRFilter)
2858 {
2859 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2860 }
2861
2862 /**
2863 * @}
2864 */
2865
2866 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
2867 * @{
2868 */
2869 /**
2870 * @brief Enable the break function.
2871 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2872 * a timer instance provides a break input.
2873 * @rmtoll BDTR BKE LL_TIM_EnableBRK
2874 * @param TIMx Timer instance
2875 * @retval None
2876 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)2877 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2878 {
2879 __IO uint32_t tmpreg;
2880 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2881 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2882 tmpreg = READ_REG(TIMx->BDTR);
2883 (void)(tmpreg);
2884 }
2885
2886 /**
2887 * @brief Disable the break function.
2888 * @rmtoll BDTR BKE LL_TIM_DisableBRK
2889 * @param TIMx Timer instance
2890 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2891 * a timer instance provides a break input.
2892 * @retval None
2893 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)2894 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2895 {
2896 __IO uint32_t tmpreg;
2897 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2898 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2899 tmpreg = READ_REG(TIMx->BDTR);
2900 (void)(tmpreg);
2901 }
2902
2903 /**
2904 * @brief Configure the break input.
2905 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2906 * a timer instance provides a break input.
2907 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
2908 * @param TIMx Timer instance
2909 * @param BreakPolarity This parameter can be one of the following values:
2910 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
2911 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2912 * @retval None
2913 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)2914 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2915 {
2916 __IO uint32_t tmpreg;
2917 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2918 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
2919 tmpreg = READ_REG(TIMx->BDTR);
2920 (void)(tmpreg);
2921 }
2922
2923 /**
2924 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2925 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2926 * a timer instance provides a break input.
2927 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2928 * BDTR OSSR LL_TIM_SetOffStates
2929 * @param TIMx Timer instance
2930 * @param OffStateIdle This parameter can be one of the following values:
2931 * @arg @ref LL_TIM_OSSI_DISABLE
2932 * @arg @ref LL_TIM_OSSI_ENABLE
2933 * @param OffStateRun This parameter can be one of the following values:
2934 * @arg @ref LL_TIM_OSSR_DISABLE
2935 * @arg @ref LL_TIM_OSSR_ENABLE
2936 * @retval None
2937 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)2938 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2939 {
2940 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
2941 }
2942
2943 /**
2944 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2945 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2946 * a timer instance provides a break input.
2947 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2948 * @param TIMx Timer instance
2949 * @retval None
2950 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)2951 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2952 {
2953 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2954 }
2955
2956 /**
2957 * @brief Disable automatic output (MOE can be set only by software).
2958 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2959 * a timer instance provides a break input.
2960 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2961 * @param TIMx Timer instance
2962 * @retval None
2963 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)2964 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2965 {
2966 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2967 }
2968
2969 /**
2970 * @brief Indicate whether automatic output is enabled.
2971 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2972 * a timer instance provides a break input.
2973 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2974 * @param TIMx Timer instance
2975 * @retval State of bit (1 or 0).
2976 */
LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)2977 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
2978 {
2979 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2980 }
2981
2982 /**
2983 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2984 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2985 * software and is reset in case of break or break2 event
2986 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2987 * a timer instance provides a break input.
2988 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2989 * @param TIMx Timer instance
2990 * @retval None
2991 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)2992 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2993 {
2994 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2995 }
2996
2997 /**
2998 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
2999 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3000 * software and is reset in case of break or break2 event.
3001 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3002 * a timer instance provides a break input.
3003 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3004 * @param TIMx Timer instance
3005 * @retval None
3006 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3007 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3008 {
3009 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3010 }
3011
3012 /**
3013 * @brief Indicates whether outputs are enabled.
3014 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3015 * a timer instance provides a break input.
3016 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3017 * @param TIMx Timer instance
3018 * @retval State of bit (1 or 0).
3019 */
LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)3020 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3021 {
3022 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3023 }
3024
3025 /**
3026 * @}
3027 */
3028
3029 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3030 * @{
3031 */
3032 /**
3033 * @brief Configures the timer DMA burst feature.
3034 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3035 * not a timer instance supports the DMA burst mode.
3036 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3037 * DCR DBA LL_TIM_ConfigDMABurst
3038 * @param TIMx Timer instance
3039 * @param DMABurstBaseAddress This parameter can be one of the following values:
3040 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3041 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3042 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3043 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3044 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3045 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3046 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3047 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3048 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3049 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3050 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3051 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3052 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3053 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3054 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3055 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3056 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3057 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3058 * @param DMABurstLength This parameter can be one of the following values:
3059 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3060 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3061 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3062 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3063 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3064 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3065 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3066 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3067 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3068 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3069 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3070 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3071 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3072 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3073 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3074 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3075 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3076 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3077 * @retval None
3078 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3079 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3080 {
3081 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3082 }
3083
3084 /**
3085 * @}
3086 */
3087
3088 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3089 * @{
3090 */
3091 /**
3092 * @brief Remap TIM inputs (input channel, internal/external triggers).
3093 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3094 * a some timer inputs can be remapped.
3095 * @rmtoll TIM1_OR ITR2_RMP LL_TIM_SetRemap\n
3096 * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3097 * TIM5_OR ITR1_RMP LL_TIM_SetRemap\n
3098 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3099 * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
3100 * TIM11_OR TI1_RMP LL_TIM_SetRemap\n
3101 * LPTIM1_OR OR LL_TIM_SetRemap
3102 * @param TIMx Timer instance
3103 * @param Remap Remap param depends on the TIMx. Description available only
3104 * in CHM version of the User Manual (not in .pdf).
3105 * Otherwise see Reference Manual description of OR registers.
3106 *
3107 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3108 *
3109 * TIM1: one of the following values
3110 *
3111 * ITR2_RMP can be one of the following values
3112 * @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*)
3113 * @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*)
3114 *
3115 * TIM2: one of the following values
3116 *
3117 * ITR1_RMP can be one of the following values
3118 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3119 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3120 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3121 *
3122 * TIM5: one of the following values
3123 *
3124 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3125 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3126 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3127 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3128 * @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*)
3129 * @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*)
3130 *
3131 * TIM9: one of the following values
3132 *
3133 * ITR1_RMP can be one of the following values
3134 * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*)
3135 * @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*)
3136 *
3137 * TIM11: one of the following values
3138 *
3139 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3140 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*)
3141 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
3142 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
3143 * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*)
3144 *
3145 * (*) Value not defined in all devices. \n
3146 *
3147 * @retval None
3148 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3149 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3150 {
3151 #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
3152 if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK)
3153 {
3154 /* Connect TIMx internal trigger to LPTIM1 output */
3155 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);
3156 MODIFY_REG(LPTIM1->OR,
3157 (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),
3158 Remap & ~(LL_TIM_LPTIM_REMAP_MASK));
3159 }
3160 else
3161 {
3162 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3163 }
3164 #else
3165 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3166 #endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
3167 }
3168
3169 /**
3170 * @}
3171 */
3172
3173 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3174 * @{
3175 */
3176 /**
3177 * @brief Clear the update interrupt flag (UIF).
3178 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3179 * @param TIMx Timer instance
3180 * @retval None
3181 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3182 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3183 {
3184 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3185 }
3186
3187 /**
3188 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3189 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3190 * @param TIMx Timer instance
3191 * @retval State of bit (1 or 0).
3192 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)3193 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3194 {
3195 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3196 }
3197
3198 /**
3199 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3200 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3201 * @param TIMx Timer instance
3202 * @retval None
3203 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3204 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3205 {
3206 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3207 }
3208
3209 /**
3210 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3211 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3212 * @param TIMx Timer instance
3213 * @retval State of bit (1 or 0).
3214 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)3215 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3216 {
3217 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3218 }
3219
3220 /**
3221 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3222 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3223 * @param TIMx Timer instance
3224 * @retval None
3225 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3226 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3227 {
3228 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3229 }
3230
3231 /**
3232 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3233 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3234 * @param TIMx Timer instance
3235 * @retval State of bit (1 or 0).
3236 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)3237 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3238 {
3239 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3240 }
3241
3242 /**
3243 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3244 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3245 * @param TIMx Timer instance
3246 * @retval None
3247 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3248 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3249 {
3250 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3251 }
3252
3253 /**
3254 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3255 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3256 * @param TIMx Timer instance
3257 * @retval State of bit (1 or 0).
3258 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)3259 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
3260 {
3261 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3262 }
3263
3264 /**
3265 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3266 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3267 * @param TIMx Timer instance
3268 * @retval None
3269 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3270 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3271 {
3272 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3273 }
3274
3275 /**
3276 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3277 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3278 * @param TIMx Timer instance
3279 * @retval State of bit (1 or 0).
3280 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)3281 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
3282 {
3283 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3284 }
3285
3286 /**
3287 * @brief Clear the commutation interrupt flag (COMIF).
3288 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3289 * @param TIMx Timer instance
3290 * @retval None
3291 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3292 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3293 {
3294 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3295 }
3296
3297 /**
3298 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3299 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3300 * @param TIMx Timer instance
3301 * @retval State of bit (1 or 0).
3302 */
LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)3303 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
3304 {
3305 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3306 }
3307
3308 /**
3309 * @brief Clear the trigger interrupt flag (TIF).
3310 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3311 * @param TIMx Timer instance
3312 * @retval None
3313 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3314 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3315 {
3316 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3317 }
3318
3319 /**
3320 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3321 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3322 * @param TIMx Timer instance
3323 * @retval State of bit (1 or 0).
3324 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)3325 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
3326 {
3327 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3328 }
3329
3330 /**
3331 * @brief Clear the break interrupt flag (BIF).
3332 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3333 * @param TIMx Timer instance
3334 * @retval None
3335 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3336 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3337 {
3338 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3339 }
3340
3341 /**
3342 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3343 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3344 * @param TIMx Timer instance
3345 * @retval State of bit (1 or 0).
3346 */
LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)3347 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
3348 {
3349 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3350 }
3351
3352 /**
3353 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3354 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3355 * @param TIMx Timer instance
3356 * @retval None
3357 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3358 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3359 {
3360 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3361 }
3362
3363 /**
3364 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3365 * (Capture/Compare 1 interrupt is pending).
3366 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3367 * @param TIMx Timer instance
3368 * @retval State of bit (1 or 0).
3369 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)3370 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
3371 {
3372 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3373 }
3374
3375 /**
3376 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3377 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3378 * @param TIMx Timer instance
3379 * @retval None
3380 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3381 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3382 {
3383 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3384 }
3385
3386 /**
3387 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3388 * (Capture/Compare 2 over-capture interrupt is pending).
3389 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3390 * @param TIMx Timer instance
3391 * @retval State of bit (1 or 0).
3392 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)3393 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
3394 {
3395 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3396 }
3397
3398 /**
3399 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3400 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3401 * @param TIMx Timer instance
3402 * @retval None
3403 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3404 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3405 {
3406 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3407 }
3408
3409 /**
3410 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
3411 * (Capture/Compare 3 over-capture interrupt is pending).
3412 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3413 * @param TIMx Timer instance
3414 * @retval State of bit (1 or 0).
3415 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)3416 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
3417 {
3418 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3419 }
3420
3421 /**
3422 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3423 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3424 * @param TIMx Timer instance
3425 * @retval None
3426 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3427 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3428 {
3429 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3430 }
3431
3432 /**
3433 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
3434 * (Capture/Compare 4 over-capture interrupt is pending).
3435 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3436 * @param TIMx Timer instance
3437 * @retval State of bit (1 or 0).
3438 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)3439 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
3440 {
3441 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3442 }
3443
3444 /**
3445 * @}
3446 */
3447
3448 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3449 * @{
3450 */
3451 /**
3452 * @brief Enable update interrupt (UIE).
3453 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3454 * @param TIMx Timer instance
3455 * @retval None
3456 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3457 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3458 {
3459 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3460 }
3461
3462 /**
3463 * @brief Disable update interrupt (UIE).
3464 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3465 * @param TIMx Timer instance
3466 * @retval None
3467 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3468 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3469 {
3470 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3471 }
3472
3473 /**
3474 * @brief Indicates whether the update interrupt (UIE) is enabled.
3475 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3476 * @param TIMx Timer instance
3477 * @retval State of bit (1 or 0).
3478 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)3479 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
3480 {
3481 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
3482 }
3483
3484 /**
3485 * @brief Enable capture/compare 1 interrupt (CC1IE).
3486 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3487 * @param TIMx Timer instance
3488 * @retval None
3489 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)3490 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3491 {
3492 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3493 }
3494
3495 /**
3496 * @brief Disable capture/compare 1 interrupt (CC1IE).
3497 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3498 * @param TIMx Timer instance
3499 * @retval None
3500 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)3501 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3502 {
3503 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3504 }
3505
3506 /**
3507 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3508 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3509 * @param TIMx Timer instance
3510 * @retval State of bit (1 or 0).
3511 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)3512 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
3513 {
3514 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
3515 }
3516
3517 /**
3518 * @brief Enable capture/compare 2 interrupt (CC2IE).
3519 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3520 * @param TIMx Timer instance
3521 * @retval None
3522 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)3523 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3524 {
3525 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3526 }
3527
3528 /**
3529 * @brief Disable capture/compare 2 interrupt (CC2IE).
3530 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3531 * @param TIMx Timer instance
3532 * @retval None
3533 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)3534 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3535 {
3536 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3537 }
3538
3539 /**
3540 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3541 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3542 * @param TIMx Timer instance
3543 * @retval State of bit (1 or 0).
3544 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)3545 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
3546 {
3547 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
3548 }
3549
3550 /**
3551 * @brief Enable capture/compare 3 interrupt (CC3IE).
3552 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3553 * @param TIMx Timer instance
3554 * @retval None
3555 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)3556 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3557 {
3558 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3559 }
3560
3561 /**
3562 * @brief Disable capture/compare 3 interrupt (CC3IE).
3563 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3564 * @param TIMx Timer instance
3565 * @retval None
3566 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)3567 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3568 {
3569 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3570 }
3571
3572 /**
3573 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3574 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3575 * @param TIMx Timer instance
3576 * @retval State of bit (1 or 0).
3577 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)3578 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
3579 {
3580 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
3581 }
3582
3583 /**
3584 * @brief Enable capture/compare 4 interrupt (CC4IE).
3585 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3586 * @param TIMx Timer instance
3587 * @retval None
3588 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)3589 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3590 {
3591 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3592 }
3593
3594 /**
3595 * @brief Disable capture/compare 4 interrupt (CC4IE).
3596 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3597 * @param TIMx Timer instance
3598 * @retval None
3599 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)3600 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3601 {
3602 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3603 }
3604
3605 /**
3606 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3607 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3608 * @param TIMx Timer instance
3609 * @retval State of bit (1 or 0).
3610 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)3611 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
3612 {
3613 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
3614 }
3615
3616 /**
3617 * @brief Enable commutation interrupt (COMIE).
3618 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3619 * @param TIMx Timer instance
3620 * @retval None
3621 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)3622 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3623 {
3624 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3625 }
3626
3627 /**
3628 * @brief Disable commutation interrupt (COMIE).
3629 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3630 * @param TIMx Timer instance
3631 * @retval None
3632 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)3633 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3634 {
3635 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3636 }
3637
3638 /**
3639 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3640 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3641 * @param TIMx Timer instance
3642 * @retval State of bit (1 or 0).
3643 */
LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)3644 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
3645 {
3646 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
3647 }
3648
3649 /**
3650 * @brief Enable trigger interrupt (TIE).
3651 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3652 * @param TIMx Timer instance
3653 * @retval None
3654 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)3655 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3656 {
3657 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3658 }
3659
3660 /**
3661 * @brief Disable trigger interrupt (TIE).
3662 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3663 * @param TIMx Timer instance
3664 * @retval None
3665 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)3666 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3667 {
3668 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3669 }
3670
3671 /**
3672 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3673 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3674 * @param TIMx Timer instance
3675 * @retval State of bit (1 or 0).
3676 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)3677 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
3678 {
3679 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
3680 }
3681
3682 /**
3683 * @brief Enable break interrupt (BIE).
3684 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3685 * @param TIMx Timer instance
3686 * @retval None
3687 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)3688 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3689 {
3690 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3691 }
3692
3693 /**
3694 * @brief Disable break interrupt (BIE).
3695 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3696 * @param TIMx Timer instance
3697 * @retval None
3698 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)3699 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3700 {
3701 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3702 }
3703
3704 /**
3705 * @brief Indicates whether the break interrupt (BIE) is enabled.
3706 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3707 * @param TIMx Timer instance
3708 * @retval State of bit (1 or 0).
3709 */
LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)3710 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
3711 {
3712 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
3713 }
3714
3715 /**
3716 * @}
3717 */
3718
3719 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
3720 * @{
3721 */
3722 /**
3723 * @brief Enable update DMA request (UDE).
3724 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3725 * @param TIMx Timer instance
3726 * @retval None
3727 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3728 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3729 {
3730 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3731 }
3732
3733 /**
3734 * @brief Disable update DMA request (UDE).
3735 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3736 * @param TIMx Timer instance
3737 * @retval None
3738 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3739 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3740 {
3741 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3742 }
3743
3744 /**
3745 * @brief Indicates whether the update DMA request (UDE) is enabled.
3746 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3747 * @param TIMx Timer instance
3748 * @retval State of bit (1 or 0).
3749 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)3750 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
3751 {
3752 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3753 }
3754
3755 /**
3756 * @brief Enable capture/compare 1 DMA request (CC1DE).
3757 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3758 * @param TIMx Timer instance
3759 * @retval None
3760 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3761 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3762 {
3763 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3764 }
3765
3766 /**
3767 * @brief Disable capture/compare 1 DMA request (CC1DE).
3768 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3769 * @param TIMx Timer instance
3770 * @retval None
3771 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3772 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3773 {
3774 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3775 }
3776
3777 /**
3778 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3779 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3780 * @param TIMx Timer instance
3781 * @retval State of bit (1 or 0).
3782 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)3783 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
3784 {
3785 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3786 }
3787
3788 /**
3789 * @brief Enable capture/compare 2 DMA request (CC2DE).
3790 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3791 * @param TIMx Timer instance
3792 * @retval None
3793 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3794 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3795 {
3796 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3797 }
3798
3799 /**
3800 * @brief Disable capture/compare 2 DMA request (CC2DE).
3801 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3802 * @param TIMx Timer instance
3803 * @retval None
3804 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3805 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3806 {
3807 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3808 }
3809
3810 /**
3811 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3812 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3813 * @param TIMx Timer instance
3814 * @retval State of bit (1 or 0).
3815 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)3816 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
3817 {
3818 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3819 }
3820
3821 /**
3822 * @brief Enable capture/compare 3 DMA request (CC3DE).
3823 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3824 * @param TIMx Timer instance
3825 * @retval None
3826 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3827 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3828 {
3829 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3830 }
3831
3832 /**
3833 * @brief Disable capture/compare 3 DMA request (CC3DE).
3834 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3835 * @param TIMx Timer instance
3836 * @retval None
3837 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3838 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3839 {
3840 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3841 }
3842
3843 /**
3844 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3845 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3846 * @param TIMx Timer instance
3847 * @retval State of bit (1 or 0).
3848 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)3849 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
3850 {
3851 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3852 }
3853
3854 /**
3855 * @brief Enable capture/compare 4 DMA request (CC4DE).
3856 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3857 * @param TIMx Timer instance
3858 * @retval None
3859 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3860 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3861 {
3862 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3863 }
3864
3865 /**
3866 * @brief Disable capture/compare 4 DMA request (CC4DE).
3867 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3868 * @param TIMx Timer instance
3869 * @retval None
3870 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3871 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3872 {
3873 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3874 }
3875
3876 /**
3877 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3878 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3879 * @param TIMx Timer instance
3880 * @retval State of bit (1 or 0).
3881 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)3882 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
3883 {
3884 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3885 }
3886
3887 /**
3888 * @brief Enable commutation DMA request (COMDE).
3889 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3890 * @param TIMx Timer instance
3891 * @retval None
3892 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)3893 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3894 {
3895 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3896 }
3897
3898 /**
3899 * @brief Disable commutation DMA request (COMDE).
3900 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3901 * @param TIMx Timer instance
3902 * @retval None
3903 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)3904 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3905 {
3906 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3907 }
3908
3909 /**
3910 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3911 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3912 * @param TIMx Timer instance
3913 * @retval State of bit (1 or 0).
3914 */
LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)3915 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
3916 {
3917 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
3918 }
3919
3920 /**
3921 * @brief Enable trigger interrupt (TDE).
3922 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3923 * @param TIMx Timer instance
3924 * @retval None
3925 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3926 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3927 {
3928 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3929 }
3930
3931 /**
3932 * @brief Disable trigger interrupt (TDE).
3933 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3934 * @param TIMx Timer instance
3935 * @retval None
3936 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3937 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3938 {
3939 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3940 }
3941
3942 /**
3943 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3944 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3945 * @param TIMx Timer instance
3946 * @retval State of bit (1 or 0).
3947 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)3948 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
3949 {
3950 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3951 }
3952
3953 /**
3954 * @}
3955 */
3956
3957 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3958 * @{
3959 */
3960 /**
3961 * @brief Generate an update event.
3962 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3963 * @param TIMx Timer instance
3964 * @retval None
3965 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3966 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3967 {
3968 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3969 }
3970
3971 /**
3972 * @brief Generate Capture/Compare 1 event.
3973 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3974 * @param TIMx Timer instance
3975 * @retval None
3976 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3977 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3978 {
3979 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3980 }
3981
3982 /**
3983 * @brief Generate Capture/Compare 2 event.
3984 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3985 * @param TIMx Timer instance
3986 * @retval None
3987 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3988 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3989 {
3990 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3991 }
3992
3993 /**
3994 * @brief Generate Capture/Compare 3 event.
3995 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3996 * @param TIMx Timer instance
3997 * @retval None
3998 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)3999 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4000 {
4001 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4002 }
4003
4004 /**
4005 * @brief Generate Capture/Compare 4 event.
4006 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4007 * @param TIMx Timer instance
4008 * @retval None
4009 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4010 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4011 {
4012 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4013 }
4014
4015 /**
4016 * @brief Generate commutation event.
4017 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4018 * @param TIMx Timer instance
4019 * @retval None
4020 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4021 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4022 {
4023 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4024 }
4025
4026 /**
4027 * @brief Generate trigger event.
4028 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4029 * @param TIMx Timer instance
4030 * @retval None
4031 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4032 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4033 {
4034 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4035 }
4036
4037 /**
4038 * @brief Generate break event.
4039 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4040 * @param TIMx Timer instance
4041 * @retval None
4042 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4043 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4044 {
4045 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4046 }
4047
4048 /**
4049 * @}
4050 */
4051
4052 #if defined(USE_FULL_LL_DRIVER)
4053 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4054 * @{
4055 */
4056
4057 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4058 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4059 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
4060 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4061 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4062 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4063 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4064 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4065 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4066 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4067 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4068 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4069 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4070 /**
4071 * @}
4072 */
4073 #endif /* USE_FULL_LL_DRIVER */
4074
4075 /**
4076 * @}
4077 */
4078
4079 /**
4080 * @}
4081 */
4082
4083 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
4084
4085 /**
4086 * @}
4087 */
4088
4089 #ifdef __cplusplus
4090 }
4091 #endif
4092
4093 #endif /* __STM32F4xx_LL_TIM_H */
4094
