1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32mp1xx_ll_tim.h"
22 #include "stm32mp1xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined(TIM12) | defined (TIM13) | defined (TIM14) | defined (TIM15) || defined (TIM16) || defined (TIM17)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
153 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
154
155 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
156 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
157
158 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
159 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
160
161 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
177
178 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
179 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
180
181 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
182 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
183 /**
184 * @}
185 */
186
187
188 /* Private function prototypes -----------------------------------------------*/
189 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
190 * @{
191 */
192 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
193 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
194 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
195 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
199 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
200 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
201 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
202 /**
203 * @}
204 */
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @addtogroup TIM_LL_Exported_Functions
208 * @{
209 */
210
211 /** @addtogroup TIM_LL_EF_Init
212 * @{
213 */
214
215 /**
216 * @brief Set TIMx registers to their reset values.
217 * @param TIMx Timer instance
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: TIMx registers are de-initialized
220 * - ERROR: invalid TIMx instance
221 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)222 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
223 {
224 ErrorStatus result = SUCCESS;
225
226 /* Check the parameters */
227 assert_param(IS_TIM_INSTANCE(TIMx));
228
229 #if defined(TIM1)
230 if (TIMx == TIM1)
231 {
232 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
233 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
234 }
235 #endif
236 #if defined(TIM2)
237 else if (TIMx == TIM2)
238 {
239 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
240 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
241 }
242 #endif
243 #if defined(TIM3)
244 else if (TIMx == TIM3)
245 {
246 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
247 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
248 }
249 #endif
250 #if defined(TIM4)
251 else if (TIMx == TIM4)
252 {
253 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
254 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
255 }
256 #endif
257 #if defined(TIM5)
258 else if (TIMx == TIM5)
259 {
260 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
261 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
262 }
263 #endif
264 #if defined(TIM6)
265 else if (TIMx == TIM6)
266 {
267 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
268 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
269 }
270 #endif
271 #if defined (TIM7)
272 else if (TIMx == TIM7)
273 {
274 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
275 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
276 }
277 #endif
278 #if defined(TIM8)
279 else if (TIMx == TIM8)
280 {
281 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
282 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
283 }
284 #endif
285 #if defined(TIM12)
286 else if (TIMx == TIM12)
287 {
288 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
289 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
290 }
291 #endif
292 #if defined(TIM13)
293 else if (TIMx == TIM13)
294 {
295 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
296 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
297 }
298 #endif
299 #if defined(TIM14)
300 else if (TIMx == TIM14)
301 {
302 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
303 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
304 }
305 #endif
306 #if defined(TIM15)
307 else if (TIMx == TIM15)
308 {
309 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
310 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
311 }
312 #endif
313 #if defined(TIM16)
314 else if (TIMx == TIM16)
315 {
316 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
317 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
318 }
319 #endif
320 #if defined(TIM17)
321 else if (TIMx == TIM17)
322 {
323 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
324 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
325 }
326 #endif
327 else
328 {
329 result = ERROR;
330 }
331
332 return result;
333 }
334
335 /**
336 * @brief Set the fields of the time base unit configuration data structure
337 * to their default values.
338 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
339 * @retval None
340 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)341 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
342 {
343 /* Set the default configuration */
344 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
345 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
346 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
347 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
348 TIM_InitStruct->RepetitionCounter = 0x00000000U;
349 }
350
351 /**
352 * @brief Configure the TIMx time base unit.
353 * @param TIMx Timer Instance
354 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
355 * @retval An ErrorStatus enumeration value:
356 * - SUCCESS: TIMx registers are de-initialized
357 * - ERROR: not applicable
358 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)359 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
360 {
361 uint32_t tmpcr1;
362
363 /* Check the parameters */
364 assert_param(IS_TIM_INSTANCE(TIMx));
365 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
366 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
367
368 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
369
370 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
371 {
372 /* Select the Counter Mode */
373 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
374 }
375
376 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
377 {
378 /* Set the clock division */
379 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
380 }
381
382 /* Write to TIMx CR1 */
383 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
384
385 /* Set the Autoreload value */
386 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
387
388 /* Set the Prescaler value */
389 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
390
391 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
392 {
393 /* Set the Repetition Counter value */
394 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
395 }
396
397 /* Generate an update event to reload the Prescaler
398 and the repetition counter value (if applicable) immediately */
399 LL_TIM_GenerateEvent_UPDATE(TIMx);
400
401 return SUCCESS;
402 }
403
404 /**
405 * @brief Set the fields of the TIMx output channel configuration data
406 * structure to their default values.
407 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
408 * @retval None
409 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)410 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
411 {
412 /* Set the default configuration */
413 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
414 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
415 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
416 TIM_OC_InitStruct->CompareValue = 0x00000000U;
417 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
418 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
419 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
420 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
421 }
422
423 /**
424 * @brief Configure the TIMx output channel.
425 * @param TIMx Timer Instance
426 * @param Channel This parameter can be one of the following values:
427 * @arg @ref LL_TIM_CHANNEL_CH1
428 * @arg @ref LL_TIM_CHANNEL_CH2
429 * @arg @ref LL_TIM_CHANNEL_CH3
430 * @arg @ref LL_TIM_CHANNEL_CH4
431 * @arg @ref LL_TIM_CHANNEL_CH5
432 * @arg @ref LL_TIM_CHANNEL_CH6
433 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
434 * @retval An ErrorStatus enumeration value:
435 * - SUCCESS: TIMx output channel is initialized
436 * - ERROR: TIMx output channel is not initialized
437 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)438 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
439 {
440 ErrorStatus result = ERROR;
441
442 switch (Channel)
443 {
444 case LL_TIM_CHANNEL_CH1:
445 result = OC1Config(TIMx, TIM_OC_InitStruct);
446 break;
447 case LL_TIM_CHANNEL_CH2:
448 result = OC2Config(TIMx, TIM_OC_InitStruct);
449 break;
450 case LL_TIM_CHANNEL_CH3:
451 result = OC3Config(TIMx, TIM_OC_InitStruct);
452 break;
453 case LL_TIM_CHANNEL_CH4:
454 result = OC4Config(TIMx, TIM_OC_InitStruct);
455 break;
456 case LL_TIM_CHANNEL_CH5:
457 result = OC5Config(TIMx, TIM_OC_InitStruct);
458 break;
459 case LL_TIM_CHANNEL_CH6:
460 result = OC6Config(TIMx, TIM_OC_InitStruct);
461 break;
462 default:
463 break;
464 }
465
466 return result;
467 }
468
469 /**
470 * @brief Set the fields of the TIMx input channel configuration data
471 * structure to their default values.
472 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
473 * @retval None
474 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)475 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
476 {
477 /* Set the default configuration */
478 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
479 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
480 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
481 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
482 }
483
484 /**
485 * @brief Configure the TIMx input channel.
486 * @param TIMx Timer Instance
487 * @param Channel This parameter can be one of the following values:
488 * @arg @ref LL_TIM_CHANNEL_CH1
489 * @arg @ref LL_TIM_CHANNEL_CH2
490 * @arg @ref LL_TIM_CHANNEL_CH3
491 * @arg @ref LL_TIM_CHANNEL_CH4
492 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
493 * @retval An ErrorStatus enumeration value:
494 * - SUCCESS: TIMx output channel is initialized
495 * - ERROR: TIMx output channel is not initialized
496 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)497 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
498 {
499 ErrorStatus result = ERROR;
500
501 switch (Channel)
502 {
503 case LL_TIM_CHANNEL_CH1:
504 result = IC1Config(TIMx, TIM_IC_InitStruct);
505 break;
506 case LL_TIM_CHANNEL_CH2:
507 result = IC2Config(TIMx, TIM_IC_InitStruct);
508 break;
509 case LL_TIM_CHANNEL_CH3:
510 result = IC3Config(TIMx, TIM_IC_InitStruct);
511 break;
512 case LL_TIM_CHANNEL_CH4:
513 result = IC4Config(TIMx, TIM_IC_InitStruct);
514 break;
515 default:
516 break;
517 }
518
519 return result;
520 }
521
522 /**
523 * @brief Fills each TIM_EncoderInitStruct field with its default value
524 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
525 * @retval None
526 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)527 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
528 {
529 /* Set the default configuration */
530 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
531 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
532 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
533 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
534 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
535 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
536 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
537 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
538 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
539 }
540
541 /**
542 * @brief Configure the encoder interface of the timer instance.
543 * @param TIMx Timer Instance
544 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
545 * @retval An ErrorStatus enumeration value:
546 * - SUCCESS: TIMx registers are de-initialized
547 * - ERROR: not applicable
548 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)549 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
550 {
551 uint32_t tmpccmr1;
552 uint32_t tmpccer;
553
554 /* Check the parameters */
555 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
556 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
557 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
558 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
559 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
560 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
561 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
562 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
563 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
564 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
565
566 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
567 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
568
569 /* Get the TIMx CCMR1 register value */
570 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
571
572 /* Get the TIMx CCER register value */
573 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
574
575 /* Configure TI1 */
576 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
577 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
578 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
579 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
580
581 /* Configure TI2 */
582 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
583 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
584 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
585 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
586
587 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
588 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
589 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
590 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
591 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
592
593 /* Set encoder mode */
594 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
595
596 /* Write to TIMx CCMR1 */
597 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
598
599 /* Write to TIMx CCER */
600 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
601
602 return SUCCESS;
603 }
604
605 /**
606 * @brief Set the fields of the TIMx Hall sensor interface configuration data
607 * structure to their default values.
608 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
609 * @retval None
610 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)611 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
612 {
613 /* Set the default configuration */
614 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
615 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
616 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
617 TIM_HallSensorInitStruct->CommutationDelay = 0U;
618 }
619
620 /**
621 * @brief Configure the Hall sensor interface of the timer instance.
622 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
623 * to the TI1 input channel
624 * @note TIMx slave mode controller is configured in reset mode.
625 Selected internal trigger is TI1F_ED.
626 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
627 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
628 * between 2 changes on the inputs. It gives information about motor speed.
629 * @note Channel 2 is configured in output PWM 2 mode.
630 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
631 * @note OC2REF is selected as trigger output on TRGO.
632 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
633 * when TIMx operates in Hall sensor interface mode.
634 * @param TIMx Timer Instance
635 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
636 * @retval An ErrorStatus enumeration value:
637 * - SUCCESS: TIMx registers are de-initialized
638 * - ERROR: not applicable
639 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)640 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
641 {
642 uint32_t tmpcr2;
643 uint32_t tmpccmr1;
644 uint32_t tmpccer;
645 uint32_t tmpsmcr;
646
647 /* Check the parameters */
648 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
649 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
650 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
651 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
652
653 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
654 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
655
656 /* Get the TIMx CR2 register value */
657 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
658
659 /* Get the TIMx CCMR1 register value */
660 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
661
662 /* Get the TIMx CCER register value */
663 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
664
665 /* Get the TIMx SMCR register value */
666 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
667
668 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
669 tmpcr2 |= TIM_CR2_TI1S;
670
671 /* OC2REF signal is used as trigger output (TRGO) */
672 tmpcr2 |= LL_TIM_TRGO_OC2REF;
673
674 /* Configure the slave mode controller */
675 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
676 tmpsmcr |= LL_TIM_TS_TI1F_ED;
677 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
678
679 /* Configure input channel 1 */
680 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
681 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
682 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
683 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
684
685 /* Configure input channel 2 */
686 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
687 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
688
689 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
690 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
691 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
692 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
693
694 /* Write to TIMx CR2 */
695 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
696
697 /* Write to TIMx SMCR */
698 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
699
700 /* Write to TIMx CCMR1 */
701 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
702
703 /* Write to TIMx CCER */
704 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
705
706 /* Write to TIMx CCR2 */
707 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
708
709 return SUCCESS;
710 }
711
712 /**
713 * @brief Set the fields of the Break and Dead Time configuration data structure
714 * to their default values.
715 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
716 * @retval None
717 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)718 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
719 {
720 /* Set the default configuration */
721 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
722 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
723 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
724 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
725 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
726 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
727 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
728 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
729 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
730 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
731 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
732 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
733 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
734 }
735
736 /**
737 * @brief Configure the Break and Dead Time feature of the timer instance.
738 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
739 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
740 * can be necessary to configure all of them during the first write access to
741 * the TIMx_BDTR register.
742 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
743 * a timer instance provides a break input.
744 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
745 * a timer instance provides a second break input.
746 * @param TIMx Timer Instance
747 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
748 * @retval An ErrorStatus enumeration value:
749 * - SUCCESS: Break and Dead Time is initialized
750 * - ERROR: not applicable
751 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)752 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
753 {
754 uint32_t tmpbdtr = 0;
755
756 /* Check the parameters */
757 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
758 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
759 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
760 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
761 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
762 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
763 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
764
765 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
766 the OSSI State, the dead time value and the Automatic Output Enable Bit */
767
768 /* Set the BDTR bits */
769 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
770 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
771 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
772 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
773 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
774 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
775 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
776 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
777 if (IS_TIM_ADVANCED_INSTANCE(TIMx))
778 {
779 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
780 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
781 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
782 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
783 }
784
785 if (IS_TIM_BKIN2_INSTANCE(TIMx))
786 {
787 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
788 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
789 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
790 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
791
792 /* Set the BREAK2 input related BDTR bit-fields */
793 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
794 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
795 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
796 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
797 }
798
799 /* Set TIMx_BDTR */
800 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
801
802 return SUCCESS;
803 }
804 /**
805 * @}
806 */
807
808 /**
809 * @}
810 */
811
812 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
813 * @brief Private functions
814 * @{
815 */
816 /**
817 * @brief Configure the TIMx output channel 1.
818 * @param TIMx Timer Instance
819 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
820 * @retval An ErrorStatus enumeration value:
821 * - SUCCESS: TIMx registers are de-initialized
822 * - ERROR: not applicable
823 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)824 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
825 {
826 uint32_t tmpccmr1;
827 uint32_t tmpccer;
828 uint32_t tmpcr2;
829
830 /* Check the parameters */
831 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
832 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
833 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
834 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
835 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
836 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
837
838 /* Disable the Channel 1: Reset the CC1E Bit */
839 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
840
841 /* Get the TIMx CCER register value */
842 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
843
844 /* Get the TIMx CR2 register value */
845 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
846
847 /* Get the TIMx CCMR1 register value */
848 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
849
850 /* Reset Capture/Compare selection Bits */
851 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
852
853 /* Set the Output Compare Mode */
854 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
855
856 /* Set the Output Compare Polarity */
857 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
858
859 /* Set the Output State */
860 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
861
862 if (IS_TIM_BREAK_INSTANCE(TIMx))
863 {
864 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
865 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
866
867 /* Set the complementary output Polarity */
868 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
869
870 /* Set the complementary output State */
871 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
872
873 /* Set the Output Idle state */
874 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
875
876 /* Set the complementary output Idle state */
877 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
878 }
879
880 /* Write to TIMx CR2 */
881 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
882
883 /* Write to TIMx CCMR1 */
884 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
885
886 /* Set the Capture Compare Register value */
887 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
888
889 /* Write to TIMx CCER */
890 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
891
892 return SUCCESS;
893 }
894
895 /**
896 * @brief Configure the TIMx output channel 2.
897 * @param TIMx Timer Instance
898 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
899 * @retval An ErrorStatus enumeration value:
900 * - SUCCESS: TIMx registers are de-initialized
901 * - ERROR: not applicable
902 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)903 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
904 {
905 uint32_t tmpccmr1;
906 uint32_t tmpccer;
907 uint32_t tmpcr2;
908
909 /* Check the parameters */
910 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
911 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
912 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
913 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
914 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
915 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
916
917 /* Disable the Channel 2: Reset the CC2E Bit */
918 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
919
920 /* Get the TIMx CCER register value */
921 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
922
923 /* Get the TIMx CR2 register value */
924 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
925
926 /* Get the TIMx CCMR1 register value */
927 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
928
929 /* Reset Capture/Compare selection Bits */
930 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
931
932 /* Select the Output Compare Mode */
933 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
934
935 /* Set the Output Compare Polarity */
936 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
937
938 /* Set the Output State */
939 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
940
941 if (IS_TIM_BREAK_INSTANCE(TIMx))
942 {
943 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
944 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
945
946 /* Set the complementary output Polarity */
947 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
948
949 /* Set the complementary output State */
950 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
951
952 /* Set the Output Idle state */
953 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
954
955 /* Set the complementary output Idle state */
956 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
957 }
958
959 /* Write to TIMx CR2 */
960 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
961
962 /* Write to TIMx CCMR1 */
963 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
964
965 /* Set the Capture Compare Register value */
966 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
967
968 /* Write to TIMx CCER */
969 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
970
971 return SUCCESS;
972 }
973
974 /**
975 * @brief Configure the TIMx output channel 3.
976 * @param TIMx Timer Instance
977 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
978 * @retval An ErrorStatus enumeration value:
979 * - SUCCESS: TIMx registers are de-initialized
980 * - ERROR: not applicable
981 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)982 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
983 {
984 uint32_t tmpccmr2;
985 uint32_t tmpccer;
986 uint32_t tmpcr2;
987
988 /* Check the parameters */
989 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
990 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
991 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
992 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
993 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
994 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
995
996 /* Disable the Channel 3: Reset the CC3E Bit */
997 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
998
999 /* Get the TIMx CCER register value */
1000 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1001
1002 /* Get the TIMx CR2 register value */
1003 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1004
1005 /* Get the TIMx CCMR2 register value */
1006 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1007
1008 /* Reset Capture/Compare selection Bits */
1009 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1010
1011 /* Select the Output Compare Mode */
1012 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1013
1014 /* Set the Output Compare Polarity */
1015 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1016
1017 /* Set the Output State */
1018 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1019
1020 if (IS_TIM_BREAK_INSTANCE(TIMx))
1021 {
1022 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1023 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1024
1025 /* Set the complementary output Polarity */
1026 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1027
1028 /* Set the complementary output State */
1029 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1030
1031 /* Set the Output Idle state */
1032 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1033
1034 /* Set the complementary output Idle state */
1035 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1036 }
1037
1038 /* Write to TIMx CR2 */
1039 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1040
1041 /* Write to TIMx CCMR2 */
1042 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1043
1044 /* Set the Capture Compare Register value */
1045 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1046
1047 /* Write to TIMx CCER */
1048 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1049
1050 return SUCCESS;
1051 }
1052
1053 /**
1054 * @brief Configure the TIMx output channel 4.
1055 * @param TIMx Timer Instance
1056 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1057 * @retval An ErrorStatus enumeration value:
1058 * - SUCCESS: TIMx registers are de-initialized
1059 * - ERROR: not applicable
1060 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1061 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1062 {
1063 uint32_t tmpccmr2;
1064 uint32_t tmpccer;
1065 uint32_t tmpcr2;
1066
1067 /* Check the parameters */
1068 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1069 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1070 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1071 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1072 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1073 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1074
1075 /* Disable the Channel 4: Reset the CC4E Bit */
1076 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1077
1078 /* Get the TIMx CCER register value */
1079 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1080
1081 /* Get the TIMx CR2 register value */
1082 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1083
1084 /* Get the TIMx CCMR2 register value */
1085 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1086
1087 /* Reset Capture/Compare selection Bits */
1088 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1089
1090 /* Select the Output Compare Mode */
1091 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1092
1093 /* Set the Output Compare Polarity */
1094 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1095
1096 /* Set the Output State */
1097 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1098
1099 if (IS_TIM_BREAK_INSTANCE(TIMx))
1100 {
1101 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1102 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1103
1104 /* Set the Output Idle state */
1105 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1106 }
1107
1108 /* Write to TIMx CR2 */
1109 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1110
1111 /* Write to TIMx CCMR2 */
1112 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1113
1114 /* Set the Capture Compare Register value */
1115 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1116
1117 /* Write to TIMx CCER */
1118 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1119
1120 return SUCCESS;
1121 }
1122
1123 /**
1124 * @brief Configure the TIMx output channel 5.
1125 * @param TIMx Timer Instance
1126 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1127 * @retval An ErrorStatus enumeration value:
1128 * - SUCCESS: TIMx registers are de-initialized
1129 * - ERROR: not applicable
1130 */
OC5Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1131 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1132 {
1133 uint32_t tmpccmr3;
1134 uint32_t tmpccer;
1135
1136 /* Check the parameters */
1137 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1138 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1139 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1140 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1141 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1142 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1143
1144 /* Disable the Channel 5: Reset the CC5E Bit */
1145 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1146
1147 /* Get the TIMx CCER register value */
1148 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1149
1150 /* Get the TIMx CCMR3 register value */
1151 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1152
1153 /* Select the Output Compare Mode */
1154 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1155
1156 /* Set the Output Compare Polarity */
1157 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1158
1159 /* Set the Output State */
1160 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1161
1162 if (IS_TIM_BREAK_INSTANCE(TIMx))
1163 {
1164 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1165 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1166
1167 /* Set the Output Idle state */
1168 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1169
1170 }
1171
1172 /* Write to TIMx CCMR3 */
1173 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1174
1175 /* Set the Capture Compare Register value */
1176 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1177
1178 /* Write to TIMx CCER */
1179 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1180
1181 return SUCCESS;
1182 }
1183
1184 /**
1185 * @brief Configure the TIMx output channel 6.
1186 * @param TIMx Timer Instance
1187 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1188 * @retval An ErrorStatus enumeration value:
1189 * - SUCCESS: TIMx registers are de-initialized
1190 * - ERROR: not applicable
1191 */
OC6Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1192 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1193 {
1194 uint32_t tmpccmr3;
1195 uint32_t tmpccer;
1196
1197 /* Check the parameters */
1198 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1199 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1200 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1201 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1202 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1203 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1204
1205 /* Disable the Channel 5: Reset the CC6E Bit */
1206 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1207
1208 /* Get the TIMx CCER register value */
1209 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1210
1211 /* Get the TIMx CCMR3 register value */
1212 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1213
1214 /* Select the Output Compare Mode */
1215 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1216
1217 /* Set the Output Compare Polarity */
1218 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1219
1220 /* Set the Output State */
1221 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1222
1223 if (IS_TIM_BREAK_INSTANCE(TIMx))
1224 {
1225 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1226 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1227
1228 /* Set the Output Idle state */
1229 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1230 }
1231
1232 /* Write to TIMx CCMR3 */
1233 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1234
1235 /* Set the Capture Compare Register value */
1236 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1237
1238 /* Write to TIMx CCER */
1239 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1240
1241 return SUCCESS;
1242 }
1243
1244 /**
1245 * @brief Configure the TIMx input channel 1.
1246 * @param TIMx Timer Instance
1247 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1248 * @retval An ErrorStatus enumeration value:
1249 * - SUCCESS: TIMx registers are de-initialized
1250 * - ERROR: not applicable
1251 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1252 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1253 {
1254 /* Check the parameters */
1255 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1256 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1257 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1258 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1259 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1260
1261 /* Disable the Channel 1: Reset the CC1E Bit */
1262 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1263
1264 /* Select the Input and set the filter and the prescaler value */
1265 MODIFY_REG(TIMx->CCMR1,
1266 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1267 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1268
1269 /* Select the Polarity and set the CC1E Bit */
1270 MODIFY_REG(TIMx->CCER,
1271 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1272 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1273
1274 return SUCCESS;
1275 }
1276
1277 /**
1278 * @brief Configure the TIMx input channel 2.
1279 * @param TIMx Timer Instance
1280 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1281 * @retval An ErrorStatus enumeration value:
1282 * - SUCCESS: TIMx registers are de-initialized
1283 * - ERROR: not applicable
1284 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1285 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1286 {
1287 /* Check the parameters */
1288 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1289 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1290 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1291 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1292 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1293
1294 /* Disable the Channel 2: Reset the CC2E Bit */
1295 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1296
1297 /* Select the Input and set the filter and the prescaler value */
1298 MODIFY_REG(TIMx->CCMR1,
1299 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1300 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1301
1302 /* Select the Polarity and set the CC2E Bit */
1303 MODIFY_REG(TIMx->CCER,
1304 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1305 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1306
1307 return SUCCESS;
1308 }
1309
1310 /**
1311 * @brief Configure the TIMx input channel 3.
1312 * @param TIMx Timer Instance
1313 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1314 * @retval An ErrorStatus enumeration value:
1315 * - SUCCESS: TIMx registers are de-initialized
1316 * - ERROR: not applicable
1317 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1318 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1319 {
1320 /* Check the parameters */
1321 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1322 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1323 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1324 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1325 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1326
1327 /* Disable the Channel 3: Reset the CC3E Bit */
1328 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1329
1330 /* Select the Input and set the filter and the prescaler value */
1331 MODIFY_REG(TIMx->CCMR2,
1332 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1333 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1334
1335 /* Select the Polarity and set the CC3E Bit */
1336 MODIFY_REG(TIMx->CCER,
1337 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1338 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1339
1340 return SUCCESS;
1341 }
1342
1343 /**
1344 * @brief Configure the TIMx input channel 4.
1345 * @param TIMx Timer Instance
1346 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1347 * @retval An ErrorStatus enumeration value:
1348 * - SUCCESS: TIMx registers are de-initialized
1349 * - ERROR: not applicable
1350 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1351 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1352 {
1353 /* Check the parameters */
1354 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1355 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1356 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1357 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1358 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1359
1360 /* Disable the Channel 4: Reset the CC4E Bit */
1361 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1362
1363 /* Select the Input and set the filter and the prescaler value */
1364 MODIFY_REG(TIMx->CCMR2,
1365 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1366 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1367
1368 /* Select the Polarity and set the CC2E Bit */
1369 MODIFY_REG(TIMx->CCER,
1370 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1371 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1372
1373 return SUCCESS;
1374 }
1375
1376
1377 /**
1378 * @}
1379 */
1380
1381 /**
1382 * @}
1383 */
1384
1385 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
1386
1387 /**
1388 * @}
1389 */
1390
1391 #endif /* USE_FULL_LL_DRIVER */
1392
