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/Zephyr-latest/boards/infineon/cy8cproto_063_ble/
Dcy8cproto_063_ble.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "cy8cproto_063_ble-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "CY8CPROTO-063-BLE PSOC™ 6 BLE Prototyping Kit";
19 uart-5 = &uart5;
29 zephyr,shell-uart = &uart5;
30 zephyr,bt-hci = &bluetooth;
33 /delete-node/ cpu@0;
36 compatible = "gpio-leds";
[all …]
/Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/
Dcy8ckit_062s2_ai.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "CY8CKIT-062S2-AI PSOC 6 AI Evaluation Kit";
18 zephyr,shell-uart = &uart5;
30 compatible = "gpio-leds";
42 compatible = "gpio-keys";
53 clock-frequency = <100000000>;
57 clock-div = <1>;
61 /* CM4 core clock = 100MHz
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ hse-bypass;
20 /delete-property/ clock-frequency;
25 /delete-property/ hsi-div;
41 /delete-property/ div-m;
42 /delete-property/ mul-n;
43 /delete-property/ div-p;
44 /delete-property/ div-q;
45 /delete-property/ div-r;
46 /delete-property/ clocks;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi5 * SPDX-License-Identifier: Apache-2.0
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <8000000>;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
30 #clock-cells = <0>;
31 compatible = "fixed-factor-clock";
38 #clock-cells = <0>;
39 compatible = "fixed-factor-clock";
[all …]
/Zephyr-latest/boards/infineon/cy8cproto_062_4343w/
Dcy8cproto_062_4343w.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "cy8cproto_062_4343w-common.dtsi"
10 #include "cy8cproto_062_4343w-pinctrl.dtsi"
17 uart-5 = &uart5;
18 i2c-0 = &i2c3;
27 zephyr,shell-uart = &uart5;
28 zephyr,bt-hci = &bt_hci_uart;
37 compatible = "infineon,cat1-uart";
39 current-speed = <115200>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg4_i2c1_hsi_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dl4_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
32 /delete-property/ clocks;
[all …]
Dl4_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
32 /delete-property/ clocks;
[all …]
Dg0_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32g4-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
7 It can take one of clk_hse or clk_hsi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48MCLK (for USB, RNG)
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32g4-pll-clock"
25 - name: st,stm32l4-pll-clock.yaml
[all …]
Dst,stm32g0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
7 It can take one of clk_hse or clk_hsi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to I2S
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32g0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
[all …]
Dst,stm32u0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32u0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
[all …]
Dst,stm32f4-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse or clk_hsi as input clock, with an
8 input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
11 Up to 2 output clocks could be supported and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32f4-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
[all …]
Dst,stm32wb-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
10 These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLPCLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLLQCLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLRCLK (System Clock)
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
24 - 64 MHz on STM32WB
25 - 62 MHz on STM32WL
[all …]
Dst,stm32l4-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
10 These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLSAI3CLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48M1CLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
25 compatible: "st,stm32l4-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
[all …]
Dst,stm32h7-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
10 These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_Px) = f(VCOx clock) / PLLPx -> pllx_p_ck ((pll1_p_ck : sys_ck))
18 f(PLL_Qx) = f(VCOx clock) / PLLQx -> pllx_q_ck
19 f(PLL_Rx) = f(VCOx clock) / PLLRx -> pllx_r_ck
21 with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
25 compatible: "st,stm32h7-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
[all …]
Dst,stm32u5-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
9 These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
11 clock in this acceptable range.
13 Each PLL can have up to 3 output clocks and for each output clock, the
16 f(PLL_P) = f(VCO clock) / PLLP
17 f(PLL_Q) = f(VCO clock) / PLLQ
18 f(PLL_R) = f(VCO clock) / PLLR
20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 clock output to the lowest frequency.
27 compatible: "st,stm32u5-pll-clock"
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dclear_clocks.overlay5 * SPDX-License-Identifier: Apache-2.0
13 /* Keep csi on to be the usart1-console clock */
25 /delete-property/ clock-frequency;
26 /delete-property/ hse-bypass;
31 /delete-property/ hsi-div;
39 /delete-property/ div-m;
40 /delete-property/ mul-n;
41 /delete-property/ div-p;
42 /delete-property/ div-q;
43 /delete-property/ div-r;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8t1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8m1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8d1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 sdram: sdram-controller@40002000 {
13 compatible = "renesas,ra-sdram";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 lcdif: display-controller@40342000 {
21 compatible = "renesas,ra-glcdc";
25 interrupt-names = "line";
30 compatible = "renesas,ra-mipi-dsi";
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
24 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
49 /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
60 /* Enable Sys Pll1 divide-by-2 clock or not */
62 /* Enable Sys Pll1 divide-by-5 clock or not */
80 * Description : FLEXSPI clock source safe configuration weak function.
81 * Called before clock source configuration.
82 * Note : Users need override this function to change FLEXSPI clock source to stable
84 * should runs in RAM and move the FLEXSPI clock source to a stable clock
[all …]

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