Lines Matching +full:clock +full:- +full:div

2 # SPDX-License-Identifier: Apache-2.0
9   These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
11   clock in this acceptable range.
13   Each PLL can have up to 3 output clocks and for each output clock, the
16     f(PLL_P) = f(VCO clock) / PLLP
17     f(PLL_Q) = f(VCO clock) / PLLQ
18     f(PLL_R) = f(VCO clock) / PLLR
20       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23         clock output to the lowest frequency.
27 compatible: "st,stm32u5-pll-clock"
29 include: [clock-controller.yaml, base.yaml]
33   "#clock-cells":
39   div-m:
44         input clock
45         Valid range: 1 - 16
47   mul-n:
52         Valid range: 4 - 512
54   div-p:
58         Valid range: 1 - 128
60   div-q:
64         Valid range: 1 - 128
66   div-r:
73         Valid range: 1 - 128
79         Valid range: 0 - 8191