Lines Matching +full:clock +full:- +full:div

2 # SPDX-License-Identifier: Apache-2.0
10   These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12   clock in this acceptable range.
14   Each PLL can have up to 3 output clocks and for each output clock, the
17     f(PLL_P) = f(VCO clock) / PLLP  --> PLLPCLK
18     f(PLL_Q) = f(VCO clock) / PLLQ  --> PLLQCLK
19     f(PLL_R) = f(VCO clock) / PLLR  --> PLLRCLK (System Clock)
21       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
24           - 64 MHz on STM32WB
25           - 62 MHz on STM32WL
27 compatible: "st,stm32wb-pll-clock"
29 include: [clock-controller.yaml, base.yaml]
32   "#clock-cells":
38   div-m:
42         Main PLL division factor for PLL input clock
43         Valid range: 1 - 8
45   mul-n:
50         Valid range: 6 - 127
52   div-p:
56         Valid range: 2 - 32
58   div-q:
62         Valid range: 2 - 8
64   div-r:
68         Main PLL division factor for PLLRCLK (system clock)
69         Valid range: 2 - 8