1/*
2 * Copyright (c) 2021 Cypress Semiconductor Corporation.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/dts-v1/;
7#include <infineon/cat1a/mpns/CY8C624ABZI_S2D44.dtsi>
8#include <infineon/cat1a/system_clocks.dtsi>
9#include "cy8cproto_062_4343w-common.dtsi"
10#include "cy8cproto_062_4343w-pinctrl.dtsi"
11
12/ {
13	model = "cy8cproto_062_4343w with an Cypress PSOC™ 6 SoC";
14	compatible = "cypress,cy8cproto_062_4343w", "cypress,PSOC6";
15
16	aliases {
17		uart-5 = &uart5;
18		i2c-0 = &i2c3;
19		watchdog0 = &watchdog0;
20		sdhc0 = &sdhc0;
21	};
22
23	chosen {
24		zephyr,sram = &sram0;
25		zephyr,flash = &flash0;
26		zephyr,console = &uart5;
27		zephyr,shell-uart = &uart5;
28		zephyr,bt-hci = &bt_hci_uart;
29	};
30};
31
32&counter0_0 {
33	status = "okay";
34};
35
36uart5: &scb5 {
37	compatible = "infineon,cat1-uart";
38	status = "okay";
39	current-speed = <115200>;
40
41	pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
42	pinctrl-names = "default";
43};
44
45uart2: &scb2 {
46	compatible = "infineon,cat1-uart";
47	status = "okay";
48
49	/* The UART bus speed (current_speed) for zephyr_bt_uart should be the same
50	 * as the default baudrate defined in CYW43xx firmware (default 115200).
51	 */
52	current-speed = <115200>;
53
54	/* HCI-UART pins */
55	pinctrl-0 = <&p3_1_scb2_uart_tx &p3_0_scb2_uart_rx &p3_2_scb2_uart_rts &p3_3_scb2_uart_cts>;
56	pinctrl-names = "default";
57
58	/* HW Flow control must be enabled for HCI H4 */
59	hw-flow-control;
60
61	bt_hci_uart: bt_hci_uart {
62		compatible = "zephyr,bt-hci-uart";
63
64		murata-1dx {
65			status = "okay";
66			compatible = "infineon,cyw43xxx-bt-hci";
67			bt-reg-on-gpios = <&gpio_prt3 4 (GPIO_ACTIVE_HIGH)>;
68
69			/* Configuration UART speeds for firmware download (fw-download-speed)
70			 * and HCI operation (hci-operation-speed).
71			 * If hci-operation-speed or fw-download-speed are not defined in
72			 * bt-hci{...} node, cyw43xx driver will use bus/current-speed as
73			 * default speed.
74			 */
75			fw-download-speed = <3000000>;
76		};
77	};
78};
79
80&sdhc0 {
81	status = "okay";
82
83	/* SDIO pins */
84	pinctrl-0 = <&p2_4_sdio_cmd &p2_5_sdio_clk &p2_0_sdio_data0
85		     &p2_1_sdio_data1 &p2_2_sdio_data2 &p2_3_sdio_data3>;
86	pinctrl-names = "default";
87
88	/* Wi-Fi configuration */
89	airoc-wifi {
90		status = "okay";
91		compatible = "infineon,airoc-wifi";
92
93		/* Wi-Fi control gpios */
94		wifi-reg-on-gpios    = <&gpio_prt2 6 GPIO_ACTIVE_HIGH>;
95		wifi-host-wake-gpios = <&gpio_prt0 4 GPIO_ACTIVE_HIGH>;
96	};
97};
98
99/* System clock configuration */
100&fll0 {
101	status = "okay";
102	clock-frequency = <100000000>;
103};
104
105&clk_hf0 {
106	clock-div = <1>;
107	clocks = <&fll0>;
108};
109
110/* CM4 core clock = 100MHz
111 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
112 */
113&clk_fast {
114	clock-div = <1>;
115};
116
117/* CM0+ core clock = 50MHz
118 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
119 */
120&clk_slow {
121	clock-div = <2>;
122};
123
124/* PERI core clock = 100MHz
125 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
126 */
127&clk_peri {
128	clock-div = <1>;
129};
130
131i2c3: &scb3 {
132	compatible = "infineon,cat1-i2c";
133
134	/* I2C pins */
135	pinctrl-0 = <&p6_0_scb3_i2c_scl &p6_1_scb3_i2c_sda>;
136	pinctrl-names = "default";
137};
138
139&watchdog0 {
140	status = "okay";
141};
142