4  * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
24 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
49 	/* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
60 	/* Enable Sys Pll1 divide-by-2 clock or not */
62 	/* Enable Sys Pll1 divide-by-5 clock or not */
80  * Description   : FLEXSPI clock source safe configuration weak function.
81  *                 Called before clock source configuration.
82  * Note          : Users need override this function to change FLEXSPI clock source to stable
84  *                 should runs in RAM and move the FLEXSPI clock source to a stable clock
85  *                 to avoid instruction/data fetch issue during clock updating.
92  * @brief Initialize the system clock
105 	rootCfg.div = 1;  in clock_init()
111 	rootCfg.div = 2;  in clock_init()
129 	ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) |  in clock_init()
135 			(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {  in clock_init()
138 	/* Call function board_flexspi_clock_safe_config() to move FlexSPI clock to a stable  in clock_init()
139 	 * clock source to avoid instruction/data fetch issue when updating PLL if XIP  in clock_init()
180 	/* Module clock root configurations. */  in clock_init()
183 	rootCfg.div = 1;  in clock_init()
190 	rootCfg.div = 2;  in clock_init()
196 	rootCfg.div = 4;  in clock_init()
201 	rootCfg.div = 4;  in clock_init()
206 	rootCfg.div = 2;  in clock_init()
211 	rootCfg.div = 3;  in clock_init()
217 	rootCfg.div = 240;  in clock_init()
224 	rootCfg.div = 240;  in clock_init()
233 	rootCfg.div = 10;  in clock_init()
241 	rootCfg.div = 4;  in clock_init()
250 	rootCfg.div = 4;  in clock_init()
259 	rootCfg.div = 4;  in clock_init()
268 	rootCfg.div = 2;  in clock_init()
277 	rootCfg.div = 1;  in clock_init()
284 	rootCfg.div = 1;  in clock_init()
298 	rootCfg.div = 2;  in clock_init()
307 	rootCfg.div = 4;  in clock_init()
312 	rootCfg.div = 2;  in clock_init()
317 	rootCfg.div = 2;  in clock_init()
322 	rootCfg.div = 10;  in clock_init()
327 	rootCfg.div = 4;  in clock_init()
332 	rootCfg.div = 4;  in clock_init()
337 	rootCfg.div = 4;  in clock_init()
342 	rootCfg.div = 10;  in clock_init()
345 	/* Set NETC PORT Ref clock source. */  in clock_init()
346 	BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=  in clock_init()
348 	BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=  in clock_init()
350 	BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=  in clock_init()
352 	BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=  in clock_init()
354 	BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=  in clock_init()
357 	/* Set TMR 1588 Ref clock source. */  in clock_init()
358 	BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |=  in clock_init()
367 	rootCfg.div = 6;  in clock_init()
374 	rootCfg.div = 6;  in clock_init()
381 	rootCfg.div = 6;  in clock_init()
392 	rootCfg.div = 3;  in clock_init()
399 	rootCfg.div = 3;  in clock_init()
406 	rootCfg.div = 3;  in clock_init()
416 	rootCfg.div = 3;  in clock_init()
425 	rootCfg.div = 3;  in clock_init()
432 	rootCfg.div = 3;  in clock_init()
439 	rootCfg.div = 3;  in clock_init()
446 	rootCfg.div = 3;  in clock_init()
457 	rootCfg.div = 10;  in clock_init()
464 	rootCfg.div = 10;  in clock_init()
470 	/* Keep core clock ungated during WFI */  in clock_init()
471 	CCM->LPCG[1].LPM0 = 0x33333333;  in clock_init()
472 	CCM->LPCG[1].LPM1 = 0x33333333;  in clock_init()
473 	/* Keep the system clock running so SYSTICK can wake up  in clock_init()
482 	/* Enable the AHB clock while the CM7 is sleeping to allow debug access  in clock_init()
485 	BLK_CTRL_S_AONMIX->M7_CFG |= BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK;  in clock_init()
490  * @brief Initialize the system clock
583 	/* Initialize system clock */  in soc_early_init_hook()