Lines Matching +full:clock +full:- +full:div

2 # SPDX-License-Identifier: Apache-2.0
7   It can take one of clk_hse or clk_hsi as input clock, with
9   clock in this acceptable range.
11   PLL can have up to 3 output clocks and for each output clock, the
14     f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
15     f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48MCLK (for USB, RNG)
16     f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
18       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32g4-pll-clock"
25   - name: st,stm32l4-pll-clock.yaml
26     property-blocklist:
27       - div-m
28       - mul-n
29       - div-p
33   div-m:
37         Division factor for PLL input clock
38         Valid range: 1 - 16
40   mul-n:
45         Valid range: 8 - 127
47   div-p:
51         Valid range: 2 - 31