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Searched +full:clkout +full:- +full:frequency (Results 1 – 25 of 32) sorted by relevance

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/Zephyr-latest/dts/bindings/rtc/
Dmicrocrystal,rv-8263-c8.yaml1 # SPDX-License-Identifier: Apache-2.0
3 # Author: Daniel Kampert <DanielKampert@Kampis-Elektroecke.de>
5 description: Micro Crystal RV-8263-C8 RTC
7 compatible: "microcrystal,rv-8263-c8"
10 - name: rtc-device.yaml
11 - name: i2c-device.yaml
14 int-gpios:
15 type: phandle-array
17 clkout:
21 - 32768
[all …]
Dmicrocrystal,rv3028.yaml2 # SPDX-License-Identifier: Apache-2.0
9 - name: rtc-device.yaml
10 - name: i2c-device.yaml
13 clkout-frequency:
16 - 32768
17 - 8192
18 - 1024
19 - 64
20 - 32
21 - 1
[all …]
Dnxp,pcf8523.yaml1 # Copyright (c) 2019-2023 Henrik Brix Andersen <henrik@brixandersen.dk>
2 # SPDX-License-Identifier: Apache-2.0
9 - name: rtc-device.yaml
10 - name: i2c-device.yaml
11 - name: pm.yaml
12 property-allowlist:
13 - wakeup-source
16 quartz-load-femtofarads:
19 - 7000
20 - 12500
[all …]
/Zephyr-latest/dts/bindings/clock/
Dlitex,clkout.yaml2 # SPDX-License-Identifier: Apache-2.0
9 compatible: "litex,clkout"
13 "#clock-cells":
22 clock-output-names:
28 litex,clock-frequency:
32 default frequency in Hz for clock output
34 litex,clock-phase:
40 litex,clock-duty-num:
46 litex,clock-duty-den:
52 litex,clock-margin:
[all …]
Dlitex,clk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
9 of up to 7 clock outputs with ability to change frequency, duty
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
33 litex,lock-timeout:
38 litex,drdy-timeout:
[all …]
/Zephyr-latest/tests/drivers/build_all/rtc/
Di2c_devices.overlay3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
13 gpio-controller;
15 #gpio-cells = <0x2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 clock-frequency = <100000>;
31 am1805-gpios = <&test_gpio 0 0>;
38 alarms-count = <1>;
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
26 static struct litex_clk_clkout *clkouts;/* clkout array for whole driver */
52 m.clkout[5].reg1 = CLKOUT5_REG1; in litex_clk_regs_addr_init()
53 m.clkout[5].reg2 = CLKOUT5_REG2; in litex_clk_regs_addr_init()
55 m.clkout[i].reg1 = addr; in litex_clk_regs_addr_init()
57 m.clkout[i].reg2 = addr; in litex_clk_regs_addr_init()
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
[all …]
/Zephyr-latest/dts/riscv/
Driscv32-litex-vexriscv.dtsi2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "litex,vexriscv", "litex-dev";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clock-frequency = <100000000>;
25 compatible = "litex,vexriscv-standard", "riscv";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4w1ad2cng.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &adc1;
16 compatible = "mmio-sram";
20 flash-controller@407e0000 {
22 compatible = "soc-nv-flash";
28 compatible = "renesas,ra-sci";
30 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
Dr7fa4e2b93cfm.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
10 /delete-node/ &agt0;
11 /delete-node/ &agt1;
12 /delete-node/ &agt2;
13 /delete-node/ &agt3;
14 /delete-node/ &agt4;
15 /delete-node/ &agt5;
16 /delete-node/ &iic0;
[all …]
Dr7fa4m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &spi1;
16 compatible = "mmio-sram";
21 compatible = "renesas,ra-gpio-ioport";
24 gpio-controller;
25 #gpio-cells = <2>;
31 compatible = "renesas,ra-gpio-ioport";
[all …]
Dr7fa4m2ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &spi1;
13 /delete-node/ &adc1;
18 compatible = "mmio-sram";
23 compatible = "renesas,ra-gpio-ioport";
26 gpio-controller;
27 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m1ad3cfp.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
13 compatible = "mmio-sram";
17 flash-controller@407e0000 {
19 #address-cells = <1>;
20 #size-cells = <1>;
23 compatible = "soc-nv-flash";
29 compatible = "renesas,ra-sce7-rng";
34 channel-count = <11>;
[all …]
Dr7fa6e2bx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
10 /delete-node/ &agt0;
11 /delete-node/ &agt1;
12 /delete-node/ &agt2;
13 /delete-node/ &agt3;
14 /delete-node/ &agt4;
15 /delete-node/ &agt5;
16 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
[all …]
Dr7fa6m2ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-sci";
21 interrupt-names = "rxi", "txi", "tei", "eri";
26 compatible = "renesas,ra-sci-uart";
33 compatible = "renesas,ra-sci";
35 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
Dr7fa6m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
32 gpio-controller;
[all …]
Dr7fa6e10x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &adc1;
16 compatible = "mmio-sram";
21 compatible = "renesas,ra-gpio-ioport";
24 gpio-controller;
25 #gpio-cells = <2>;
31 compatible = "renesas,ra-gpio-ioport";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2a1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &sci2;
12 /delete-node/ &sci3;
13 /delete-node/ &ioport6;
14 /delete-node/ &ioport7;
15 /delete-node/ &ioport8;
20 compatible = "mmio-sram";
25 compatible = "renesas,ra-spi";
[all …]
/Zephyr-latest/samples/drivers/clock_control_litex/
DREADME.rst1 .. zephyr:code-sample:: clock-control-litex
3 :relevant-api: clock_control_interface
11 …lock Manager (MMCM) module to generate up to 7 clocks with defined phase, frequency and duty cycle.
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
25 :start-at: clk0: clock-controller@0 {
26 :end-at: };
29 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
31 :start-at: clk1: clock-controller@1 {
[all …]
/Zephyr-latest/dts/arm/renesas/ra/
Dra-cm4-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
11 #include <zephyr/dt-bindings/clock/ra_clock.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m4";
26 xtal: clock-main-osc {
27 compatible = "renesas,ra-cgc-external-clock";
28 clock-frequency = <1200000>;
[all …]
/Zephyr-latest/boards/nxp/twr_ke18f/
Dtwr_ke18f.dts2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include "twr_ke18f-pinctrl.dtsi"
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
27 pwm-led0 = &orange_pwm_led;
28 pwm-led1 = &yellow_pwm_led;
29 pwm-led2 = &green_pwm_led;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8t1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8d1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 sdram: sdram-controller@40002000 {
13 compatible = "renesas,ra-sdram";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 lcdif: display-controller@40342000 {
21 compatible = "renesas,ra-glcdc";
25 interrupt-names = "line";
30 compatible = "renesas,ra-mipi-dsi";
[all …]
/Zephyr-latest/samples/drivers/clock_control_litex/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
13 /* Select clock outputs for tests [0-6] */
17 /* Values for frequency test */
75 printf("CLKOUT%d: get_status: rate:%d phase:%d duty:%d\n", in litex_clk_test_getters()
78 printf("CLKOUT%d: get_rate:%d\n", i, rate); in litex_clk_test_getters()
127 printf("Frequency test\n"); in litex_clk_test_freq()
148 if (ret != 0 && ret != -ENOTSUP) { in litex_clk_test_freq()
159 i -= LITEX_TEST_FREQUENCY_STEP) { in litex_clk_test_freq()
164 if (ret != 0 && ret != -ENOTSUP) { in litex_clk_test_freq()
200 if (ret != 0 && ret != -ENOTSUP) { in litex_clk_test_phase()
[all …]

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