1/*
2 * Copyright (c) 2024 TOKITA Hiroshi
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra2/ra2xx.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/delete-node/ &sci2;
12/delete-node/ &sci3;
13/delete-node/ &ioport6;
14/delete-node/ &ioport7;
15/delete-node/ &ioport8;
16
17/ {
18	soc {
19		sram0: memory@20000000 {
20			compatible = "mmio-sram";
21			reg = <0x20000000 DT_SIZE_K(32)>;
22		};
23
24		spi1: spi@40072100 {
25			compatible = "renesas,ra-spi";
26			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
27			interrupt-names = "rxi", "txi", "tei", "eri";
28		};
29
30		pwm1: pwm1@40078100 {
31			compatible = "renesas,ra-pwm";
32			divider = <RA_PWM_SOURCE_DIV_1>;
33			channel = <RA_PWM_CHANNEL_1>;
34			clocks = <&pclkd MSTPD 6>;
35			reg = <0x40078100 0x100>;
36			#pwm-cells = <3>;
37			status = "disabled";
38		};
39
40		pwm2: pwm2@40078200 {
41			compatible = "renesas,ra-pwm";
42			divider = <RA_PWM_SOURCE_DIV_1>;
43			channel = <RA_PWM_CHANNEL_2>;
44			clocks = <&pclkd MSTPD 6>;
45			reg = <0x40078200 0x100>;
46			#pwm-cells = <3>;
47			status = "disabled";
48		};
49
50		pwm3: pwm3@40078300 {
51			compatible = "renesas,ra-pwm";
52			divider = <RA_PWM_SOURCE_DIV_1>;
53			channel = <RA_PWM_CHANNEL_3>;
54			clocks = <&pclkd MSTPD 6>;
55			reg = <0x40078300 0x100>;
56			#pwm-cells = <3>;
57			status = "disabled";
58		};
59
60		pwm4: pwm4@40078400 {
61			compatible = "renesas,ra-pwm";
62			divider = <RA_PWM_SOURCE_DIV_1>;
63			channel = <RA_PWM_CHANNEL_4>;
64			clocks = <&pclkd MSTPD 6>;
65			reg = <0x40078400 0x100>;
66			#pwm-cells = <3>;
67			status = "disabled";
68		};
69
70		pwm5: pwm5@40078500 {
71			compatible = "renesas,ra-pwm";
72			divider = <RA_PWM_SOURCE_DIV_1>;
73			channel = <RA_PWM_CHANNEL_5>;
74			clocks = <&pclkd MSTPD 6>;
75			reg = <0x40078500 0x100>;
76			#pwm-cells = <3>;
77			status = "disabled";
78		};
79
80		pwm6: pwm6@40078600 {
81			compatible = "renesas,ra-pwm";
82			divider = <RA_PWM_SOURCE_DIV_1>;
83			channel = <RA_PWM_CHANNEL_6>;
84			clocks = <&pclkd MSTPD 6>;
85			reg = <0x40078600 0x100>;
86			#pwm-cells = <3>;
87			status = "disabled";
88		};
89
90		trng: trng {
91			compatible = "renesas,ra-trng";
92			status = "disabled";
93		};
94	};
95
96	clocks: clocks {
97		#address-cells = <1>;
98		#size-cells = <1>;
99
100		xtal: clock-main-osc {
101			compatible = "renesas,ra-cgc-external-clock";
102			clock-frequency = <DT_FREQ_M(12)>;
103			#clock-cells = <0>;
104			status = "disabled";
105		};
106
107		hoco: clock-hoco {
108			compatible = "fixed-clock";
109			clock-frequency = <DT_FREQ_M(48)>;
110			#clock-cells = <0>;
111		};
112
113		moco: clock-moco {
114			compatible = "fixed-clock";
115			clock-frequency = <DT_FREQ_M(8)>;
116			#clock-cells = <0>;
117		};
118
119		loco: clock-loco {
120			compatible = "fixed-clock";
121			clock-frequency = <32768>;
122			#clock-cells = <0>;
123		};
124
125		subclk: clock-subclk {
126			compatible = "renesas,ra-cgc-subclk";
127			clock-frequency = <32768>;
128			#clock-cells = <0>;
129			status = "disabled";
130		};
131
132		pclkblock: pclkblock@4001e01c {
133			compatible = "renesas,ra-cgc-pclk-block";
134			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
135			      <0x40047008 4>;
136			reg-names = "MSTPA", "MSTPB","MSTPC",
137				    "MSTPD";
138			#clock-cells = <0>;
139			clocks = <&hoco>;
140			status = "okay";
141
142			iclk: iclk {
143				compatible = "renesas,ra-cgc-pclk";
144				div = <1>;
145				#clock-cells = <2>;
146				status = "okay";
147			};
148
149			pclkb: pclkb {
150				compatible = "renesas,ra-cgc-pclk";
151				div = <2>;
152				#clock-cells = <2>;
153				status = "okay";
154			};
155
156			pclkd: pclkd {
157				compatible = "renesas,ra-cgc-pclk";
158				div = <1>;
159				#clock-cells = <2>;
160				status = "okay";
161			};
162
163			fclk: fclk {
164				compatible = "renesas,ra-cgc-pclk";
165				div = <1>;
166				#clock-cells = <2>;
167				status = "okay";
168			};
169
170			clkout: clkout {
171				compatible = "renesas,ra-cgc-pclk";
172				#clock-cells = <2>;
173				status = "disabled";
174			};
175
176
177			sdadcclk: sdadcclk {
178				compatible = "renesas,ra-cgc-pclk";
179				#clock-cells = <2>;
180				status = "disabled";
181			};
182		};
183	};
184};
185
186&ioport0 {
187	port-irqs = <&port_irq0 &port_irq4>;
188	port-irq-names = "port-irq0",
189			 "port-irq4";
190	port-irq0-pins = <1>;
191	port-irq4-pins = <0>;
192};
193
194&ioport1 {
195	port-irqs = <&port_irq2 &port_irq3 &port_irq4
196	&port_irq5 &port_irq6 &port_irq7>;
197	port-irq-names = "port-irq2",
198			 "port-irq3",
199			 "port-irq4",
200			 "port-irq5",
201			 "port-irq6",
202			 "port-irq7";
203	port-irq2-pins = <10>;
204	port-irq3-pins = <9>;
205	port-irq4-pins = <0>;
206	port-irq5-pins = <1>;
207	port-irq6-pins = <4 11>;
208	port-irq7-pins = <5 12>;
209};
210
211&ioport2 {
212	port-irqs = <&port_irq0 &port_irq2 &port_irq3
213	&port_irq6>;
214	port-irq-names = "port-irq0",
215			 "port-irq2",
216			 "port-irq3",
217			 "port-irq6";
218	port-irq0-pins = <5>;
219	port-irq2-pins = <13>;
220	port-irq3-pins = <12>;
221	port-irq6-pins = <6>;
222};
223
224&ioport3 {
225	port-irqs = <&port_irq4 &port_irq5>;
226	port-irq-names = "port-irq4",
227			 "port-irq5";
228	port-irq4-pins = <2>;
229	port-irq5-pins = <1>;
230};
231
232&ioport4 {
233	port-irqs = <&port_irq0 &port_irq1 &port_irq5
234	&port_irq7>;
235	port-irq-names = "port-irq0",
236			 "port-irq1",
237			 "port-irq5",
238			 "port-irq7";
239	port-irq0-pins = <0>;
240	port-irq1-pins = <7 8>;
241	port-irq5-pins = <1>;
242	port-irq7-pins = <9>;
243};
244
245&ioport5 {
246	port-irqs = <&port_irq1 &port_irq2 &port_irq3>;
247	port-irq-names = "port-irq1",
248			 "port-irq2",
249			 "port-irq3";
250	port-irq1-pins = <2>;
251	port-irq2-pins = <1>;
252	port-irq3-pins = <0>;
253};
254