1/*
2 * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <freq.h>
9#include <arm/armv7-m.dtsi>
10#include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
11#include <zephyr/dt-bindings/clock/ra_clock.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu@0 {
19			device_type = "cpu";
20			compatible = "arm,cortex-m4";
21			reg = <0>;
22		};
23	};
24
25	clocks: clocks {
26		xtal: clock-main-osc {
27			compatible = "renesas,ra-cgc-external-clock";
28			clock-frequency = <1200000>;
29			status = "disabled";
30			#clock-cells = <0>;
31		};
32
33		subclk: clock-subclk {
34			compatible = "renesas,ra-cgc-subclk";
35			clock-frequency = <32768>;
36			status = "disabled";
37			#clock-cells = <0>;
38		};
39
40		hoco: clock-hoco {
41			compatible = "fixed-clock";
42			clock-frequency = <24000000>;
43			status = "okay";
44			#clock-cells = <0>;
45		};
46
47		moco: clock-moco {
48			compatible = "fixed-clock";
49			clock-frequency = <8000000>;
50			status = "okay";
51			#clock-cells = <0>;
52		};
53
54		loco: clock-loco {
55			compatible = "fixed-clock";
56			clock-frequency = <32768>;
57			status = "okay";
58			#clock-cells = <0>;
59		};
60
61		pll: pll {
62			compatible = "renesas,ra-cgc-pll";
63			#clock-cells = <0>;
64
65			/* PLL */
66			clocks = <&xtal>;
67			div = <2>;
68			mul = <8 0>;
69			status = "disabled";
70		};
71	};
72
73	sram0: memory0@20000000 {
74		compatible = "mmio-sram";
75		reg = <0x20000000 DT_SIZE_K(32)>;
76	};
77
78	soc {
79		interrupt-parent = <&icu>;
80		icu: interrupt-controller@40006000 {
81			compatible = "renesas,ra-interrupt-controller-unit";
82			reg = <0x40006000 0x40>;
83			reg-names = "icu";
84			interrupt-controller;
85			#interrupt-cells = <3>;
86		};
87
88		pclkblock: pclkblock@4001e01c {
89			compatible = "renesas,ra-cgc-pclk-block";
90			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
91			      <0x40047008 4>;
92			reg-names = "MSTPA", "MSTPB","MSTPC",
93				    "MSTPD";
94			compatible = "renesas,ra-cgc-pclk-block";
95			#clock-cells = <0>;
96			clocks = <&moco>;
97			status = "okay";
98
99			iclk: iclk {
100				compatible = "renesas,ra-cgc-pclk";
101				div = <16>;
102				#clock-cells = <2>;
103				status = "okay";
104			};
105
106			pclka: pclka {
107				compatible = "renesas,ra-cgc-pclk";
108				div = <16>;
109				#clock-cells = <2>;
110				status = "okay";
111			};
112
113			pclkb: pclkb {
114				compatible = "renesas,ra-cgc-pclk";
115				div = <16>;
116				#clock-cells = <2>;
117				status = "okay";
118			};
119
120			pclkc: pclkc {
121				compatible = "renesas,ra-cgc-pclk";
122				div = <1>;
123				#clock-cells = <2>;
124				status = "okay";
125			};
126
127			pclkd: pclkd {
128				compatible = "renesas,ra-cgc-pclk";
129				div = <16>;
130				#clock-cells = <2>;
131				status = "okay";
132			};
133
134			fclk: fclk {
135				compatible = "renesas,ra-cgc-pclk";
136				div = <16>;
137				#clock-cells = <2>;
138				status = "okay";
139			};
140
141			clkout: clkout {
142				compatible = "renesas,ra-cgc-pclk";
143				#clock-cells = <2>;
144				status = "disabled";
145			};
146		};
147
148		fcu: flash-controller@4001c000 {
149			compatible = "renesas,ra-flash-controller";
150			reg = <0x4001c000 0x44>;
151			reg-names = "fcache";
152
153			#address-cells = <1>;
154			#size-cells = <1>;
155
156			flash0: flash0@0 {
157				compatible = "soc-nv-flash";
158				reg = <0x00000000 DT_SIZE_K(256)>;
159			};
160
161			flash1: flash1@40100000 {
162				compatible = "soc-nv-flash";
163				reg = <0x40100000 DT_SIZE_K(8)>;
164			};
165		};
166
167		ioport0: gpio@40040000 {
168			compatible = "renesas,ra-gpio";
169			reg = <0x40040000 0x20>;
170			gpio-controller;
171			#gpio-cells = <2>;
172			ngpios = <16>;
173			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
174				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>,
175				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
176				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ7>,
177				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ10>,
178				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ15>;
179			interrupt-names = "port-irq2", "port-irq3", "port-irq6",
180					  "port-irq7", "port-irq10", "port-irq15";
181			port-irq2-pins = <2>;
182			port-irq3-pins = <4>;
183			port-irq6-pins = <0>;
184			port-irq7-pins = <1 15>;
185			port-irq10-pins = <5>;
186			port-irq15-pins = <11>;
187			status = "disabled";
188		};
189
190		ioport1: gpio@40040020 {
191			compatible = "renesas,ra-gpio";
192			reg = <0x40040020 0x20>;
193			gpio-controller;
194			#gpio-cells = <2>;
195			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
196				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ1>,
197				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
198				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>,
199				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ4>;
200			interrupt-names = "port-irq0", "port-irq1", "port-irq2",
201					  "port-irq3", "port-irq4";
202			port-irq0-pins = <5>;
203			port-irq1-pins = <1>;
204			port-irq2-pins = <0>;
205			port-irq3-pins = <10>;
206			port-irq4-pins = <11>;
207			ngpios = <16>;
208			status = "disabled";
209		};
210
211		ioport2: gpio@40040040 {
212			compatible = "renesas,ra-gpio";
213			reg = <0x40040040 0x20>;
214			gpio-controller;
215			#gpio-cells = <2>;
216			ngpios = <16>;
217			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
218				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ1>,
219				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
220				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>;
221			interrupt-names = "port-irq0", "port-irq1", "port-irq2",
222					  "port-irq3";
223			port-irq0-pins = <6>;
224			port-irq1-pins = <5>;
225			port-irq2-pins = <13>;
226			port-irq3-pins = <12>;
227			status = "disabled";
228		};
229
230		ioport3: gpio@40040060 {
231			compatible = "renesas,ra-gpio";
232			reg = <0x40040060 0x20>;
233			gpio-controller;
234			#gpio-cells = <2>;
235			ngpios = <16>;
236			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ5>,
237				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
238				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ8>,
239				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ9>;
240			interrupt-names = "port-irq5", "port-irq6", "port-irq8", "port-irq9";
241			port-irq5-pins = <2>;
242			port-irq6-pins = <1>;
243			port-irq8-pins = <5>;
244			port-irq9-pins = <4>;
245			status = "disabled";
246		};
247
248		ioport4: gpio@40040080 {
249			compatible = "renesas,ra-gpio";
250			reg = <0x40040080 0x20>;
251			gpio-controller;
252			#gpio-cells = <2>;
253			ngpios = <16>;
254			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
255				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ4>,
256				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ5>,
257				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
258				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ7>,
259				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ8>,
260				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ9>;
261			interrupt-names = "port-irq0", "port-irq4", "port-irq5", "port-irq6",
262					  "port-irq7", "port-irq8", "port-irq9";
263			port-irq0-pins = <0>;
264			port-irq4-pins = <2 11>;
265			port-irq5-pins = <1 10>;
266			port-irq6-pins = <9>;
267			port-irq7-pins = <8>;
268			port-irq8-pins = <15>;
269			port-irq9-pins = <14>;
270			status = "disabled";
271		};
272
273		ioport5: gpio@400400a0 {
274			compatible = "renesas,ra-gpio";
275			reg = <0x400400a0 0x20>;
276			gpio-controller;
277			#gpio-cells = <2>;
278			ngpios = <16>;
279			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ11>,
280				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ12>,
281				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ14>;
282			interrupt-names = "port-irq11", "port-irq12", "port-irq14";
283			port-irq11-pins = <1>;
284			port-irq12-pins = <2>;
285			port-irq14-pins = <5>;
286			status = "disabled";
287		};
288
289		pinctrl: pinctrl@40040800 {
290			compatible = "renesas,ra-pinctrl-pfs";
291			reg = <0x40040800 0x500 0x40040d03 0x1>;
292			reg-names = "pfs", "pmisc_pwpr";
293			status = "okay";
294		};
295
296		sci0: sci@40070000 {
297			compatible = "renesas,ra-sci";
298			reg = <0x40070000 0x20>;
299			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI>,
300				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_TXI>,
301				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_TEI>,
302				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_ERI>,
303				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_AM>,
304				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI_OR_ERI>;
305			interrupt-names = "rxi", "txi", "tei", "eri", "am", "rxi-or-eri";
306			clocks = <&pclka MSTPB 31>;
307			#clock-cells = <1>;
308			status = "disabled";
309			uart {
310				compatible = "renesas,ra-uart-sci";
311				status = "disabled";
312			};
313		};
314
315		sci1: sci@40070020 {
316			compatible = "renesas,ra-sci";
317			reg = <0x40070020 0x20>;
318			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_RXI>,
319				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_TXI>,
320				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_TEI>,
321				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_ERI>,
322				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_AM>;
323			interrupt-names = "rxi", "txi", "tei", "eri", "am";
324			clocks = <&pclka MSTPB 30>;
325			#clock-cells = <1>;
326			status = "disabled";
327			uart {
328				compatible = "renesas,ra-uart-sci";
329				status = "disabled";
330			};
331		};
332
333		sci9: sci@40070120 {
334			compatible = "renesas,ra-sci";
335			reg = <0x40070120 0x20>;
336			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_RXI>,
337				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_TXI>,
338				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_TEI>,
339				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_ERI>,
340				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_AM>;
341			interrupt-names = "rxi", "txi", "tei", "eri", "am";
342			clocks = <&pclka MSTPB 22>;
343			#clock-cells = <1>;
344			status = "disabled";
345			uart {
346				compatible = "renesas,ra-uart-sci";
347				status = "disabled";
348			};
349		};
350	};
351};
352
353&nvic {
354	arm,num-irq-priority-bits = <4>;
355};
356