1/*
2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	compatible = "litex,vexriscv", "litex-dev";
13	model = "litex,vexriscv";
14
15
16	chosen {
17		zephyr,entropy = &prbs0;
18	};
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23		cpu0: cpu@0 {
24			clock-frequency = <100000000>;
25			compatible = "litex,vexriscv-standard", "riscv";
26			device_type = "cpu";
27			reg = <0>;
28			riscv,isa = "rv32im_zicsr_zifencei";
29			status = "okay";
30		};
31	};
32	soc {
33		#address-cells = <1>;
34		#size-cells = <1>;
35		compatible = "litex,vexriscv";
36		ranges;
37		ctrl0: soc_controller@e0000000 {
38			compatible = "litex,soc-controller";
39			reg = <0xe0000000 0x4
40				0xe0000004 0x4
41				0xe0000008 0x4>;
42			reg-names = "reset",
43				"scratch",
44				"bus_errors";
45		};
46		intc0: interrupt-controller@bc0 {
47			compatible = "litex,vexriscv-intc0";
48			#address-cells = <0>;
49			#interrupt-cells = <2>;
50			interrupt-controller;
51			reg = <0xbc0 0x4 0xfc0 0x4>;
52			reg-names = "irq_mask", "irq_pending";
53			riscv,max-priority = <7>;
54		};
55		uart0: serial@e0001800 {
56			compatible = "litex,uart";
57			interrupt-parent = <&intc0>;
58			interrupts = <2 10>;
59			reg = <0xe0001800 0x4
60				0xe0001804 0x4
61				0xe0001808 0x4
62				0xe000180c 0x4
63				0xe0001810 0x4
64				0xe0001814 0x4
65				0xe0001818 0x4
66				0xe000181c 0x4>;
67			reg-names =
68				"rxtx",
69				"txfull",
70				"rxempty",
71				"ev_status",
72				"ev_pending",
73				"ev_enable",
74				"txempty",
75				"rxfull";
76			status = "disabled";
77		};
78		spi0: spi@e0002000 {
79			compatible = "litex,spi";
80			reg = <0xe0002000 0x4
81				0xe0002004 0x4
82				0xe0002008 0x4
83				0xe000200c 0x4
84				0xe0002010 0x4
85				0xe0002014 0x4>;
86			reg-names = "control",
87				"status",
88				"mosi",
89				"miso",
90				"cs",
91				"loopback";
92			status = "disabled";
93			#address-cells = <1>;
94			#size-cells = <0>;
95		};
96		spi1: spi@e000c000 {
97			compatible = "litex,spi-litespi";
98			reg = <0xe000c000 0x4>,
99				<0xe000c004 0x4>,
100				<0xe000c008 0x4>,
101				<0xe000c00c 0x4>,
102				<0xe000c010 0x4>,
103				<0xe000c800 0x4>,
104				<0x60000000 0x1000000>;
105			reg-names = "core_mmap_dummy_bits",
106				"core_master_cs",
107				"core_master_phyconfig",
108				"core_master_rxtx",
109				"core_master_status",
110				"phy_clk_divisor",
111				"flash_mmap";
112			#address-cells = <1>;
113			#size-cells = <0>;
114			spiflash0: flash@0 {
115				compatible = "jedec,spi-nor";
116				reg = <0>;
117				spi-max-frequency = <10000000>;
118			};
119		};
120		timer0: timer@e0002800 {
121			compatible = "litex,timer0";
122			interrupt-parent = <&intc0>;
123			interrupts = <1 0>;
124			reg = <0xe0002800 0x4
125				0xe0002804 0x4
126				0xe0002808 0x4
127				0xe000280c 0x4
128				0xe0002810 0x4
129				0xe0002814 0x4
130				0xe0002818 0x4
131				0xe000281c 0x4
132				0xe0002820 0x4
133				0xe0002824 0x8>;
134			reg-names =
135				"load",
136				"reload",
137				"en",
138				"update_value",
139				"value",
140				"ev_status",
141				"ev_pending",
142				"ev_enable",
143				"uptime_latch",
144				"uptime_cycles";
145			status = "disabled";
146		};
147		wdt0: watchdog@e000d000 {
148			compatible = "litex,watchdog";
149			interrupt-parent = <&intc0>;
150			reg = <0xe000d000 0x4>,
151				<0xe000d004 0x4>,
152				<0xe000d008 0x4>,
153				<0xe000d00c 0x4>,
154				<0xe000d010 0x4>,
155				<0xe000d014 0x4>;
156			reg-names = "control",
157				"cycles",
158				"remaining",
159				"ev_status",
160				"ev_pending",
161				"ev_enable";
162			interrupts = <8 15>;
163		};
164		mdio0: mdio@e0008000 {
165			compatible = "litex,liteeth-mdio";
166			reg = <0xe0008000 0x4>,
167				<0xe0008004 0x4>,
168				<0xe0008008 0x4>;
169			reg-names = "crg_reset",
170				"mdio_w",
171				"mdio_r";
172			#address-cells = <1>;
173			#size-cells = <0>;
174			status = "disabled";
175
176			phy0: ethernet-phy@1 {
177				compatible = "ethernet-phy";
178				reg = <1>;
179			};
180		};
181		eth0: ethernet@e0009800 {
182			compatible = "litex,liteeth";
183			interrupt-parent = <&intc0>;
184			interrupts = <3 0>;
185			reg = <0xe0009800 0x4
186				0xe0009804 0x4
187				0xe0009808 0x4
188				0xe000980c 0x4
189				0xe0009810 0x4
190				0xe0009814 0x4
191				0xe0009818 0x4
192				0xe000981c 0x4
193				0xe0009820 0x4
194				0xe0009824 0x4
195				0xe0009828 0x4
196				0xe000982c 0x4
197				0xe0009830 0x4
198				0xe0009834 0x4
199				0xb0000000 0x2000>;
200			local-mac-address = [10 e2 d5 00 00 02];
201			reg-names = "rx_slot",
202				"rx_length",
203				"rx_errors",
204				"rx_ev_status",
205				"rx_ev_pending",
206				"rx_ev_enable",
207				"tx_start",
208				"tx_ready",
209				"tx_level",
210				"tx_slot",
211				"tx_length",
212				"tx_ev_status",
213				"tx_ev_pending",
214				"tx_ev_enable",
215				"buffers";
216			phy-handle = <&phy0>;
217			status = "disabled";
218		};
219		dna0: dna@e0003800 {
220			compatible = "litex,dna0";
221			/* DNA data is 57-bits long,
222			so it requires 8 bytes.
223			In LiteX each 32-bit register holds
224			only a single byte of meaningful data,
225			hence 8 registers. */
226			reg = <0xe0003800 0x20>;
227			reg-names = "mem";
228			status = "disabled";
229		};
230		i2c0: i2c@e0005000 {
231			compatible = "litex,i2c";
232			reg = <0xe0005000 0x4 0xe0005004 0x4>;
233			reg-names = "write", "read";
234			clock-frequency = <I2C_BITRATE_STANDARD>;
235			#address-cells = <1>;
236			#size-cells = <0>;
237			status = "disabled";
238		};
239		gpio_out: gpio@e0005800 {
240			compatible = "litex,gpio";
241			reg = <0xe0005800 0x4>;
242			reg-names = "control";
243			ngpios = <4>;
244			port-is-output;
245			status = "disabled";
246			gpio-controller;
247			#gpio-cells = <2>;
248		};
249		gpio_in: gpio@e0006000 {
250			compatible = "litex,gpio";
251			reg = <0xe0006000 0x4
252				0xe0006004 0x4
253				0xe0006008 0x4
254				0xe0006010 0x4
255				0xe0006014 0x4>;
256			interrupt-parent = <&intc0>;
257			interrupts = <4 2>;
258			reg-names = "base",
259				"irq_mode",
260				"irq_edge",
261				"irq_pend",
262				"irq_en";
263			ngpios = <4>;
264			status = "disabled";
265			gpio-controller;
266			#gpio-cells = <2>;
267		};
268		prbs0: prbs@e0006800 {
269			compatible = "litex,prbs";
270			reg = <0xe0006800 0x4>;
271			reg-names = "status";
272			status = "disabled";
273		};
274		pwm0: pwm@e0007000 {
275			compatible = "litex,pwm";
276			reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>;
277			reg-names = "enable", "width", "period";
278			status = "disabled";
279			#pwm-cells = <2>;
280		};
281		i2s_rx: i2s_rx@e000a800 {
282			compatible = "litex,i2s";
283			reg = <0xe000a800 0x4
284				0xe000a804 0x4
285				0xe000a808 0x4
286				0xe000a80c 0x4
287				0xe000a810 0x4
288				0xe000a814 0x4
289				0xb1000000 0x40000>;
290			interrupt-parent = <&intc0>;
291			interrupts = <6 2>;
292			#address-cells = <1>;
293			#size-cells = <0>;
294			reg-names = "ev_status",
295				"ev_pending",
296				"ev_enable",
297				"rx_ctl",
298				"rx_stat",
299				"rx_conf",
300				"fifo";
301			fifo_depth = <256>;
302			status = "disabled";
303		};
304		i2s_tx: i2s_tx@e000b000 {
305			compatible = "litex,i2s";
306			reg = <0xe000b000 0x4
307				0xe000b004 0x4
308				0xe000b008 0x4
309				0xe000b00c 0x4
310				0xe000b010 0x4
311				0xe000b014 0x4
312				0xb2000000 0x40000>;
313			interrupt-parent = <&intc0>;
314			interrupts = <7 2>;
315			#address-cells = <1>;
316			#size-cells = <0>;
317			reg-names = "ev_status",
318				"ev_pending",
319				"ev_enable",
320				"tx_ctl",
321				"tx_stat",
322				"tx_conf",
323				"fifo";
324			fifo_depth = <256>;
325			status = "disabled";
326		};
327		clock-outputs {
328			#address-cells = <1>;
329			#size-cells = <0>;
330			clk0: clock-controller@0 {
331				#clock-cells = <1>;
332				reg = <0>;
333				compatible = "litex,clkout";
334				clock-output-names = "CLK_0";
335				litex,clock-frequency = <11289600>;
336				litex,clock-phase = <0>;
337				litex,clock-duty-num = <1>;
338				litex,clock-duty-den = <2>;
339				litex,clock-margin = <1>;
340				litex,clock-margin-exp = <2>;
341				status = "disabled";
342			};
343			clk1: clock-controller@1 {
344				#clock-cells = <1>;
345				reg = <1>;
346				compatible = "litex,clkout";
347				clock-output-names = "CLK_1";
348				litex,clock-frequency = <22579200>;
349				litex,clock-phase = <0>;
350				litex,clock-duty-num = <1>;
351				litex,clock-duty-den = <2>;
352				litex,clock-margin = <1>;
353				litex,clock-margin-exp = <2>;
354				status = "disabled";
355			};
356		};
357		clock0: clock@e0004800 {
358			compatible = "litex,clk";
359			reg = <0xe0004800 0x4
360				0xe0004804 0x4
361				0xe0004808 0x4
362				0xe000480c 0x4
363				0xe0004810 0x4
364				0xe0004814 0x4
365				0xe0004818 0x4
366				0xe000481c 0x4>;
367			reg-names = "drp_reset",
368				"drp_locked",
369				"drp_read",
370				"drp_write",
371				"drp_drdy",
372				"drp_adr",
373				"drp_dat_w",
374				"drp_dat_r";
375			#clock-cells = <1>;
376			clocks = <&clk0 0>, <&clk1 1>;
377			clock-output-names = "CLK_0", "CLK_1";
378			litex,lock-timeout = <10>;
379			litex,drdy-timeout = <10>;
380			litex,divclk-divide-min = <1>;
381			litex,divclk-divide-max = <107>;
382			litex,clkfbout-mult-min = <2>;
383			litex,clkfbout-mult-max = <65>;
384			litex,vco-freq-min = <600000000>;
385			litex,vco-freq-max = <1200000000>;
386			litex,clkout-divide-min = <1>;
387			litex,clkout-divide-max = <126>;
388			litex,vco-margin = <0>;
389			status = "disabled";
390		};
391	};
392};
393