1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/ {
12	soc {
13		sram0: memory@1ffe0000 {
14			compatible = "mmio-sram";
15			reg = <0x1ffe0000 DT_SIZE_K(384)>;
16		};
17
18		sci5: sci5@400700a0 {
19			compatible = "renesas,ra-sci";
20			interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
21			interrupt-names = "rxi", "txi", "tei", "eri";
22			reg = <0x400700a0 0x20>;
23			clocks = <&pclka MSTPB 26>;
24			status = "disabled";
25			uart {
26				compatible = "renesas,ra-sci-uart";
27				channel = <5>;
28				status = "disabled";
29			};
30		};
31
32		sci6: sci6@400700c0 {
33			compatible = "renesas,ra-sci";
34			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
35			interrupt-names = "rxi", "txi", "tei", "eri";
36			reg = <0x400700c0 0x20>;
37			clocks = <&pclka MSTPB 25>;
38			status = "disabled";
39			uart {
40				compatible = "renesas,ra-sci-uart";
41				channel = <6>;
42				status = "disabled";
43			};
44		};
45
46		sci7: sci7@400700e0 {
47			compatible = "renesas,ra-sci";
48			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
49			interrupt-names = "rxi", "txi", "tei", "eri";
50			reg = <0x400700e0 0x20>;
51			clocks = <&pclka MSTPB 24>;
52			status = "disabled";
53			uart {
54				compatible = "renesas,ra-sci-uart";
55				channel = <7>;
56				status = "disabled";
57			};
58		};
59
60		iic2: iic2@40053200 {
61			compatible = "renesas,ra-iic";
62			channel = <2>;
63			reg = <0x40053200 0x100>;
64			status = "disabled";
65		};
66
67		adc@4005c000 {
68			channel-count = <13>;
69			channel-available-mask = <0x1f00ff>;
70		};
71
72		adc@4005c200 {
73			channel-count = <9>;
74			channel-available-mask = <0x700e7>;
75		};
76
77		pwm13: pwm13@40078d00 {
78			compatible = "renesas,ra-pwm";
79			divider = <RA_PWM_SOURCE_DIV_1>;
80			channel = <RA_PWM_CHANNEL_13>;
81			clocks = <&pclkd MSTPD 6>;
82			reg = <0x40078d00 0x100>;
83			#pwm-cells = <3>;
84			status = "disabled";
85		};
86	};
87
88	clocks: clocks {
89		#address-cells = <1>;
90		#size-cells = <1>;
91
92		xtal: clock-main-osc {
93			compatible = "renesas,ra-cgc-external-clock";
94			clock-frequency = <DT_FREQ_M(12)>;
95			#clock-cells = <0>;
96			status = "disabled";
97		};
98
99		hoco: clock-hoco {
100			compatible = "fixed-clock";
101			clock-frequency = <DT_FREQ_M(20)>;
102			#clock-cells = <0>;
103		};
104
105		moco: clock-moco {
106			compatible = "fixed-clock";
107			clock-frequency = <DT_FREQ_M(8)>;
108			#clock-cells = <0>;
109		};
110
111		loco: clock-loco {
112			compatible = "fixed-clock";
113			clock-frequency = <32768>;
114			#clock-cells = <0>;
115		};
116
117		subclk: clock-subclk {
118			compatible = "renesas,ra-cgc-subclk";
119			clock-frequency = <32768>;
120			#clock-cells = <0>;
121			status = "disabled";
122		};
123
124		pll: pll {
125			compatible = "renesas,ra-cgc-pll";
126			#clock-cells = <0>;
127
128			/* PLL */
129			clocks = <&xtal>;
130			div = <1>;
131			mul = <20 0>;
132			status = "disabled";
133		};
134
135		pclkblock: pclkblock@4001e01c {
136			compatible = "renesas,ra-cgc-pclk-block";
137			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
138			      <0x40047008 4>;
139			reg-names = "MSTPA", "MSTPB","MSTPC",
140				    "MSTPD";
141			#clock-cells = <0>;
142			clocks = <&pll>;
143			status = "okay";
144
145			iclk: iclk {
146				compatible = "renesas,ra-cgc-pclk";
147				div = <2>;
148				#clock-cells = <2>;
149				status = "okay";
150			};
151
152			pclka: pclka {
153				compatible = "renesas,ra-cgc-pclk";
154				div = <2>;
155				#clock-cells = <2>;
156				status = "okay";
157			};
158
159			pclkb: pclkb {
160				compatible = "renesas,ra-cgc-pclk";
161				div = <4>;
162				#clock-cells = <2>;
163				status = "okay";
164			};
165
166			pclkc: pclkc {
167				compatible = "renesas,ra-cgc-pclk";
168				div = <4>;
169				#clock-cells = <2>;
170				status = "okay";
171			};
172
173			pclkd: pclkd {
174				compatible = "renesas,ra-cgc-pclk";
175				div = <2>;
176				#clock-cells = <2>;
177				status = "okay";
178			};
179
180			bclk: bclk {
181				compatible = "renesas,ra-cgc-pclk";
182				div = <2>;
183				bclkout: bclkout {
184					compatible = "renesas,ra-cgc-busclk";
185					clk-out-div = <2>;
186					sdclk = <1>;
187					#clock-cells = <0>;
188				};
189				#clock-cells = <2>;
190				status = "okay";
191			};
192
193			uclk: uclk {
194				compatible = "renesas,ra-cgc-pclk";
195				div = <5>;
196				#clock-cells = <2>;
197				status = "okay";
198			};
199
200			fclk: fclk {
201				compatible = "renesas,ra-cgc-pclk";
202				div = <4>;
203				#clock-cells = <2>;
204				status = "okay";
205			};
206
207			clkout: clkout {
208				compatible = "renesas,ra-cgc-pclk";
209				#clock-cells = <2>;
210				status = "disabled";
211			};
212		};
213	};
214};
215
216&ioport0 {
217	port-irqs = <&port_irq6 &port_irq7 &port_irq8
218	&port_irq9 &port_irq10 &port_irq11
219	&port_irq12 &port_irq13>;
220	port-irq-names = "port-irq6",
221			 "port-irq7",
222			 "port-irq8",
223			 "port-irq9",
224			 "port-irq10",
225			 "port-irq11",
226			 "port-irq12",
227			 "port-irq13";
228	port-irq6-pins = <0>;
229	port-irq7-pins = <1>;
230	port-irq8-pins = <2>;
231	port-irq9-pins = <4>;
232	port-irq10-pins = <5>;
233	port-irq11-pins = <6>;
234	port-irq12-pins = <8>;
235	port-irq13-pins = <9 15>;
236};
237
238&ioport1 {
239	port-irqs = <&port_irq0 &port_irq1 &port_irq2
240	&port_irq3 &port_irq4>;
241	port-irq-names = "port-irq0",
242			 "port-irq1",
243			 "port-irq2",
244			 "port-irq3",
245			 "port-irq4";
246	port-irq0-pins = <5>;
247	port-irq1-pins = <1 4>;
248	port-irq2-pins = <0>;
249	port-irq3-pins = <10>;
250	port-irq4-pins = <11>;
251};
252
253&ioport2 {
254	port-irqs = <&port_irq0 &port_irq1 &port_irq2
255	&port_irq3>;
256	port-irq-names = "port-irq0",
257			 "port-irq1",
258			 "port-irq2",
259			 "port-irq3";
260	port-irq0-pins = <6>;
261	port-irq1-pins = <5>;
262	port-irq2-pins = <3 13>;
263	port-irq3-pins = <2 12>;
264};
265
266&ioport3 {
267	port-irqs = <&port_irq5 &port_irq6
268	&port_irq8 &port_irq9>;
269	port-irq-names = "port-irq5",
270			 "port-irq6",
271			 "port-irq8",
272			 "port-irq9";
273	port-irq5-pins = <2>;
274	port-irq6-pins = <1>;
275	port-irq8-pins = <5>;
276	port-irq9-pins = <4>;
277};
278
279&ioport4 {
280	port-irqs = <&port_irq0 &port_irq4 &port_irq5
281	&port_irq6 &port_irq7 &port_irq8
282	&port_irq9>;
283	port-irq-names = "port-irq0",
284			 "port-irq4",
285			 "port-irq5",
286			 "port-irq6",
287			 "port-irq7",
288			 "port-irq8",
289			 "port-irq9";
290	port-irq0-pins = <0>;
291	port-irq4-pins = <2 11>;
292	port-irq5-pins = <1 10>;
293	port-irq6-pins = <9>;
294	port-irq7-pins = <8>;
295	port-irq8-pins = <15>;
296	port-irq9-pins = <14>;
297};
298
299&ioport5 {
300	port-irqs = <&port_irq11 &port_irq12 &port_irq14
301	&port_irq15>;
302	port-irq-names = "port-irq11",
303			 "port-irq12",
304			 "port-irq14",
305			 "port-irq15";
306	port-irq11-pins = <1>;
307	port-irq12-pins = <2>;
308	port-irq14-pins = <5 12>;
309	port-irq15-pins = <6 11>;
310};
311
312&ioport7 {
313	port-irqs = <&port_irq10 &port_irq11>;
314	port-irq-names = "port-irq10",
315			 "port-irq11";
316	port-irq10-pins = <9>;
317	port-irq11-pins = <8>;
318};
319