1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/ {
12	soc {
13		sram0: memory@1ffe0000 {
14			compatible = "mmio-sram";
15			reg = <0x1ffe0000 DT_SIZE_K(640)>;
16		};
17
18		ioport8: gpio@40040100 {
19			compatible = "renesas,ra-gpio-ioport";
20			reg = <0x40040100 0x20>;
21			port = <8>;
22			gpio-controller;
23			#gpio-cells = <2>;
24			ngpios = <16>;
25			status = "disabled";
26		};
27
28		ioport9: gpio@40040120 {
29			compatible = "renesas,ra-gpio-ioport";
30			reg = <0x40040120 0x20>;
31			port = <9>;
32			gpio-controller;
33			#gpio-cells = <2>;
34			ngpios = <16>;
35			status = "disabled";
36		};
37
38		ioporta: gpio@40040140 {
39			compatible = "renesas,ra-gpio-ioport";
40			reg = <0x40040140 0x20>;
41			port = <10>;
42			gpio-controller;
43			#gpio-cells = <2>;
44			ngpios = <16>;
45			status = "disabled";
46		};
47
48		ioportb: gpio@40040160 {
49			compatible = "renesas,ra-gpio-ioport";
50			reg = <0x40040160 0x20>;
51			port = <11>;
52			gpio-controller;
53			#gpio-cells = <2>;
54			ngpios = <16>;
55			status = "disabled";
56		};
57
58		sci5: sci5@400700a0 {
59			compatible = "renesas,ra-sci";
60			interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
61			interrupt-names = "rxi", "txi", "tei", "eri";
62			reg = <0x400700a0 0x20>;
63			clocks = <&pclka MSTPB 26>;
64			status = "disabled";
65			uart {
66				compatible = "renesas,ra-sci-uart";
67				channel = <5>;
68				status = "disabled";
69			};
70		};
71
72		sci6: sci6@400700c0 {
73			compatible = "renesas,ra-sci";
74			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
75			interrupt-names = "rxi", "txi", "tei", "eri";
76			reg = <0x400700c0 0x20>;
77			clocks = <&pclka MSTPB 25>;
78			status = "disabled";
79			uart {
80				compatible = "renesas,ra-sci-uart";
81				channel = <6>;
82				status = "disabled";
83			};
84		};
85
86		sci7: sci7@400700e0 {
87			compatible = "renesas,ra-sci";
88			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
89			interrupt-names = "rxi", "txi", "tei", "eri";
90			reg = <0x400700e0 0x20>;
91			clocks = <&pclka MSTPB 24>;
92			status = "disabled";
93			uart {
94				compatible = "renesas,ra-sci-uart";
95				channel = <7>;
96				status = "disabled";
97			};
98		};
99
100		iic2: iic2@40053200 {
101			compatible = "renesas,ra-iic";
102			channel = <2>;
103			reg = <0x40053200 0x100>;
104			status = "disabled";
105		};
106
107		usbhs: usbhs@40060000 {
108			compatible = "renesas,ra-usb";
109			reg = <0x40060000 0x2000>;
110			interrupts = <54 12>, <55 12>, <56 12>;
111			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
112			num-bidir-endpoints = <10>;
113			phys = <&usbhs_phy>;
114			status = "disabled";
115			udc {
116				compatible = "renesas,ra-udc";
117				status = "disabled";
118			};
119		};
120
121		adc@4005c000 {
122			channel-count = <13>;
123			channel-available-mask = <0x1f00ff>;
124		};
125
126		adc@4005c200 {
127			channel-count = <11>;
128			channel-available-mask = <0xf00ef>;
129		};
130
131		pwm13: pwm13@40078d00 {
132			compatible = "renesas,ra-pwm";
133			divider = <RA_PWM_SOURCE_DIV_1>;
134			channel = <RA_PWM_CHANNEL_13>;
135			clocks = <&pclkd MSTPD 6>;
136			reg = <0x40078d00 0x100>;
137			#pwm-cells = <3>;
138			status = "disabled";
139		};
140	};
141
142	clocks: clocks {
143		#address-cells = <1>;
144		#size-cells = <1>;
145
146		xtal: clock-main-osc {
147			compatible = "renesas,ra-cgc-external-clock";
148			clock-frequency = <DT_FREQ_M(24)>;
149			#clock-cells = <0>;
150			status = "disabled";
151		};
152
153		hoco: clock-hoco {
154			compatible = "fixed-clock";
155			clock-frequency = <DT_FREQ_M(20)>;
156			#clock-cells = <0>;
157		};
158
159		moco: clock-moco {
160			compatible = "fixed-clock";
161			clock-frequency = <DT_FREQ_M(8)>;
162			#clock-cells = <0>;
163		};
164
165		loco: clock-loco {
166			compatible = "fixed-clock";
167			clock-frequency = <32768>;
168			#clock-cells = <0>;
169		};
170
171		subclk: clock-subclk {
172			compatible = "renesas,ra-cgc-subclk";
173			clock-frequency = <32768>;
174			#clock-cells = <0>;
175			status = "disabled";
176		};
177
178		pll: pll {
179			compatible = "renesas,ra-cgc-pll";
180			#clock-cells = <0>;
181
182			/* PLL */
183			clocks = <&xtal>;
184			div = <2>;
185			mul = <20 0>;
186			status = "disabled";
187		};
188
189		pclkblock: pclkblock@4001e01c {
190			compatible = "renesas,ra-cgc-pclk-block";
191			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
192			      <0x40047008 4>;
193			reg-names = "MSTPA", "MSTPB","MSTPC",
194				    "MSTPD";
195			#clock-cells = <0>;
196			clocks = <&pll>;
197			status = "okay";
198
199			iclk: iclk {
200				compatible = "renesas,ra-cgc-pclk";
201				div = <2>;
202				#clock-cells = <2>;
203				status = "okay";
204			};
205
206			pclka: pclka {
207				compatible = "renesas,ra-cgc-pclk";
208				div = <2>;
209				#clock-cells = <2>;
210				status = "okay";
211			};
212
213			pclkb: pclkb {
214				compatible = "renesas,ra-cgc-pclk";
215				div = <4>;
216				#clock-cells = <2>;
217				status = "okay";
218			};
219
220			pclkc: pclkc {
221				compatible = "renesas,ra-cgc-pclk";
222				div = <4>;
223				#clock-cells = <2>;
224				status = "okay";
225			};
226
227			pclkd: pclkd {
228				compatible = "renesas,ra-cgc-pclk";
229				div = <2>;
230				#clock-cells = <2>;
231				status = "okay";
232			};
233
234			bclk: bclk {
235				compatible = "renesas,ra-cgc-pclk";
236				div = <2>;
237				bclkout: bclkout {
238					compatible = "renesas,ra-cgc-busclk";
239					clk-out-div = <2>;
240					sdclk = <1>;
241					#clock-cells = <0>;
242				};
243				#clock-cells = <2>;
244				status = "okay";
245			};
246
247			uclk: uclk {
248				compatible = "renesas,ra-cgc-pclk";
249				div = <5>;
250				#clock-cells = <2>;
251				status = "okay";
252			};
253
254			fclk: fclk {
255				compatible = "renesas,ra-cgc-pclk";
256				div = <4>;
257				#clock-cells = <2>;
258				status = "okay";
259			};
260
261			clkout: clkout {
262				compatible = "renesas,ra-cgc-pclk";
263				#clock-cells = <2>;
264				status = "disabled";
265			};
266		};
267	};
268
269	usbhs_phy: usbhs-phy {
270		compatible = "renesas,ra-usbphyc";
271		#phy-cells = <0>;
272	};
273};
274
275&ioport0 {
276	port-irqs = <&port_irq6 &port_irq7 &port_irq8
277	&port_irq9 &port_irq10 &port_irq11
278	&port_irq12 &port_irq13 &port_irq14>;
279	port-irq-names = "port-irq6",
280			 "port-irq7",
281			 "port-irq8",
282			 "port-irq9",
283			 "port-irq10",
284			 "port-irq11",
285			 "port-irq12",
286			 "port-irq13",
287			 "port-irq14";
288	port-irq6-pins = <0>;
289	port-irq7-pins = <1>;
290	port-irq8-pins = <2>;
291	port-irq9-pins = <4>;
292	port-irq10-pins = <5>;
293	port-irq11-pins = <6>;
294	port-irq12-pins = <8>;
295	port-irq13-pins = <9 15>;
296	port-irq14-pins = <10>;
297};
298
299&ioport1 {
300	port-irqs = <&port_irq0 &port_irq1 &port_irq2
301	&port_irq3 &port_irq4>;
302	port-irq-names = "port-irq0",
303			 "port-irq1",
304			 "port-irq2",
305			 "port-irq3",
306			 "port-irq4";
307	port-irq0-pins = <5>;
308	port-irq1-pins = <1 4>;
309	port-irq2-pins = <0>;
310	port-irq3-pins = <10>;
311	port-irq4-pins = <11>;
312};
313
314&ioport2 {
315	port-irqs = <&port_irq0 &port_irq1 &port_irq2
316	&port_irq3>;
317	port-irq-names = "port-irq0",
318			 "port-irq1",
319			 "port-irq2",
320			 "port-irq3";
321	port-irq0-pins = <6>;
322	port-irq1-pins = <5>;
323	port-irq2-pins = <3 13>;
324	port-irq3-pins = <2 12>;
325};
326
327&ioport3 {
328	port-irqs = <&port_irq5 &port_irq6
329	&port_irq8 &port_irq9>;
330	port-irq-names = "port-irq5",
331			 "port-irq6",
332			 "port-irq8",
333			 "port-irq9";
334	port-irq5-pins = <2>;
335	port-irq6-pins = <1>;
336	port-irq8-pins = <5>;
337	port-irq9-pins = <4>;
338};
339
340&ioport4 {
341	port-irqs = <&port_irq0 &port_irq4 &port_irq5
342	&port_irq6 &port_irq7 &port_irq8
343	&port_irq9>;
344	port-irq-names = "port-irq0",
345			 "port-irq4",
346			 "port-irq5",
347			 "port-irq6",
348			 "port-irq7",
349			 "port-irq8",
350			 "port-irq9";
351	port-irq0-pins = <0>;
352	port-irq4-pins = <2 11>;
353	port-irq5-pins = <1 10>;
354	port-irq6-pins = <9>;
355	port-irq7-pins = <8>;
356	port-irq8-pins = <15>;
357	port-irq9-pins = <14>;
358};
359
360&ioport5 {
361	port-irqs = <&port_irq11 &port_irq12 &port_irq14
362	&port_irq15>;
363	port-irq-names = "port-irq11",
364			 "port-irq12",
365			 "port-irq14",
366			 "port-irq15";
367	port-irq11-pins = <1>;
368	port-irq12-pins = <2>;
369	port-irq14-pins = <5 12>;
370	port-irq15-pins = <6 11>;
371};
372
373&ioport7 {
374	port-irqs = <&port_irq7 &port_irq8 &port_irq10
375	&port_irq11>;
376	port-irq-names = "port-irq7",
377			 "port-irq8",
378			 "port-irq10",
379			 "port-irq11";
380	port-irq7-pins = <6>;
381	port-irq8-pins = <7>;
382	port-irq10-pins = <9>;
383	port-irq11-pins = <8>;
384};
385